CN101789118B - Drawing data access system and method - Google Patents

Abstract

A drawing data access system. The drawing data access system comprises a main memory controller for accessing a main memory; and a graphics cache controller for receiving an access instruction. The mapping cache controller maps a virtual address corresponding to the access instruction to a physical address according to the mapping address mapping table, and maps the physical address to one of a plurality of states according to the mapping address state table; the graphics cache controller accesses a graphics data corresponding to the access instruction from a memory of a processor or a main memory according to the state selection.

Description

Drawing data access system and method

technical field

The present invention relates to a drawing data access system and method, and more particularly to a drawing data access system and method that avoids accessing drawing data through a snooping path to improve efficiency.

Background technique

In today's computer systems, there is often a dedicated cache (cache memory or cache) in the processor or graphics module. Different from the main memory (also known as system memory) located outside the processor or graphics module, the cache is a small memory used to store frequently used program codes and data, which can enhance the processor or graphics module to access data speed. However, there is naturally a problem of cache coherence between the processor and the graphics module sharing a main memory, and generally speaking, snoop transaction and non-snoop transaction are often used ) parallel approach to overcome it.

FIG. 1 is a schematic diagram of a cache architecture between a central processing unit (CPU) 110 and a graphics module 160 in the prior art. The computer system 100 includes a CPU 110, a main memory 120, a north bridge chip 180 and a graphics module 160, and the north bridge chip includes a front side bus interface 130, a main memory controller 140, and a graphics module interface 150. In another embodiment, the graphics module 160 can also be included in the north bridge chip.

In the CPU 110, as mentioned above, there is a CPU cache 112 for increasing the access speed of the CPU 110. The main memory 120 has a plurality of physical addresses, and stores various data respectively. The front side bus interface 130 is coupled to the CPU 110 as an interface between the CPU 110 and the graphics module 160. The front side bus interface 130 can also be connected to other devices in the computer system 100 in addition to managing the communication between the CPU 110 and the graphics module 160. For example, South Bridge chip, PCI and other devices (not shown in the figure). The main memory controller 140 is coupled to the main memory 120 and the FSB interface 130 . The graphics module interface 150 is an interface between the main memory controller 140 and the graphics module 160 . As mentioned above, the graphics module 160 has a graphics cache 162 to increase the access speed of the graphics module 160 .

In the prior art, when the drawing module 160 receives an access instruction, it will refer to the drawing address mapping table GAMT (Graphics Address Mapping Table, GAMT) in the drawing cache 162, and the virtual address corresponding to the access instruction ( Virtual Address) into a physical address (Physical Address). Wherein, the complete drawing address mapping table GAMT is stored in the main memory 120, and the drawing module 160 will retrieve the drawing address mapping table GAMT in the main memory 120, and store the more frequently used part of the table in the drawing cache 162 for use. FIG. 2 is a schematic diagram of a drawing address mapping table. For example, each entry in the graphics address mapping table includes 6 columns. The first column VA records the virtual address, which is usually 16K bytes in size; the next four columns PA0~PA 3 point to four physical addresses with a size of about 4K bytes; and the last column LRU is usually used to record recent The least recently used (Least Recently Used) physical address information, when the drawing cache 162 space is not enough, the least used item in the drawing address mapping table will be replaced according to the information provided by the LRU. It should be noted that, in each physical address column, there is a snoop bit for indicating whether the data of the physical address exists in the CPU cache 112 or not. For example, when the graphics module 160 receives an access instruction, it will check the physical address corresponding to the access instruction. If the monitoring bit of the physical address is 1 (can be cached), it means that in the CPU cache 112 of the CPU 110 There may be data corresponding to the physical address, then the drawing module 160 will send a request to the CPU 110 through the front side bus interface 130 to access the data corresponding to the physical address, or monitor and judge the high speed of the CPU at the front side bus interface 130 When the cache 112 does not have the data, the data is accessed again through the main memory controller 140 to the main memory 120 (the above paths are collectively referred to as monitoring path A). If the monitoring bit is 0 (not cacheable), it means that the data must not exist in the CPU cache 112. At this time, the drawing module 160 will send a request to the main memory 120 through the drawing module interface 150 and the main memory controller 140. And access the data in the main memory 120 (this path is called non-monitoring path B).

However, when the request for access by the graphics module 160 is sent through the monitoring path A, since the FSB interface 130 additionally manages other devices, such as: south bridge chip, PCI, or other devices, the request sent by the graphics module 160 must be communicated with other devices. Waiting with the request sent. Afterwards, the FSB interface 130 begins to perform operations such as bus protocol snooping on the CPU 110, and changes to the main memory 120 to access data when it is known that there is no such data in the CPU cache 112. Therefore, relatively speaking, the time consumed by monitoring path A will be much longer than the non-monitoring path B that directly accesses the main memory 120 through the graphics module interface 150 and the main memory controller 140. The cumulative time spent will adversely affect system performance.

Contents of the invention

The purpose of the present invention is to reduce the cumulative time consumed by monitoring paths in the prior art for drawing data access by continuously tracking the data status, thereby improving the performance of the drawing system.

The invention provides a drawing data access system, which includes: a main memory controller and a drawing cache controller. Wherein the main memory controller is coupled to a main memory with multiple physical addresses for directly accessing the main memory; and the graphics cache controller is coupled to the main memory controller for receiving an access command . The graphics cache controller includes a graphics address mapping table (GraphicsAddress Mapping Table, GAMT) and a graphics address state table. The drawing cache controller maps a virtual address corresponding to the access instruction to a physical address according to the drawing address mapping table, and re-maps the physical address to a state among a plurality of states according to the drawing address state table . Then, the graphics cache controller selects to access from a processor's memory or the main memory according to the state.

The present invention also provides a drawing data access method, including: receiving an access instruction; mapping a virtual address corresponding to the access instruction to a physical address according to a drawing address mapping table; The physical address is re-mapped to a state in a plurality of states; and a drawing data corresponding to the access command is selected to be accessed from a processor memory or a main memory according to the state.

Description of drawings

FIG. 1 is a schematic diagram of the cache architecture between the CPU 110 and the graphics module 160 in the prior art;

FIG. 2 is a schematic diagram of a drawing address mapping table;

FIG. 3 is a drawing data access system 300 according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the drawing address mapping table GAMT and a drawing address state table GAST;

FIG. 5 is a flowchart of a drawing data access method according to another embodiment of the present invention;

FIG. 6 is a detailed flowchart of step S530 in the drawing data access method ( FIG. 5 ) according to another embodiment of the present invention.

[Description of main component labels]

100～computer system; 110～CPU;

112～CPU cache; 120～main memory;

130～front side bus interface; 140～main memory controller;

150～drawing module interface; 160～drawing module;

162～drawing cache; 180～Northbridge chip;

GAMT～drawing address mapping table; 300～drawing data access system;

310～CPU; 312～CPU cache memory;

320～main memory; 330～front side bus interface;

340～main memory controller; 350～graphic module interface;

360～drawing module; 362～drawing cache controller;

380～North Bridge Chip; GAMT～Drawing Address Mapping Table;

GAST～drawing address state table; S510～S540～steps;

S610～S670～steps.

Detailed ways

The following describes the preferred embodiment of the present invention. Each embodiment is used to illustrate the principles of the present invention, but not to limit the present invention. The scope of the present invention should be determined by the appended claims.

FIG. 3 is a drawing data access system 300 according to an embodiment of the present invention. The drawing data access system 300 of the present invention includes a CPU 310, a main memory 320, a north bridge chip 380 and a drawing module 360. The north bridge chip 380 includes a front side bus interface 330 , a main memory controller 340 , and a graphics module interface 350 . In the CPU 310, there is a CPU cache 312 for increasing the access speed of the CPU 310. The main memory 320 has multiple physical addresses, and stores various data respectively, including storing a Graphics Address Mapping Table (GAMT). The FSB interface 330 is coupled to the CPU 310 for monitoring (snoop) the CPU 310 accessing the main memory 120. The main memory controller 340 is coupled to the main memory 320 and the FSB interface 330 and is mainly used for directly accessing the main memory 320 . The graphics module interface 350 is an interface between the main memory controller 340 and the graphics module 360 . The graphics module 360 includes a graphics cache controller 362, which is coupled to the front side bus interface 330, and is coupled to the main memory controller 340 through the graphics module interface 350, for receiving an access command R/W (read or Write), and select to access data from the CPU cache 312 or the main memory 320 according to the physical address corresponding to the access command R/W. In this embodiment, the above-mentioned graphics module 360 is located outside the north bridge chip 380 . In another embodiment, the graphics module 360 can also be located in the north bridge chip 380 . However, in other embodiments, the invention is not necessarily so limited.

The graphics cache controller 362 of the present invention includes a graphics address state table GAST in addition to a graphics address mapping table GAMT. The graphics cache controller 362 retrieves the complete graphics address mapping table GAMT stored in the main memory 320 , and stores the more frequently used part of the table in the graphics cache controller 362 for use. FIG. 4 is a schematic diagram of the graphics address mapping table GAMT and a graphics address status table GAST. Please also refer to Figure 3. The graphics cache controller 362 can map a virtual address VA corresponding to the access instruction R/W to a physical address PA according to the graphics address mapping table GAMT, and then remap the physical address PA to a physical address PA according to the graphics address state table GAST. state. Since one virtual address VA may be mapped to multiple physical addresses PA, for example, in this embodiment, a 16K virtual address VA_0 can be mapped to four 4K physical addresses PA_00-PA_03 respectively, and the drawing cache control The controller 362 can check whether the data corresponding to the selected physical address PA is correct by drawing the information in the tag column (Tag) in the address state table GAST.

In addition, in another embodiment of the present invention, the drawing address mapping table GAMT may include an LRU (LeastRecently Used) field, which is usually used to record the information of the least recently used virtual address. When the drawing cache 362 space is not enough, it will follow The information provided by this LRU replaces the least used one of the entries in the drawing address mapping table GAMT.

The drawing cache controller 362 selects a data access path according to the state corresponding to the physical address PA, and accesses drawing data corresponding to the access command R/W. In the present invention, by defining different states according to different physical addresses according to their usage conditions, it is possible to greatly reduce the graphics cache controller 362's monitoring (snoop) processor through the front side bus interface 330 (such as the monitoring path in the prior art). A), and adopt the non-monitoring path B (the way of accessing the main memory 320 through the graphics module interface 350 and the main memory controller 340) to replace the monitoring path A, thereby improving the efficiency of drawing data access.

In a preferred embodiment, the states in the graphics address state table GAST may include: an initial state, a shared state and a modified state. Each state is set as follows:

(1) Initial state: when an item of the drawing address state table GAST is initialized or invalidated, or when no physical address is registered, the item is registered as the initial state I, as shown in FIG. 4 .

(2) Shared state: when a physical address (such as PA_00) in the drawing address mapping table GAMT is registered in the drawing address state table GAST for the first time, the physical address PA_00 is registered as a shared state S in the drawing address state table GAST.

(3) Correction state: if the drawing data corresponding to a physical address (such as PA_11) in the drawing address mapping table GAMT has been accessed by the drawing cache controller 362, no matter through the monitoring path A or the non-monitoring path B, Then the physical address PA_11 is registered as the modified state M in the drawing address state table GAST. The mechanism of how the present invention modifies the shared state S to the modified state M will be described in detail later.

Next, the functions of the drawing cache controller 362 of the present invention will be described. In one embodiment, after receiving the access command R/W0, the graphics cache controller 362 can convert the virtual address VA_0 corresponding to the access command R/W0 into a physical address PA_00 according to the graphics address mapping table GAMT. Because the physical address PA_00 is registered in the drawing address state table GAST for the first time and has not been accessed by other access commands, the physical address PA_00 is registered as the shared state S in the drawing address state table GAST. Thereafter, since the physical address PA_00 has not been accessed or updated, in order to maintain the cache data consistency between the graphics module 360 and the CPU 310, the graphics cache controller 362 will choose to use the FSB interface 330 ( Monitoring path A) performs data access. Afterwards, the FSB interface 330 will further monitor the CPU 310. In one case, when the data to be accessed in the CPU cache 312 of the CPU 310 is not invalid, the FSB interface 330 will access the CPU cache 312. In another case, when the FSB interface 330 finds that the data to be accessed in the CPU cache 312 has been invalidated, the FSB interface 330 changes to the access command R/W in the main memory 320 through the main memory controller 340. The drawing data is accessed on the corresponding physical address PA_00. In any case, after accessing the drawing data, the drawing module 360 invalidates the drawing data corresponding to the access command R/W0 in the CPU cache 312 to maintain cache data consistency. As mentioned above, after the physical address PA_00 is accessed, the state will no longer be the shared state S, but will change to the modified state M.

In another embodiment, after receiving the access command R/W1, the drawing cache controller 362 finds that the physical address PA_11 converted from the virtual address VA_1 corresponding to the access command R/W1 has been registered in the drawing address state table GAST , and its state has been registered as the modified state M, so it is known that the physical address PA_11 has been used by other access commands to access data. Therefore, the graphics cache controller 362 can choose to directly access the graphics data located at the physical address PA_11 in the main memory 320 through the graphics module interface 350 and the main memory controller 340 (non-monitoring path B). In this way, according to the drawing data access system of the present invention, only the physical address accessed for the first time will be accessed through the monitoring path A, and most of the access operations will be performed through the non-monitoring path B, thereby reducing the number of physical addresses accessed through the monitoring path A. Monitor the cumulative time consumed by routing access to drawing data, thereby improving the performance of the drawing system.

It should be noted that, in order to maintain the cache data consistency between the CPU 310 and the drawing module 360, in a preferred embodiment, the drawing data access system 300 of the present invention may additionally include a dedicated drawing monitoring bus (path C ). The drawing monitoring bus is coupled between the front side bus interface 330 and the drawing cache controller 362. When the CPU 310 accesses drawing data to the cache memory in the main memory 320 or other devices, the CPU 310 can pass the drawing monitoring bus ( Path C), invalidate the physical address of the drawing data corresponding to the drawing address state table GAST in the drawing cache controller 362, or modify the state of the corresponding physical address of the drawing data in the drawing address state table GAST to share state S. In the case of not using the drawing monitor bus (path C), the update data of the drawing cache controller 362 by the CPU 310 can be transmitted through the original pipeline (path A or path B), and the data flow burden of the pipeline will be relatively heavy. Therefore, the drawing data access system 300 having a dedicated drawing monitor bus can also enable the present invention to obtain higher drawing data access performance compared with the prior art.

In addition, in one embodiment of the present invention, when the storage space of the drawing address mapping table GAMT is insufficient, the drawing cache controller 362 can replace the drawing address mapping table according to the information provided by the Least Recently Used (Least Recently Used) field LRU An item that is least used in the GAMT, and the graphics cache controller 362 will invalidate the physical address of the item that should be replaced in the graphics address state table GAST.

It is worth mentioning that the number of states set in the graphics address state table GAST of the present invention is not limited to the three types of "initial state", "shared state" and "modified state". In addition, those skilled in the art can also integrate or change the graphics address mapping table GAMT and the graphics address status table GAST according to the spirit of the present invention, or even reduce or add more fields for various purposes.

In addition to the above drawing data access system, the present invention also provides a drawing data access method. FIG. 5 is a flowchart of a drawing data access method according to another embodiment of the invention. Similar to the foregoing description, the drawing data access method of the present invention can be applied to a computer system, please refer to FIGS. 3 and 4 together. In step S510 , the graphics cache controller 362 can map a virtual address VA corresponding to an access command to a physical address PA according to a graphics address mapping table GAMT. In step S520, the drawing cache controller 362 can remap the physical address PA to a state among a plurality of states according to a drawing address state table GAST, and these states can be an initial state I, a shared state S , and a modified state M. Please refer to FIG. 4 and FIG. 5 together. Wherein, when an item in the drawing address state table GAST is after initialization or being invalidated, or when not registering any physical address, then this item is registered as initial state I; When a physical address in the drawing address mapping table GAMT (such as When PA_00) is registered in the drawing address state table GAST for the first time, the physical address PA_00 is registered as the shared state S in the drawing address state table GAST; and when a physical address (such as PA_11) in the drawing address state table GAST corresponds The drawing data of the drawing has been accessed by the drawing cache controller 362, then the physical address PA_11 is registered as the modified state M in the drawing address state table GAST. Thereafter, in step S530, the drawing cache controller 362 selects to access the drawing data corresponding to the access instruction from the CPU cache 312 through the front side bus interface 330 according to the state of the physical address PA mapping, or selects to use the drawing The module interface 350 and the main memory controller 340 access the drawing data corresponding to the access command from the main memory 320 .

FIG. 6 is a detailed flowchart of step S530 in the drawing data access method ( FIG. 5 ) according to another embodiment of the present invention. Step S530 further includes: in step S610, judging whether the physical address corresponding to the access command is registered in the graphics address status table GAST. If the registered state is the shared state S, go to step S620 and choose to access data through the FSB interface 330 (monitoring path A). If the registered state is the modified state M, then go to step S630 and choose to access the drawing data corresponding to the physical address in the main memory 320 through the main memory controller 340 (non-monitoring path B).

The above step S620 is further divided into two situations. In step S640, after monitoring the CPU 310, the FSB interface 330 determines whether the drawing data corresponding to the physical address in the CPU cache 312 of the CPU 310 is invalid. If the corresponding drawing data in the CPU cache 312 is not invalid, go to step S650 to access the drawing data in the CPU cache 312 . If the corresponding drawing data in the CPU cache 312 is invalid, go to step S660 and choose to access the drawing data in the main memory 320 through the main memory controller 340 . After accessing the drawing data, steps S650 and S660 both proceed to step S670. In step S670 , the FSB interface 330 invalidates the drawing data corresponding to the physical address in the CPU cache 312 , and modifies the state corresponding to the drawing data in the drawing address state table GAST to the modified state M.

Finally, in an ideal embodiment, in order to maintain the cache data consistency between the CPU 310 and the drawing module 360, the drawing data access method of the present invention further includes: When the high-speed cache accesses a drawing data, then CPU 310 invalidates the physical address corresponding to the drawing data on the drawing address state table GAST table in the drawing module 360 (by path C), or the physical address corresponding to the drawing data The state of the address is changed to shared state S.

In this way, according to the drawing data access method of the present invention, only the physical address accessed for the first time will access the corresponding drawing data through the monitoring path A, and most of the access operations will be stored through the non-monitoring path B. Therefore, it can reduce the cumulative time consumed by accessing the drawing data through the monitoring path, thereby improving the performance of the drawing system.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. mapping data accessing system comprises:

One main memory controller couples the primary memory with a plurality of physical addresss, in order to this primary memory of access; And

One draws gets controller soon, is coupled to this main memory controller, and this drawing is got controller soon and comprised:

One drawing address mapping table; And

One drawing address state table;

Wherein this drawing is got controller soon in order to receive an access instruction; According to this drawing address mapping table with the pairing virtual address map of this access instruction to a physical address; Again according to this drawing address state table with the state of this physical address map in a plurality of states; And select the pairing draw data of this access instruction of access from the storer of a processor or this primary memory according to this state

Wherein these a plurality of states comprise at least:

One original state, one in this drawing address state table after initialization or being disabled, or when not having any physical address of login, then this is registered as this original state;

One shares state, when one first physical address in this drawing address mapping table is logined to this drawing address state table first, then in this drawing address state table, this first physical address is registered as this shared state; And

It is out-of-date that one correction state, the pairing draw data of one second physical address in this drawing address state watch are once got the controller access by this drawing soon, in this drawing address state table, is this correction state with this second physics address registration then.

2. mapping data accessing system according to claim 1, wherein,

Get controller soon when this drawing and receive this access instruction; And when pairing this physical address of this access instruction is registered as this shared state in this drawing address state table; Then this draw data that controller selects to be positioned at through a front-side bus interface access storer of this processor is got in this drawing soon, and wherein this front-side bus interface is in order to keep watch on the also storer of this processor of access; And

Get controller soon when this drawing and receive this access instruction; And when pairing this physical address of this access instruction was registered as this correction state in this drawing address state table, then this draw data that controller selects to be positioned at through this main memory controller access this primary memory was got in this drawing soon.

3. mapping data accessing system according to claim 2; Wherein this drawing get soon controller behind the storer of this processor of access with this draw data ineffective treatment in the storer of this processor, and in should drawing address state table the status modifier of this physical address that should draw data be become should the correction state.

4. mapping data accessing system according to claim 2; Wherein this front-side bus interface is coupled to this main memory controller; When this draw data after this front-side bus interface is kept watch on the storer of this processor in the storer of this processor of discovery had lost efficacy, this front-side bus interface was positioned at this draw data of this primary memory through this main memory controller access.

5. mapping data accessing system according to claim 1; Also comprise a drawing monitor bus; Be coupled to a front-side bus interface and this drawing is got between the controller soon; When another draw data of this processor access, this processor makes in this drawing address state table the status modifier to physical address that should another draw data become this shared state or ineffective treatment through this drawing monitor bus.

6. draw data access method comprises:

According to a drawing address mapping table with the pairing virtual address map of an access instruction to a physical address;

According to a drawing address state table with the state of this physical address map in a plurality of states; And

Select the pairing draw data of this access instruction of access from the storer of a processor or a primary memory according to this state,

Wherein these a plurality of states comprise at least:

One original state, one in this drawing address state table after initialization or being disabled, or when not having any physical address of login, then this is registered as this original state;

One shares state, when one first physical address in this drawing address mapping table is logined to this drawing address state table first, then in this drawing address state table, this first physical address is registered as this shared state; And

One correction state, the pairing draw data of one second physical address in this drawing address state table was once out-of-date by access, in this drawing address state table, was this correction state with this second physics address registration then.

7. draw data access method according to claim 6 also comprises:

When pairing this physical address of this access instruction is registered as this shared state in this drawing address state table, then be positioned at this draw data of the storer of this processor through a front-side bus interface access; And

When pairing this physical address of this access instruction is registered as this correction state in this drawing address state table, then be positioned at this draw data of this primary memory through a main memory controller access.

8. draw data access method according to claim 7; Wherein behind the storer of this processor of access; With this draw data ineffective treatment of the storer of this processor, and in should drawing address state table the status modifier of this physical address that should draw data be become should the correction state.

9. draw data access method according to claim 7; When finding when the storer of this processor of access that wherein this draw data in the storer of this processor had lost efficacy, be positioned at this draw data of this primary memory through a main memory controller access.

10. draw data access method according to claim 6 also comprises:

When another draw data of a processor access, the status modifier to physical address that should another draw data in this drawing address state table is become this shared state or ineffective treatment.

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