CN101777302A - Display circuit and display for a display - Google Patents
Display circuit and display for a display Download PDFInfo
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- CN101777302A CN101777302A CN 201010129457 CN201010129457A CN101777302A CN 101777302 A CN101777302 A CN 101777302A CN 201010129457 CN201010129457 CN 201010129457 CN 201010129457 A CN201010129457 A CN 201010129457A CN 101777302 A CN101777302 A CN 101777302A
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Abstract
The invention provides a display circuit for a display and the display. The display comprises a grid driving device, a data driving device and a display circuit. The display circuit has at least one display unit having four pixels. Each pixel has two sub-pixels, and each sub-pixel has a transistor and is coupled to a pixel electrode. The transistors of the two sub-pixels of each pixel are electrically connected to the data driving device in a serial connection mode. The transistors of the two sub-pixels of each pixel are respectively electrically connected to the gate driving device to receive the signal of the gate driving device, wherein the signal of the gate driving device is used as a switching signal for receiving the data signal provided by the data driving device. The display circuit of the invention utilizes two sub-pixels of each pixel to be connected in series to receive the same data voltage and matches with the pixel arrangement mode and the connection relation between the data line and the gate line as well as the pixel, thereby reducing the number of the data lines required by the whole and reducing the power consumption of the electronic display.
Description
Technical field
Display circuit and the display of the present invention about being used for a display, more specifically, display circuit of the present invention is with two sub-pixel serial connections, to see through single data line acceptance, make the whole required data line number of display circuit be reduced to half of existing display circuit by the data voltage that a data driven unit is provided.
Background technology
Along with electronics shows scientific and technological progress, various electronic console is used in the daily life in a large number, and its display quality also more and more meets people's demand.Electronic console is to present image by a plurality of display units that control is arranged in the matrix pattern, and wherein each pixel all has a transistor and a pixel electrode.The transistor of each pixel is connected to different data lines respectively receiving a data voltage, and data voltage is conducted to pixel electrode, so that pixel is luminous.
Because the size of electronic console is done bigger and bigger now, to possess accurately and careful display quality for making the image that presents, the pixel quantity of display interior just needs proportional with the size of electronic console.Correspondingly, just need have the lot of data line to provide data voltage to each pixel.Thus, large-sized electronic console promptly exists the big shortcoming of power consumption.
Therefore, how to reduce the power consumption of electronic console, and keep its display quality simultaneously, and then promote the marketable value of electronic console, be the target that also need reach.
Summary of the invention
In view of the problem that prior art faced, a purpose of the present invention is to provide a kind of display and display circuit thereof.The display circuit utilization receiving same data voltage, and cooperates two sub-pixels of each pixel serial connection with the annexation of pixel arrangement mode and data line and gate line and pixel, reduces the required data line number of integral body, and then the power consumption of reduction electronic console.
For reaching above-mentioned purpose, the invention provides a kind of display, it comprises a kind of display circuit, a gate drive apparatus and a data driven unit.Gate drive apparatus is in order to produce a plurality of signals, data driven unit is then in order to produce the plurality of data signal, wherein these signals comprise a first grid signal, a second grid signal and one the 3rd signal, and these data-signals comprise one first data-signal, one second data-signal and one the 3rd data-signal.
This kind display circuit comprises a first grid polar curve, a second grid line, one the 3rd gate line, one first data line, one second data line, one the 3rd data line and at least one display unit.First grid polar curve is along delegation (row) direction setting and electrically connect gate drive apparatus, in order to receive the first grid signal.The second grid line follows direction and is set in parallel in the below of first grid polar curve and electrically connects gate drive apparatus, in order to receive the second grid signal.The 3rd gate line follows direction and be arranged in parallel, and is positioned at the below of second grid line, and the 3rd gate line electrically connects gate drive apparatus, in order to receive the 3rd signal.First data line is along row (column) direction setting and an electric connection data driven unit vertical with line direction, in order to receive first data-signal.Second data line is set in parallel in the left side of first data line and electrically connects data driven unit along column direction, and in order to receive second data-signal, wherein the polarity of second data-signal system is opposite with the polarity of first data-signal.The 3rd data line, be set in parallel in the left side of second data line and electrically connect data driven unit along column direction, in order to receive one the 3rd data-signal, wherein the polarity of the 3rd data-signal is opposite and identical with the polarity of first data-signal with the polarity of second data-signal.
In addition, display unit comprises one first pixel (pixel), one second pixel, one the 3rd pixel and one the 4th pixel.First pixel comprises a 1A sub-pixel (sub-pixel) and a 1B sub-pixel, the 1A sub-pixel comprises a 1A transistor (transistor), the 1A transistor comprises a 1A grid (gate), one 1A source electrode (source) and 1A drain electrode (drain), the 1B sub-pixel comprises a 1B transistor, the 1B transistor comprises a 1B grid, one 1B source electrode and 1B drain electrode, wherein the 1A sub-pixel is arranged at the left side of 1B sub-pixel along line direction, 1A source-coupled to the first data line, the 1A gate coupled is to the second grid line, 1A drain electrode and 1B source-coupled, the 1B gate coupled is to first grid polar curve.
Second pixel is arranged at the left side of first pixel along line direction, it comprises a 2A sub-pixel and a 2B sub-pixel, the 2A sub-pixel comprises a 2A transistor, the 2A transistor comprises a 2A grid, one 2A source electrode and 2A drain electrode, the 2B sub-pixel comprises a 2B transistor, the 2B transistor comprises a 2B grid, one 2B source electrode and 2B drain electrode, wherein the 2A sub-pixel is arranged at the right side of 2B sub-pixel along column direction, 2A source-coupled to the second data line, the 2A gate coupled is to the second grid line, 2A drain electrode and 2B source-coupled, the 2B gate coupled is to first grid polar curve.
The 3rd pixel is arranged at the below of first pixel along column direction, it comprises a 3A sub-pixel and a 3B sub-pixel, the 3A sub-pixel comprises a 3A transistor, the 3A transistor comprises a 3A grid, one 3A source electrode and 3A drain electrode, the 3B sub-pixel comprises a 3B transistor, the 3B transistor comprises a 3B grid, one 3B source electrode and 3B drain electrode, wherein the 3A sub-pixel is arranged at the right side of 3B sub-pixel along line direction, 3A source-coupled to the second data line, 3A gate coupled to the three gate lines, 3A drain electrode and 3B source-coupled, the 3B gate coupled is to the second grid line.
The 4th pixel is arranged at the left side of the 3rd pixel along line direction, and be arranged at the below of second pixel along column direction, it comprises a 4A sub-pixel and a 4B sub-pixel, the 4A sub-pixel comprises a 4A transistor, the 4A transistor comprises a 4A grid, one 4A source electrode and 4A drain electrode, the 4B sub-pixel comprises a 4B transistor, the 4B transistor comprises a 4B grid, one 4B source electrode and 4B drain electrode, wherein the 4A sub-pixel is arranged at the left side of 4B sub-pixel along line direction, 4A source-coupled to the three data lines, 4A gate coupled to the three gate lines, 4A drain electrode and 4B source-coupled, the 4B gate coupled is to the second grid line.
For reaching aforementioned purpose, display also can comprise another kind of display circuit.This display circuit comprises a first grid polar curve, a second grid line, one first data line and one first pixel.Gate line is adjacent and be arranged in parallel along delegation (row) direction, and data line is then along row (column) the direction setting vertical with described line direction.First pixel comprises a 1A sub-pixel and a 1B sub-pixel.The 1A sub-pixel comprises one first switch and one first pixel electrode, and first switch comprises a control end, one first end and one second end, the described control end of first switch is coupled in the second grid line, first end of first switch is coupled in first data line, and second end of first switch is coupled in first pixel electrode.The 1B sub-pixel comprises a second switch and one second pixel electrode, and second switch comprises a control end, one first end and one second end; The control end of second switch is coupled in first grid polar curve, and first end of second switch is coupled in first pixel electrode, and second end of second switch is coupled in second pixel electrode, and second pixel electrode is between first pixel electrode and first data line.
Display circuit utilization of the present invention is connected in series two sub-pixels of each pixel to receive same data voltage, and the annexation of cooperation pixel arrangement mode and data line and gate line and pixel, reduce whole required data line number, and then reduced the power consumption of electronic console.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, does not constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is the synoptic diagram of the display of one embodiment of the invention;
Fig. 2 is the synoptic diagram of display circuit of the display of one embodiment of the invention;
Fig. 3 is a grid voltage waveform that is used for display circuit of the present invention;
Fig. 4 is another grid voltage waveform that is used for display circuit of the present invention;
Fig. 5 is the another grid voltage waveform that is used for display circuit of the present invention;
Fig. 6 is a grid voltage waveform again that is used for display circuit of the present invention;
Fig. 7 A is a polarity of describing the pixel electrode of each sub-pixel of the present invention; And
Fig. 7 B is the brightness performance of describing the pixel electrode of each sub-pixel of the present invention.
[primary clustering symbol description]
1: display 11: gate drive apparatus
13: display circuit 15: data driven unit
135: display unit 135a: first pixel
135b: the second pixel 135c: the 3rd pixel
135d: the 4th pixel 1A: sub-pixel
1A1: transistor 1A1s: source electrode
1A1g: grid 1A1d: drain electrode
1A3: pixel electrode 1B: sub-pixel
1B1: transistor 1B1s: source electrode
1B1g: grid 1B1d: drain electrode
1B3: pixel electrode 2A: sub-pixel
2A1: transistor 2A1s: source electrode
2A1g: grid 2A1d: drain electrode
2A3: pixel electrode 2B: sub-pixel
2B1: transistor 2B1s: source electrode
2B1g: grid 2B1d: drain electrode
2B3: pixel electrode 3A: sub-pixel
3A1: transistor 3A1s: source electrode
3A1g: grid 3A1d: drain electrode
3A3: pixel electrode 3B: sub-pixel
3B1: transistor 3B1s: source electrode
3B1g: grid 3B1d: drain electrode
3B3: pixel electrode 4A: sub-pixel
4A1: transistor 4A1s: source electrode
4A1g: grid 4A1d: drain electrode
4A3: pixel electrode 4B: sub-pixel
4B1: transistor 4B1s: source electrode
4B1g: grid 4B1d: drain electrode
4B3: pixel electrode g1: first grid polar curve
G2: second grid line g3: the 3rd gate line
Gn-2: n-2 gate line gn-1: n-1 gate line
Gn: n gate line d1: first data line
D2: the second data line d3: the 3rd data line
Dm-2: m-2 data line dm-1: m-1 data line
Dm: m data line Sg1: first grid signal
Sg2: second grid signal Sg3: the 3rd signal
Sd1: the first data-signal Sd2: second data-signal
Sd3: the 3rd data-signal T: time variable
λ: fixed value
V0, V1, V2, V3, V4, V5: magnitude of voltage
T0, T1, T 2, T3, T 4, T5: time interval
Embodiment
The invention provides a kind of display and display circuit thereof.Below will explain content of the present invention, yet embodiments of the invention are not to need can implement as the described any environment of embodiment, application or mode in order to restriction the present invention through embodiment.Therefore, only be explaination purpose of the present invention about the explanation of embodiment, but not in order to direct restriction the present invention.Need the expositor, in following examples and the diagram, omit and do not illustrate with the non-directly related assembly of the present invention.
One embodiment of the invention as shown in Figure 1, it is the synoptic diagram of display 1 of the present invention.Display 1 comprises a gate drive apparatus 11, a display circuit 13 and a data driven unit 15.Gate drive apparatus 11 is in order to producing a plurality of signals, and see through a plurality of gate lines (be g1, g2, g3 ..., gn-1, gn-1, gn) provide these signals to display circuit 13.Data driven unit 15 is in order to produce the plurality of data signal, see through the plurality of data line (be d1, d2, d3 ..., dm-2, dm-1, dm) and provide these data-signals to display circuit 13.Because of the size restriction of the space of a whole page and for more clearly setting forth technology contents of the present invention, follow-up explanation and correlative type are only depicted local circuit (being following single display unit 135), part of grid pole line (being following gate line g1, g2, g3) and the segment data line (being following data line d1, d2, d3) of display circuit 13 as representative, and remainder then omits and do not show.
Further with reference to figure 2, its demonstration is used for the part of the display circuit 13 of display 1.Display circuit 13 comprises a first grid polar curve g1, a second grid line g2, one the 3rd gate line g3, one first data line d1, one second data line d2, one the 3rd data line d3, a plurality of display unit 135 and a common electrode (figure does not draw).First grid polar curve g1, second grid line g2 and the 3rd gate line g3 carry a first grid signal Sg1, a second grid signal Sg2 and one the 3rd signal Sg3 respectively secretly, and the first data line d1, the second data line d2 and the 3rd data line d3 carry one first data-signal Sd1, one second data-signal Sd2 and one the 3rd data-signal Sd3 respectively secretly.Energising is depressed into these display units 135 to common electrode in order to provide altogether.Each display unit 135 comprises four pixels, i.e. one first pixel 135a, one second pixel 135b, one the 3rd pixel 135c and one the 4th pixel 135d.As before described, for ease of understanding, and because of the size restriction of the space of a whole page, present embodiment Fig. 2 only shows single display unit 135, and whole display circuit repeats to extend for the local circuit of Fig. 2.When practical application, know the number of art technology person when visual increase in demand display unit.
As shown in Figure 2, first grid polar curve g1 is along delegation (row) direction setting, and sees through and be electrically connected to gate drive apparatus 11, receives a first grid signal Sg1 who is produced by gate drive apparatus 11 whereby.Second grid line g2 also follows the below that direction is set in parallel in first grid polar curve g1, and through being electrically connected to gate drive apparatus 11, receives a second grid signal Sg2 who is produced by gate drive apparatus 11 whereby.Similarly, the 3rd gate line g3 also follows the below that direction is set in parallel in second grid line g2, and through being electrically connected to gate drive apparatus 11 to receive one the 3rd signal Sg3 that is produced by gate drive apparatus 11.
The voltage waveform that voltage waveform such as Fig. 3 to Fig. 6 described of first grid signal Sg1, second grid signal Sg2 and the 3rd signal Sg3 one of them.In Fig. 3, the voltage waveform of each signal Sg1, Sg2, Sg3 all comprises one first interval T1, one second interval T2 and three kinds of time intervals of one the 3rd interval T3, wherein the magnitude of voltage of the first interval T1 is V1, and the magnitude of voltage of the second interval T2 is V2, and the magnitude of voltage of the 3rd interval T3 is V3.In addition, in Fig. 3, V1 and V3 are the accurate position of a high voltage, and V2 is the accurate position of a low-voltage, V1=V3＞V2 wherein, T1=T2, T3=2T1.In addition, anyly be familiar with that this operator can understand first grid signal Sg1, second grid signal Sg2 easily and the 3rd signal Sg3 has same waveform as, and only having a fixed difference each other on sequential (also is Sg2 (t-τ)=Sg1 (t) and Sg3 (t-τ)=Sg2 (t), wherein t is a time variable, τ is a fixed value), the relation between all the other signals is also same as described above.In addition, the relation between the signal that Fig. 4 to Fig. 6 described is also same as described above, so do not give unnecessary details in addition in subsequent paragraph.
In Fig. 4, the voltage waveform of each signal Sg1, Sg2, Sg3 all comprises one first interval T1, one second interval T2, one the 3rd interval T3, one the 4th interval T4 and one the 5th interval T5 equal time interval, wherein the magnitude of voltage of the first interval T1 is V1, the magnitude of voltage of the second interval T2 is V2, the magnitude of voltage of the 3rd interval T3 is V3, the magnitude of voltage of the 4th interval T4 is V4, and the magnitude of voltage of the 5th interval T5 is V4.In addition, in Fig. 4, V1, V3 and V5 are the accurate position of a high voltage, and V2 and V4 be the accurate position of a low-voltage, V1=V3=V5＞V2=V4 wherein, and T1＞＞λ, T2=(T1+2 λ), T3=(T1-λ), T4=2 λ, λ are a fixed value.
In Fig. 5, the voltage waveform of each signal Sg1, Sg2, Sg3 all comprises one first interval T1, one second interval T2 and one the 3rd interval T3 equal time interval, wherein the first interval T1 also can be divided into interval (T1-T0) interval that reaches of T0, the magnitude of voltage in T0 interval is V1, (T1-T0) Qu Jian magnitude of voltage is one to be decremented to the function of V0 in time by V1, the magnitude of voltage of the second interval T2 is V2, the 3rd interval T3 more can be divided into interval (T3-T0) interval that reaches of T0, the magnitude of voltage in T0 interval is V3, and (T3-T0) Qu Jian magnitude of voltage is one to be decremented to the function of V0 in time by V1.The magnitude of voltage of the 4th interval T4 is V4.In addition, in the 5th figure, V1, V3 and V4 are the accurate position of a high voltage, V2 is the accurate position of a low-voltage, and V0 is the voltage quasi position between accurate position of high voltage and the accurate interdigit of low-voltage, wherein V1=V3=V4＞V2, V1＞V0 〉=V2, T1=T2=T3=T4, T=T1-T0.
In Fig. 6, the voltage waveform of each signal Sg1, Sg2, Sg3 all comprises one first interval T1, one second interval T2, one the 3rd interval T3, one the 4th interval T4 and one the 5th interval T5 equal time interval, wherein the magnitude of voltage of the first interval T1 is V1, the magnitude of voltage of the second interval T2 is V2, the magnitude of voltage of the 3rd interval T3 is V3, the magnitude of voltage of the 4th interval T4 is V4, and the magnitude of voltage of the 5th interval T5 is V5.In addition, in Fig. 6, V1, V3 and V5 are the accurate position of a high voltage, and V2 and V4 be the accurate position of a low-voltage, V1=V3=V5＞V2=V4 wherein, T1=T3=T5, T2=2T1, T4＜T1.
The first data line d1 is along row (column) direction setting vertical with line direction, and sees through and be electrically connected to data driven unit 15, to receive the one first data-signal Sd1 that is produced by data driven unit 15.The second data line d2 is set in parallel in the left side of the first data line d1 along column direction, and sees through and be electrically connected to data driven unit 15, to receive the one second data-signal Sd2 that is produced by data driven unit 15.The 3rd data line d3 is set in parallel in the left side of the second data line d2 along column direction, and sees through electric connection data driven unit 15, to receive one the 3rd data-signal Sd3 that is produced by data driven unit 15.In the present invention, for the polarity between the first pixel 135a, the second pixel 135b, the 3rd pixel 135c and the 4th pixel 135d is operated in some conversions (dot inversion) mode, it is opposite with the polarity of the first data-signal Sd1 that the polarity of the second data-signal Sd2 is designed to, and the polarity of the 3rd data-signal Sd3 is designed to opposite with the polarity of the second data-signal Sd2, and it is identical with the polarity of the first data-signal Sd1, thus, with a design of inversion mode running, can further improve the power consumption problem by the polarity between pixel.
Among the present invention, each pixel all has two sub-pixels, wherein two sub-pixels can receive the data-signal that a data driven unit 15 is provided jointly in the serial connection mode, so display circuit 13 of the present invention at number of pixels with under the identical situation of prior art, can reduce the data line of half, and then reach the effect of power saving.The detailed circuit structure of each pixel, also be between sub-pixel annexation and and data line and gate line between annexation, then described in detail in subsequent paragraph.
The first pixel 135a comprises a sub-pixel (sub-pixel) 1A and a sub-pixel 1B, and sub-pixel 1A comprises a transistor (transistor) 1A1 and a pixel electrode 1A3.Transistor 1A1 comprises a grid (gate) 1A1g, one source pole (source) 1A1s and drain electrode (drain) 1A1d.Sub-pixel 1B comprises a transistor 1B1, and transistor 1B1 comprises a grid 1B1g, one source pole 1B1s and a drain electrode 1B1d.Sub-pixel 1A is arranged at the left side of sub-pixel 1B along line direction, and the source electrode 1A1s of transistor 1A1 is coupled to the first data line d1 accepting the first data-signal Sd1, and grid 1A1g is coupled to second grid line g2 and receives second grid signal Sg2 switching transistor 1A1 to see through.The source electrode 1B1s coupling of the drain electrode 1A1d of the transistor 1A1 of sub-pixel 1A and the transistor 1B1 of sub-pixel 1B is connected in series to reach the first data-signal Sd1 that the common reception first data line d1 is carried secretly sub-pixel 1A with sub-pixel 1B.Grid 1B1g is coupled to first grid polar curve g1 and receives first grid signal Sg1 switching transistor 1B1 to see through.
In addition, pixel electrode (pixel electrode) 1A3 is coupled to the drain electrode 1A1d of transistor 1A1, and the source electrode 1B1s of transistor 1B1 sees through the drain electrode 1A1d that pixel electrode 1A3 is coupled to transistor 1A1.Sub-pixel 1B comprises a pixel electrode 1B3, and the drain electrode 1B1d of transistor 1B1 is coupled to pixel electrode 1B3.In addition, sub-pixel 1A exists a liquid crystal capacitance (figure does not draw) and a storage capacitors (figure does not draw) to be coupled in parallel between pixel electrode 1A3 and common electrode.Similarly, sub-pixel 1B also exists a liquid crystal capacitance and a storage capacitors to be coupled in parallel between pixel electrode 1B3 and common electrode.
The second pixel 135b comprises a sub-pixel 2A and a sub-pixel 2B.Sub-pixel 2A comprises a transistor 2A1 and a pixel electrode 2A3.Transistor 2A1 comprises a grid 2A1g, one source pole 2A1s and a drain electrode 2A1d.Sub-pixel 2B comprises a transistor 2B1, and transistor 2B1 comprises a grid 2B1g, one source pole 2B1s and a drain electrode 2B1d.Sub-pixel 2A is arranged at the right side of sub-pixel 2B along line direction, and the source electrode 2A1s of transistor 2A1 is coupled to the second data line d2 receiving the second data-signal Sd2, and grid 2A1g is coupled to second grid line g2 and receives second grid signal Sg2 switching transistor 2A1 to see through.The source electrode 2B1s coupling of the drain electrode 2A1d of the transistor 2A1 of sub-pixel 2A and the transistor 2B1 of sub-pixel 2B is connected in series to reach to share sub-pixel 2A and receives the second data-signal Sd2 that the second data line d2 is carried secretly with sub-pixel 2B.Grid 2B1g is coupled to first grid polar curve g1 and receives first grid signal Sg1 switching transistor 2B1 to see through.
In addition, pixel electrode 2A3 is coupled to the drain electrode 2A1d of transistor 2A1, and the source electrode 2B1s of transistor 2B1 sees through the drain electrode 2A1d that pixel electrode 2A3 is coupled to transistor 2A1.Sub-pixel 2B comprises a pixel electrode 2B3, and the drain electrode 2B1d of transistor 2B1 is coupled to pixel electrode 2B3.Sub-pixel 2A exists a liquid crystal capacitance (figure does not draw) and a storage capacitors (figure does not draw) to be coupled in parallel between pixel electrode 2A3 and common electrode.Similarly, sub-pixel 2B also exists a liquid crystal capacitance and a storage capacitors to be coupled in parallel between pixel electrode 2B3 and common electrode.
The 3rd pixel 135c is arranged at the right side of the 4th pixel 135d and is arranged at the below of the first pixel 135a along column direction along line direction, and comprises a sub-pixel 3A and sub-pixel 3B.Sub-pixel 3A comprises a transistor 3A1 and a pixel electrode 3A3.Transistor 3A1 comprises a grid 3A1g, one source pole 3A1s and a drain electrode 3A1d.Sub-pixel 3B comprises a transistor 3B1, and transistor 3B1 comprises a grid 3B1g, one source pole 3B1s and a drain electrode 3B1d.Sub-pixel 3A is the right side that is arranged at sub-pixel 3B along line direction, and the source electrode 3A1s of transistor 3A1 is coupled to the second data line d2 receiving the second data-signal Sd2, and grid 3A1g is coupled to the 3rd gate line g3 to receive the 3rd signal Sg3 switching transistor 3A1 to see through.The drain electrode 3A1d of the transistor 3A1 of sub-pixel 3A is and the source electrode 3B1s coupling of the transistor 3B1 of sub-pixel 3B, sub-pixel 3A is connected in series with sub-pixel 3B to reach the second data-signal Sd2 that the common reception second data line d2 is carried secretly.Grid 3B1g is coupled to second grid line g2 and receives second grid signal Sg2 switching transistor 3B1 to see through.
In addition, pixel electrode 3A3 is coupled to the drain electrode 3A1d of transistor 3A1, and the source electrode 3B1s of transistor 3B1 sees through the drain electrode 3A1d that pixel electrode 3A3 is coupled to transistor 3A1.Sub-pixel 3B comprises a pixel electrode 3B3, and the drain electrode 3B1d of transistor 3B1 is coupled to pixel electrode 3B3.In addition, sub-pixel 3A exists a liquid crystal capacitance (figure does not draw) and a storage capacitors (figure does not draw) to be coupled in parallel between pixel electrode 3A3 and common electrode.Similarly, sub-pixel 3B also exists a liquid crystal capacitance and a storage capacitors to be coupled in parallel between pixel electrode 3B3 and common electrode.
The 4th pixel 135d is arranged at the below of the second pixel 135b and comprises a sub-pixel 4A and a sub-pixel 4B along column direction.Pixel 4A comprises a transistor 4A1 and a pixel electrode 4A3.Transistor 4A1 comprises a grid 4A1g, one source pole 4A1s and a drain electrode 4A1d.Sub-pixel 4B comprises a transistor 4B1, and transistor 4B1 comprises a grid 4B1g, one source pole 4B1s and a drain electrode 4B1d.Sub-pixel 4A is the left side that is arranged at sub-pixel 4B along line direction, and the source electrode 4A1s of transistor 4A1 is coupled to the 3rd data line d3 receiving the 3rd data-signal Sd3, and grid 4A1g is coupled to the 3rd gate line g3 to receive the 3rd signal Sg3 switching transistor 4A1 to see through.The drain electrode 4A1d of transistor 4A1 is and the source electrode 4B1s coupling of transistor 4B1, sub-pixel 4A is connected in series with sub-pixel 4B to reach the 3rd data-signal Sd3 that common reception the 3rd data line d3 is carried secretly.Grid 4B1g is coupled to second grid line g2 and receives second grid signal Sg2 switching transistor 4B1 to see through.
In addition, pixel electrode 4A3 is coupled to the drain electrode 4A1d of transistor 4A1, and the source electrode 4B1s of transistor 4B1 sees through the drain electrode 4A1d that pixel electrode 4A3 is coupled to transistor 4A1.Sub-pixel 4B comprises a pixel electrode 4B3, and the drain electrode 4B1d of transistor 4B1 is coupled to pixel electrode 4B3.In addition, sub-pixel 4A exists a liquid crystal capacitance (figure does not draw) and a storage capacitors (figure does not draw) to be coupled in parallel between pixel electrode 4A3 and common electrode.Similarly, sub-pixel 4B also exists a liquid crystal capacitance and a storage capacitors to be coupled in parallel between pixel electrode 4B3 and common electrode.
The person of noting, in present embodiment, the transistor of each sub-pixel is to be an effect (field-effect) thin film transistor (TFT) (thin-film transistor, TFT), but be not limited in this, in other example, transistor also replaceable has the circuit or the electronic package of switching function for other.These have the circuit of switching function or electronic package also as described above embodiment have a control end corresponding to grid, corresponding to one first end of source electrode and corresponding to one second end of drain electrode, thereby reach aforesaid coupled relation.
In addition, as discussed previously, by the polarity design of data-signal, the polarity between pixel is operated with an inversion mode, therefore when the polarity between pixel operated with an inversion mode, then the polarity between sub-pixel was to operate in row counter-rotating (column inversion) mode.
Specifically, when the polarity of the first data-signal Sd1 and the 3rd data-signal Sd3 all is positive polarity (+), and when the second data-signal Sd2 is negative polarity (-), pixel electrode 1A3,1B3,2A3,2B3,3A3,3B3, the polar relationship of 4A3 and 4B3 is shown in Fig. 7 A, that is to say, the pixel electrode 1A3 and the 1B3 that connect the sub-pixel of the first data-signal Sd1 are positive polarity (+), the pixel electrode 1A3 that connects the sub-pixel of the second data-signal Sd2,1B3,3A3 and 3B3 are negative polarity (-), and the pixel electrode 4A3 and the 4B3 that connect the sub-pixel of the 3rd data-signal Sd3 are positive polarity (+).Therefore, the polarity between pixel is to operate in counter-rotating (dot inversion) mode, and the polarity between sub-pixel is to operate in row counter-rotating (column inversion) mode.
In addition, because two adjacent sub-pixels are to be connected to a data line by the serial connection mode, therefore when reception during as signal that Fig. 3 to Fig. 6 painted, between pixel can because of gate line each other the difference of sequential have the difference of brightness, and adjacent subpixels then can have the difference of brightness because of the length of duration of charging each other is different, so make pixel electrode of the present invention have four kinds of different brightness performances (I, II, III and IV), shown in Fig. 7 B.Yet, arrangement by bridge circuit design of the present invention and pixel can make the pixel electrode of four kinds of different brightness performances of tool be distributed in whole display circuit regularly effectively, the sub-pixel of adjacent two row or adjacent two row has different brightness performance, makes display frame more even.
Describe as present embodiment, though the sub-pixel of the first pixel 135a electrically connects mode and electrically connects mode similar in appearance to the sub-pixel of the second pixel 135b, the source electrode 1A1s of the first pixel 135a by the transistor 1A1 of sub-pixel 1A sees through mode that the circuit cross-over connection is coupled in the first data line d1 through sub-pixel 1B and changes the order of connection between sub-pixel.Thus, the arrangement that sees through above-mentioned bridge circuit design and pixel can reach the charging effect of same pixel electrode, and then reduces the abnormal occurrence that human eye is discovered film flicker.
In sum, in the display circuit of display of the present invention, be transistor series connection with two sub-pixels to accept same data voltage, make its whole required data line be reduced to half of existing display.In addition, the design of the bridge circuit of transmission display circuit, the arrangement of pixel and the annexation between data line and gate line and pixel can reach the charging effect of same pixel electrode effectively, and then avoid the flicker problem of display frame.Therefore, display of the present invention not only can be kept its display quality, more can reduce the power consumption of display circuit effectively, to overcome the shortcoming of prior art.
The above embodiments only are used for exemplifying example of the present invention, and explain technical characterictic of the present invention, are not to be used for limiting protection scope of the present invention.Any be familiar with this operator can unlabored change or the arrangement of the isotropism scope that all belongs to the present invention and advocated, the scope of the present invention should be as the criterion with claim.
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Effective date of registration: 20240911 Address after: Gyeonggi Do, South Korea Patentee after: SAMSUNG DISPLAY Co.,Ltd. Country or region after: Republic of Korea Address before: Hsinchu City, Taiwan, China Patentee before: AU OPTRONICS Corp. Country or region before: TaiWan, China |
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