CN101764615B - Stable sigma-delta modulator - Google Patents
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Abstract
The invention discloses a stable sigma-delta modulator. For an SDM higher than two orders on the basis of the traditional single-ring structure, a signal vibration amplitude controller (AC) is inserted every two orders, and a high-order SDM is divided into a plurality of two-order SDM sections. Compared with the SDM with the traditional structure, the invention can thoroughly solve the stability problem of the SDM on the basis of ensuring the SDM integral performance, in addition, the invention has no difference on the normal signal processing from the SDM on the basis of the traditional single-ring structure, and the theoretical derivation process and the conclusion of each performance index of the invention are the same as those of the SDM on the basis of the traditional single-ring structure.
Description
Technical field
The present invention relates to ∑-sigma-delta modulator in the integrated circuit (IC) design (SDM) technical field, particularly on the basis that guarantees ∑-sigma-delta modulator overall performance, thoroughly solve a kind of stable ∑-sigma-delta modulator of SDM stability problem.
Background technology
∑-sigma-delta modulator technology has the characteristic of noise shaping, noise and the harmonic wave that produces in the quantizing process can be pushed away toward high frequency band, and then reach the digital-to-analogue conversion of high-res, the elementary cell of ∑-sigma-delta modulator is integrator, as shown in Figure 1, thus ∑-sigma-delta modulator technology be widely used in many fields.Along with the SDM exponent number increases, the noise shaping effect will more be that significantly overall performance is better, but when the exponent number of SDM during greater than second order, can cause stable problem, cause stablizing input range and be very restricted.
According to quantification theory, if the quantizer input signal exceeds the opereating specification of quantizer, then the quantization error of quantizer can strengthen.When quantizer was inputted head and shoulders above the quantizer opereating specification, quantization error increased severely suddenly, produced serious distortion when causing reduction, and this situation is called quantizer overload phenomenon, thereby caused the SDM stability problem.But the quantizer input signal only otherwise the opereating specification of plussage device, and quantization error just can be limited in certain scope, thereby makes SDM keep stable.
Since the first ∑-sigma-delta modulator framework in 1962 since (being traditional single ring architecture) be suggested, ∑-sigma-delta modulator development is existing many decades so far, and its stable research and inquirement has been obtained remarkable progress.In the at present practical application, can compare accurately the variation of normal signal in SDM and estimate.That is to say, during normal signal process SDM, can according to certain rule steady change, therefore in actual applications, can for concrete normal signal characteristics design SDM structure, can not exceed the opereating specification of quantizer when making normal signal through quantification; But not normal signal is when the SDM, and variation characteristic is unpredictable, thereby can exceed the opereating specification of quantizer.Large quantity research and experiment show, when the exponent number of SDM during greater than second order, stability problem will occur.
Along with the SDM exponent number increases, stable input range is less, when recovering stablizing signal outside the input range, does not reach the recovery index of requirement, even can not recover fully, thereby cause distorted signals, as shown in Figure 2, can have a strong impact on like this performance of system.
Summary of the invention
The present invention is directed to above-mentioned technical problem, proposed a kind of stable ∑-sigma-delta modulator, can on the basis that guarantees the SDM overall performance, thoroughly solve the stability problem of SDM.
Technical scheme of the present invention is as follows:
A kind of stable ∑-sigma-delta modulator is characterized in that: for the high-order SDM based on single ring architecture more than 2 rank, every then the insertion through 2 rank connects a signal amplitude controller AC, and high-order SDM is divided into a plurality of 2 rank SDM joints.
Described SDM is comprised of 2n+1 integrator and n amplitude controller at least, wherein n 〉=1;
The output signal of described integrator is input signal and previous chronomere system output signal sum;
The output signal of amplitude controller depends on that the input signal of amplitude controller and default fixed value carry out the comparison of numerical values recited, when described input signal numerical value during greater than default fixed value, described output signal is default fixed value, otherwise described output signal is described input signal.
Integrator is used for noise is carried out shaping, and amplitude controller is used to specify the scope of signal amplitude, according to the amplitude range intercept signal.
The output signal end of 2m-1 level integrator is connected to the input signal end of 2m level integrator, the output signal end of 2m level integrator is connected to the input signal end of m level amplitude controller, the output signal end of m level amplitude controller is connected to the input signal end of 2m+1 level integrator, m=1 wherein,, n; The systems by output feedback signal end is connected with every one-level integrator input signal end.
The input signal of the 1st grade of integrator is: input signal (X)-system output signal (Y) * feedback factor (c
1);
The input signal of 2m level integrator is: output signal * gain coefficient (a of 2m-1 level integrator
2m-1The current output signal of)-2m+1 level integrator * feedback factor b
2m-system output signal (Y) * feedback factor (c
2m);
The input signal of m level amplitude controller is: 2m level integrator output signal * gain coefficient (a
2m)-system output signal (Y) * feedback factor (c
2m+1);
The input signal of 2m+1 level integrator is the output signal of m level amplitude controller;
The final output signal of system (Y) is output signal and quantizing noise input signal (E) sum of afterbody integrator.
Common SDM structure has two kinds among the DAC: single ring architecture and cascade structure.A plurality of SDM connect mutually, form cascade structure.Corresponding cascade structure, the system that only has a SDM is single ring architecture.
The structure of SDM of the present invention has the new construction that is different from single ring architecture and cascade structure.Compare with traditional SDM, the SDM of structure of the present invention by in each 2 rank Nodes control signal amplitude bound, revises the amplitude of improper signal under the prerequisite that does not affect normal signal.2 rank SDM joint belongs to low stage structure, not existence and stability problem.Cut off by amplitude controller between the 2 rank SDM joint, avoided quantizer opereating specification external signal pernicious cumulative at each internode of SDM by feedback, thereby can not exceed the quantizer opereating specification when all signals are quantized, therefore on the basis that guarantees the SDM overall performance, thoroughly solve the stability problem of SDM.
Beneficial effect of the present invention is as follows:
The SDM of structure of the present invention compares with the SDM of traditional structure, can on the basis that guarantees the SDM overall performance, thoroughly solve the SDM stability problem, and the present invention and based on the SDM of traditional single ring architecture in the processing of normal signal without any difference, the theoretical derivation of its property indices and conclusion are identical with SDM based on traditional single ring architecture.
Description of drawings
Fig. 1 is the structural representation of integrator
Fig. 2 is the waveform signal schematic diagram after recovering
Fig. 3 is 5 rank SDM configuration diagram based on traditional single ring architecture
Fig. 4 is 5 rank SDM configuration diagram of the present invention
Fig. 5 is implementation schematic diagram of the present invention
Specific embodiment
A kind of stable ∑-sigma-delta modulator is characterized in that: for the high-order SDM based on traditional single ring architecture more than 2 rank, every then the insertion through 2 rank connects a signal amplitude controller AC, and high-order SDM is divided into a plurality of 2 rank SDM joints.
Described SDM is comprised of 2n+1 integrator and n amplitude controller at least, wherein n 〉=1;
The output signal of described integrator is input signal and previous chronomere system output signal sum;
The output signal of amplitude controller depends on that the input signal of amplitude controller and default fixed value carry out the comparison of numerical values recited, when described input signal numerical value during greater than default fixed value, described output signal is default fixed value, otherwise described output signal is described input signal.
Integrator is used for noise is carried out shaping, and amplitude controller is used to specify the scope of signal amplitude, according to the amplitude range intercept signal.
The output signal end of 2m-1 level integrator is connected to the input signal end of 2m level integrator, the output signal end of 2m level integrator is connected to the input signal end of m level amplitude controller, the output signal end of m level amplitude controller is connected to the input signal end of 2m+1 level integrator, m=1 wherein,, n; The systems by output feedback signal end is connected with every one-level integrator input signal end.
As shown in Figure 3-4, take 5 rank based on the SDM with LOCAL FEEDBACK ring of traditional single ring architecture as example, compare with traditional SDM, the present invention is under the prerequisite that does not affect normal signal, by in each 2 rank Nodes control signal amplitude bound, revise the amplitude of improper signal.2 rank SDM joint belongs to low stage structure, not existence and stability problem.Cut off by amplitude controller between the 2 rank SDM joint, avoided quantizer opereating specification external signal pernicious cumulative at each internode of SDM by feedback, thereby can not exceed the quantizer opereating specification when all signals are quantized, therefore on the basis that guarantees the SDM overall performance, thoroughly solve the stability problem of SDM.
Among Fig. 3-4, X is the signal input, and E is the quantizing noise input, and Y is the final output of system, a
1, a
2, a
3, a
4Be the gain coefficient of every inter-stage, b
1, b
2, c
1, c
2, c
3,, c
4, c
5Be feedback factor, z
-1Represent that a unit interval postpones.
Native system is composed in series by five integrator unit, inserts respectively an amplitude controller behind the second level and the fourth stage integrator.
The input signal of first order integrator is: input signal (X)-system output signal (Y) * feedback factor (c
1);
The input signal of second level integrator is: output signal * gain coefficient (a of first order integrator
1Current output signal * feedback factor (b of)-third level integrator
1)-system output signal (Y) * feedback factor (c
2);
The input signal of first amplitude controller is: second level integrator output signal * gain coefficient (a
2)-system output signal (Y) * feedback factor (c
3).
The input signal of third level integrator is the output signal of first amplitude controller.
The input signal of fourth stage integrator is: third level integrator output signal * gain coefficient (a
3Current output signal * feedback factor (b of)-level V integrator
2)-system output signal (Y) * feedback factor (c
4).
The input signal of second amplitude controller is comprised of two parts: fourth stage integrator output signal * gain coefficient (a
4)-system output signal (Y) * feedback factor (c
5).
The input signal of level V integrator is the output signal of second amplitude controller.
The final output signal of system (Y) is level V integrator output signal and quantizing noise input signal (E) sum.
As shown in Figure 5, in codec (CODEC), utilize ∑ with structure of the present invention-sigma-delta modulator to realize high accuracy high-performance digital to analog converter (DAC).
Original SDM is for based on the 5 rank SDM with LOCAL FEEDBACK ring of traditional single ring architecture, by audio analyzer, the performance index of the CODEC that adopts two kinds of structure SDM tested.Test result is as shown in table 1, and the performance index of two kinds of CODEC are identical.
| Full width of cloth THD | Half range THD | SNR | |
| Former CODEC | 80 | 75 | 88 |
| CODEC after improving | 80 | 75 | 88 |
Table 1
Adopt a large amount of test signals that two kinds of CODEC are carried out the FPGA test, in conjunction with the audio analyzer test result, draw the following conclusions:
During the input normal signal, the two performance index is identical.When inputting improper signal, adopt the CODEC of former SDM can not normally recover exceeding the signal of stablizing input range; The CODEC that employing has structure SDM of the present invention can both normally recover all improper signals in the test, has reached the purpose that thoroughly solves the SDM stability problem on the basis that guarantees ∑-sigma-delta modulator overall performance.
Claims (3)
1. sigma-delta modulator, it is characterized in that: for the high-order sigma-delta modulator based on single ring architecture more than 2 rank, every then the insertion through 2 rank connects a signal amplitude controller AC, the high-order sigma-delta modulator is divided into the joint of a plurality of 2 rank sigma-delta modulators;
Described sigma-delta modulator is comprised of 2n+1 integrator and n amplitude controller at least, wherein n 〉=1;
The output signal of described integrator is input signal and previous chronomere system output signal sum;
The output signal of amplitude controller depends on that the input signal of amplitude controller and default fixed value carry out the comparison of numerical values recited, when the input signal numerical value of described amplitude controller during greater than default fixed value, described output signal is default fixed value, otherwise described output signal is described input signal;
Integrator is used for noise is carried out shaping, and amplitude controller is used to specify the scope of signal amplitude, according to the amplitude range intercept signal.
2. described a kind of sigma-delta modulator according to claim 1, it is characterized in that: the output signal end of 2m-1 level integrator is connected to the input signal end of 2m level integrator, the output signal end of 2m level integrator is connected to the input signal end of m level amplitude controller, the output signal end of m level amplitude controller is connected to the input signal end of 2m+1 level integrator, m=1 wherein,, n; The systems by output feedback signal end is connected with every one-level integrator input signal end.
3. described a kind of sigma-delta modulator according to claim 1 and 2 is characterized in that:
The input signal of the 1st grade of integrator is: input signal-system output signal Y * feedback factor (c
1);
The input signal of 2m level integrator is: the output signal of 2m-1 level integrator * gain coefficient a
2m-1The current output signal of-Di 2m+1 level integrator * feedback factor b
2m-system output signal Y * feedback factor c
2m
The input signal of m level amplitude controller is: 2m level integrator output signal * gain coefficient a
2m-system output signal Y * feedback factor c
2m+1
The input signal of 2m+1 grade integrator is the output signal of m level amplitude controller;
The final output signal Y of system is output signal and the quantizing noise input signal E sum of afterbody integrator;
M=1 wherein ..., n.
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|---|---|---|---|
| CN 200910216415 CN101764615B (en) | 2009-11-27 | 2009-11-27 | Stable sigma-delta modulator |
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| CN101764615B true CN101764615B (en) | 2013-04-24 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102340314A (en) * | 2010-07-28 | 2012-02-01 | 中兴通讯股份有限公司 | Sigma-delta modulator |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5243345A (en) * | 1991-03-01 | 1993-09-07 | U.S. Philips Corporation | Sigma-delta modulator having a plural order loop filter with successive filter sections of successively smaller signal excursion range |
| CN1319276A (en) * | 1999-07-28 | 2001-10-24 | 皇家菲利浦电子有限公司 | Variable order SIGMA-DELTA modulator |
-
2009
- 2009-11-27 CN CN 200910216415 patent/CN101764615B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5243345A (en) * | 1991-03-01 | 1993-09-07 | U.S. Philips Corporation | Sigma-delta modulator having a plural order loop filter with successive filter sections of successively smaller signal excursion range |
| CN1319276A (en) * | 1999-07-28 | 2001-10-24 | 皇家菲利浦电子有限公司 | Variable order SIGMA-DELTA modulator |
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Address after: 610041 Sichuan city of Chengdu province high tech Zone Kyrgyzstan Road 33 block A No. 9 Patentee after: IPGoal Microelectronics (Sichuan) Co.,Ltd. Address before: 402 room 7, building 610041, incubator Park, hi tech Zone, Sichuan, Chengdu Patentee before: IPGoal Microelectronics (Sichuan) Co.,Ltd. |
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