CN101764605A - Negative voltage level switching circuit - Google Patents

Abstract

The invention relates to a negative voltage level switching circuit which comprises two inserted N pipes, two upward pulling P pipes and two positive feedback N pipes, wherein a source electrode of each upward pulling P pipe is connected with positive voltage Vdd, and a drain electrode thereof is connected with a drain electrode of each inserted N pipe; a source electrode of each positive feedback N pipe is connected with negative voltage Vneg, and a drain electrode thereof is connected with a source electrode of each inserted N pipe; a node between the second inserted N pipe and the second upward pulling P pipe is taken as output Vout, a grid electrode between the first inserted N pipe and the first upward pulling P pipe is connected with an input signal Vin, and a grid electrode of the first positive feedback N pipe is connected with output voltage Vout; grid electrodes of the second inserted N pipe and the second upward pulling P are connected with an output end of an inverter, and an input end of the inverter is connected with the input signal Vin; and a grid electrode of the second positive feedback N pipe is connected with a node between the first inserted N pipe and the drain electrode of the first upward pulling P pipe. The negative voltage level switching circuit can be used for reducing the conduction current needed by the P pipes under the same conduction condition, reduces the areas of the P pipes, accelerates the voltage switching speed and decreasing the switching power consumption.

Description

Negative voltage level switching circuit

Technical field

The present invention relates to integrated circuit (IC) design, particularly a kind of conversion that is used for according to input signal is switched output voltage between forward voltage and negative voltage negative voltage commutation circuit.

Background technology

Integrated circuit for adapting to various operations, need to tend to different voltage in running.And the input voltage of circuit is generally single or limited, therefore, needs to be converted to input voltage the circuit of needed positive high voltage of different operating or negative high voltage in the circuit design.

(Flash Memory) is example with flash memory, in the storage organization of typical NOR type Flash storage chip, each memory cell comprises a MOSFET, its grid is connected to corresponding word line WL, drain electrode connects corresponding bit line BL, and the source electrode of all memory cell all is connected on the identical source line VS.And when reading, writing with erase operation to memory cell, the representative value of the relative voltage that word line, bit line and source line are required as shown in Table 1:

The typical operation voltage of table one NOR Flash

Operation	??WL(Vg)(V)	??BL(Vd)(v)	?VS(Vs)(v)	??Vb(v)
					Read	??3/0	??1/--	?0	??0
Write	??10/0	??6.5/0	?0	??0
					Wipe	??-8/0	??Float	?6.5	??0

According to prior art, the integrated circuit of storage chip such as Flash or EEPROM generally is to use the manufacturing of CMOS technology, and raising along with technological level, the device integrated level improves constantly, in order to reduce power consumption and to dwindle chip size, people wish to reduce the size and the operating voltage of individual devices, and along with dwindling of size, the puncture voltage of MOS device is also reducing gradually.With 0.18 μ m technology is example, the puncture voltage of high-voltage tube be about 10.5V and low-voltage tube only for 7.5V.And in the circuit of storage chips such as Flash or EEPROM, usually need-6～-negative voltage of 10V, therefore, extremely low negative voltage (as-10V) and between the forward voltage Vdd switch, and in handoff procedure, prevent device breakdown be the problem that must solve in the integrated circuit (IC) design.And good design decapacitation realizes outside the circuit basic function, should satisfy also that area is little, working stability, conversion speed is fast and index such as low in energy consumption.

Fig. 1 is a typical negative voltage level switching circuit of the prior art.This circuit by two P channel mosfets (transistor P101, P102) and two N-channel MOS FET (transistor N103 N104) constitutes, in order to narrate conveniently, below with the P channel mosfet with N-channel MOS FET abbreviates the P pipe as and N manages.Vdd is a forward voltage among Fig. 1, Vneg is a negative voltage, input signal Vin is to the level signal of switching between the Vdd at 0v, the reverse signal Vin_b that this circuit obtains after by inverter Inv by input signal Vin and Vin controls the turn-on and turn-off of P pipe P101 and P102 respectively, and act on the right N pipe (N103, N104) of two formations positive feedback, thereby control output voltage Vout.

With reference to Fig. 1, when input signal Vin voltage was Vdd, reverse signal Vin_b voltage was 0v, at this moment, transistor P101 turn-offs, and transistor P102 conducting, output voltage V out by on move Vdd to, because output voltage V out is connected to the grid of transistor N103, therefore, transistor N103 is switched on, then with the grid voltage of transistor N104 drop-down be negative voltage Vneg, transistor N104 is turn-offed, thereby make output voltage V out maintain Vdd; And when input signal Vin is 0v, reverse signal Vin_b voltage is Vdd, at this moment, transistor P102 turn-offs, and transistor P101 conducting, then move Vdd on the grid voltage with transistor N104, make transistor N104 conducting, thus with output voltage V out drop-down be negative voltage Vneg because output voltage V out is connected to the grid of transistor N103, therefore, transistor N103 is turned off.Like this, the circuit of Fig. 1 has been realized voltage transitions and conversion back circuit no current path substantially.

But but there is following shortcoming in circuit as shown in Figure 1:

The first, for the amplitude that adapts to Vneg becomes big, must strengthen P pipe size.When metal-oxide-semiconductor worked in the saturation region, its desirable saturation current can be tried to achieve by following formula,

$I_D=\frac{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}}{2}\×\frac{W}{L}\×{(V_{\mathrm{GS}}-V_{\mathrm{th}})}^2---\left(1\right)$

Wherein, μ _nExpression electronics, hole mobility, relevant with doping content, C _OxDepend on dielectric constant, for certain material and doping content, the two is a constant, V _GSThe expression gate source voltage, V _ThThe expression threshold voltage, W represents the width of metal-oxide-semiconductor, L represents the length of metal-oxide-semiconductor.For the handoff procedure that input signal Vin changes, the electric current that flows through the N pipe in the handoff procedure will be proportional to (V _GS-V _Th) ², and wherein for the N pipe, V _GS=V _Out-V _NegSo along with reduce (amplitude that is Vneg becomes big) of Vneg, the switch current of N pipe will increase.Finish in order to guarantee to switch, the switch current of P pipe also must increase, but according to (1) formula, (V of P pipe _GS-V _Th) absolute value is Vdd-V _ThBe definite value,, must increase in order to increase saturation current

But length L generally by the process conditions decision of CMOS processing procedure, can not at will reduce, and is to increase this ratio, must increase width W.Make principle according to integrated circuit, because the main charge carrier of P raceway groove is the hole, in order to obtain and the identical conductive capability of N channel transistor that with electronics is main charge carrier, P pipe area just need be managed big several times than N, therefore increase P pipe width W, will cause enlarging markedly of circuit layout area.

The second, according to above-mentioned analysis, along with reducing of Vneg, switch current will increase, and obviously switch power consumption and also will increase.And for current technology, under the condition of 0.18 μ m or smaller szie, switch power consumption in the circuit total power consumption, to have occupied sizable ratio, therefore, the increase of switching power consumption will bring very big influence to circuit integral body.

The 3rd, circuit working instability, the switch speed of circuit are subjected to the Vdd influence, and be in service at circuit, if Vneg reduces, perhaps Vdd reduces, and all can cause switch speed to descend, and if the two be reduced to surpass to a certain degree so that the saturation conduction electric current of P pipe less than the saturation conduction electric current of N pipe, be that the P pipe can't provide enough current lead-through abilities, circuit will enter metastable state, and voltage can't switch, and cause very big dc power.

In order to address the above problem, application number is 03156368.6, and the applying date is on September 5th, 2003, " negative voltage level conversion circuit " by name, and the Chinese invention patent of Granted publication CN 12005160 discloses a kind of improved circuit structure, as shown in Figure 2.From Fig. 2 as seen, this circuit comprises: the CMOS inverter, and its input connects input voltage; First inverter, it is made of PMOS pipe P201 and NMOS pipe N205, is connected between the input and negative high voltage input of CMOS inverter; Second inverter is made of the 2nd PMOS pipe P202 and the 2nd NMOS pipe N206, is connected between the output and negative high voltage input of CMOS inverter, and its output is the output of described negative voltage level conversion circuit; The high level of this output output is by described the 2nd PMOS pipe P202 transmission, and the low level of this output output is by described the 2nd NMOS pipe N206 transmission; The input of described first inverter connects the output of second inverter, and the output of first inverter connects the input of second inverter, makes first inverter and second inverter become the positive feedback passage of output voltage; The 3rd PMOS pipe P203 that connects grounded-grid between the output of the input of CMOS inverter and first inverter is to provide the initial voltage of second inverter; The 4th PMOS pipe P204 that connects grounded-grid between the output of the output of CMOS inverter and second inverter is to provide the initial voltage of first inverter.

This circuit is to make two branch roads be in non-equilibrium state with inverter equally, and Ji required drive current when reducing level conversion is finished signal by regenerative circuit again and switched, and strengthens the driving force of drawing with the P pipe of two grounded-grids, the quickening reversal rate.But, because the source electrode of P pipe is not directly to meet VDD, but receive on input signal Vin or the reverse signal input signal Vin_b, though therefore this circuit can make whole negative high voltage level shifting circuit when input voltage reduces, circuit still can operate as normal, but to such structure, use under the situation of the same area at the P pipe, pull-up current is to reaching 1/4 of aforementioned circuit, that is if reach identical pull-up current, P pipe area then will increase 4 times, simultaneously, increases the chip area that the P pipe also can significantly increase circuit.So still there are many deficiencies in this circuit.

Summary of the invention

Purpose of the present invention promptly is to overcome the above-mentioned defective of prior art, solves to the amplitude that adapts to Vneg becomes big, must strengthen the problem of P pipe size, reduces to switch power consumption, and guarantees to switch stable.

For this reason, the invention provides a kind of negative pressure commutation circuit, be connected to a forward voltage Vdd and a negative voltage Vneg, and according to input signal Vin switching output voltage V out, it is characterized in that, described circuit comprises that an inverter and source electrode, drain electrode are connected two group transistors between forward voltage Vdd and the negative voltage Vneg, wherein:

Comprise in first group transistor: first inserts the N pipe; Draw the P pipe on first, its source electrode is connected to forward voltage Vdd, and drain electrode is connected to first drain electrode of inserting the N pipe; First positive feedback N pipe, its source electrode is connected to negative voltage Vneg, and drain electrode is connected to the source electrode of the first insertion N pipe;

Comprise in second group transistor: second inserts the N pipe; Draw the P pipe on second, its source electrode is connected to forward voltage Vdd, and drain electrode is connected to second drain electrode of inserting the N pipe, and the node between the two connects output voltage V out; Second positive feedback N pipe, its source electrode is connected to negative voltage Vneg, and drain electrode is connected to the source electrode of the second insertion N pipe; And

Draw the grid of P pipe to be connected to input signal Vin on the described first insertion N pipe and first, the grid of the first positive feedback N pipe connects output voltage V out; Described second inserts the output that draws the P tube grid to be connected to inverter on N pipe and second, the input connection input signal Vin of inverter; The grid of the second positive feedback N pipe is connected to first and inserts the node that draws on N pipe and first between the drain electrode of P pipe.

Beneficial effect of the present invention is, by increasing the mode of isolating the N pipe, under the condition that increases chip area hardly circuit performance is made improvements; Compared with prior art, the required conducting electric current of P pipe under the identical turn-on condition can be reduced, thereby required P pipe size can be reduced; And circuit of the present invention can be accelerated the voltage switch speed and reduce to switch power consumption.

Description of drawings

Fig. 1 is the circuit diagram of prior art negative voltage level conversion circuit embodiment one;

Fig. 2 is the circuit diagram of prior art negative voltage level conversion circuit embodiment two;

Fig. 3 is the circuit diagram of negative voltage level conversion circuit embodiment one of the present invention.

Embodiment

Negative voltage level switching circuit of the present invention as shown in Figure 3.It comprises inverter I307, two P-channel metal-oxide-semiconductor field-effect transistors (MOSFET) P301, P302; 4 n channel metal oxide semiconductor field effect transistors (MOSFET) N303, N304, N305, N306; In order to narrate conveniently, below abbreviate MOSFET as transistor, abbreviate P-channel metal-oxide-semiconductor field-effect transistor (MOSFET) as the P pipe, n channel metal oxide semiconductor field effect transistor (MOSFET) abbreviates the N pipe as.

See also Fig. 3, wherein Vdd is a forward voltage, and Vneg is a negative voltage, and Vin is an input signal, and obtaining reverse input signal behind the Vin input signal process reverser I307 is Vin_b, and negative voltage level switching circuit is output as Vout.Two group transistor circuit are arranged between forward voltage Vdd and negative voltage Vneg, source, the drain electrode series connection in regular turn of drawing P pipe P301, first to insert N pipe N303 and first positive feedback N pipe N305 on first constitute the first group transistor circuit, draw the source S 301 of P pipe P301 to be connected to forward voltage Vdd on first, its drain D 301 is connected to first and inserts the drain D 303 that N manages N303, the source S 303 of the first insertion N pipe N303 and the drain D 305 of first positive feedback N pipe N305 are joined, and the source electrode of first positive feedback N pipe N305 meets negative voltage Vneg; The second group transistor circuit draws the source of P pipe P302, the second insertion N pipe N304 and second positive feedback N pipe N306, drain electrode series connection in regular turn to constitute on second, draw the source S 302 of P pipe P302 to be connected to forward voltage Vdd on second, its drain D 302 is connected to second and inserts the drain D 304 that N manages N304, output Vout is connected to the node between the two, the source S 304 of the second insertion N pipe N304 and the drain D 306 of second positive feedback N pipe N306 are joined, and the source electrode of second positive feedback N pipe N306 meets negative voltage Vneg; And two group transistor circuit are by the control action formation inverter and the positive feedback passage of grid, the grid G 301, the G303 that draw P pipe P301 and first to insert N pipe N303 on first are connected to input signal Vin, the grid G 302, the G304 that draw P pipe P302 and second to insert N pipe N304 on second are connected to reverse input signal Vin_b, the grid G 305 of first positive feedback N pipe N305 is connected to output Vout, and 306 of the grid G of second positive feedback N pipe N306 are connected to the drain D 301 and first of drawing P pipe P301 on first and insert node Vout_b between the drain D 303 that N manages N303.Each P channel mosfet, be to draw the substrate (base stage) of P pipe P301, P302 to be connected to forward voltage Vdd on first and second, and each N-channel MOS FET, promptly first and second substrate (base stage) that inserts N pipe N303, N304 and first and second positive feedback N pipe N305 and N306 is connected to negative voltage Vneg.

Wherein, each transistorized source, leakage, grid mark S301～306, D301～306, G301～306th, for narrating the clear code name of introducing each transistor electrodes, it is not a Reference numeral.General general knowledge and circuit symbol according to Analog Electronics Technique represent, those of ordinary skill in the art is in conjunction with the content of specification, when can be easily that above-mentioned electrode code name is corresponding with the respective electrode node in the accompanying drawing.

Circuit of the present invention is equivalent in the circuit of prior art Fig. 1, has added one respectively at two positive feedback branch and has inserted the N pipe.Its course of work is as follows: when input signal Vin voltage is Vdd, reverse signal Vin_b voltage is 0v, at this moment, draw P pipe P301 to turn-off on first, and draw P to manage the P302 conducting on second, second inserts N pipe N304 turn-offs, output voltage V out by on move Vdd to because output voltage V out is connected to the grid of first positive feedback N pipe N305, therefore, first positive feedback N pipe N305 is switched on, simultaneously, because first grid voltage that inserts N pipe N303 also is Vdd, first inserts N pipe N303 conducting, then with the grid voltage of second positive feedback N pipe N306 drop-down be negative voltage Vneg, make second positive feedback N pipe N306 shutoff, thereby make output voltage V out maintain Vdd; And when input signal Vin becomes 0v, reverse signal Vin_b voltage becomes Vdd, at this moment, draw P pipe P301 conducting on first, first inserts N pipe N303 turn-offs, then move Vdd on the grid voltage with second positive feedback N pipe N306, make second positive feedback N pipe N306 conducting, simultaneously, draw P pipe P302 to turn-off on second, and because the second grid time variant voltage of inserting N pipe N304 is Vdd, second inserts N pipe N304 conducting, thus with output voltage V out drop-down be negative voltage Vneg because output voltage V out is connected to the grid that the first positive feedback N manages N305, therefore, first positive feedback N pipe N305 is turned off.Like this, realized when input signal Vin between Vdd and 0v during conversion, the conversion of output Vout between Vdd and negative voltage Vneg.In transfer process of the present invention, each transistorized transition status and voltage are as shown in the table:

Table one Vin becomes circuit state variation the Vdd process from 0V

Table two Vin becomes circuit state variation the 0V process from Vdd

From said process, circuit of the present invention as can be seen has following characteristics:

The first, because under the identical parameters situation, the size of P pipe and N pipe is bigger than very, and (with circuit structure shown in Figure 1 is example, works as Vdd=3V, normal in order to guarantee handoff functionality during Vneg=-8v, and N pipe size is about 1/15～1/10 of P pipe size; P pipe and N pipe size is than bigger in the circuit structure of Fig. 2), it is very little to the influence of the total chip area of circuit therefore to insert two N pipes, obviously is far smaller than and inserts the influence that chip area that the P pipe caused doubles in the prior art of Fig. 2.

The second, the switch speed of circuit of the present invention is very fast.With the handoff procedure of the Vin shown in the table one from 0 to Vdd is example, on draw branch road, draw P pipe P302 conducting on second, draw the grid of P pipe P301 pipe to meet Vdd on first, electric current is 0; To drop-down branch road, the grid that inserts N pipe (first inserts N pipe N303) meets Vdd, its V _GSBe Vdd-Vneg, this voltage very big (Vdd=2v for example, Vneg=-8v, then V _GS=10v), therefore the ducting capacity of the first insertion N pipe N303 is very strong, can have any impact to drop-down speed hardly; And since on draw branch road to draw on can be soon, so the grid voltage of positive feedback N pipe (the first positive feedback N manage N305) rises very soon, accelerated the speed of pull-down current increase.Like this, by on draw the positive feedback effect of branch road and drop-down branch road, can add the switch speed of fast-circuit greatly.

The 3rd, owing to insert the partition effect of N pipe (first and second inserts N pipe N303, N304), when Vdd significantly reduced, circuit also can operate as normal.According to the simulation result to circuit of the present invention, when Vneg=-8v, even Vdd is reduced to 1.5v, circuit also can be normally, switch apace.

The 4th, in the level handoff procedure, P pipe source electrode directly meets Vdd, on draw ability strong; And the grid voltage that inserts N pipe (first and second inserts N pipe N303, N304) Vdd and 0 rather than Vneg between switch, this just greatly reduces the conducting electric current that inserts the N pipe.Therefore, on draw the pull-down current of branch road to die down, help improving the speed of drawing.Reduce and the raising of switch speed of switch current will be made contributions to the decline of switching power consumption simultaneously from two aspects.Simultaneously, because pull-down current dies down, can also reduce P pipe size greatly.

In sum, compared with prior art, reaching under the prerequisite that the same electrical crush-cutting changes purpose, circuit of the present invention can the scaled down version area of pictural surface, increases conversion speed and reduces power consumption simultaneously.According to emulation and test result, this circuit of the present invention is more half as large than prior art Fig. 1 at chip area, and under the situation than the circuit little 3/4 of Fig. 2, reversal rate is still fast than them, and power consumption reduces greatly simultaneously.Particularly when Vdd was very low, the level switch speed was faster more than 7 times, for example than the structure of Fig. 1 and Fig. 2: during Vdd=1.8V, switch speed of the present invention is 2.4ns and prior art is 17ns.

Claims (1)

1. negative voltage level switching circuit, be connected to a forward voltage Vdd and a negative voltage Vneg, and according to input signal Vin switching output voltage V out, it is characterized in that, described circuit comprises that an inverter and source electrode, drain electrode are connected two group transistors between forward voltage Vdd and the negative voltage Vneg, wherein:

Comprise in first group transistor: first inserts the N pipe; Draw the P pipe on first, its source electrode is connected to forward voltage Vdd, and drain electrode is connected to first drain electrode of inserting the N pipe; First positive feedback N pipe, its source electrode is connected to negative voltage Vneg, and drain electrode is connected to the source electrode of the first insertion N pipe;

Comprise in second group transistor: second inserts the N pipe; Draw the P pipe on second, its source electrode is connected to forward voltage Vdd, and drain electrode is connected to second drain electrode of inserting the N pipe, and the node between the two connects output voltage V out; Second positive feedback N pipe, its source electrode is connected to negative voltage Vneg, and drain electrode is connected to the source electrode of the second insertion N pipe; And

Draw the grid of P pipe to be connected to input signal Vin on the described first insertion N pipe and first, the grid of the first positive feedback N pipe connects output voltage V out; Described second inserts the output that draws the P tube grid to be connected to inverter on N pipe and second, the input connection input signal Vin of inverter; The grid of the second positive feedback N pipe is connected to first and inserts the node that draws on N pipe and first between the drain electrode of P pipe.

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