CN101751985B - Method for updating memory device - Google Patents

Abstract

The present invention provides an updating method for a memory device, which is applicable to a memory device and includes the following steps. First, a sleep mode in which the memory device cannot be read or written is set. During the sleep mode, the first and second memory cell arrays are automatically updated in sequence, and the steps of automatically updating the first and second memory cell arrays each include: during an equal potential period, switching the potentials of a sensing line pair, a first bit line pair, and a second bit line pair to a reference voltage, wherein the sensing line pair and the second bit line pair are electrically disconnected from each other; and during the updating period, adjusting the potentials of the first and second bit line pairs according to the updating sequence of the first and second memory cell arrays, and electrically connecting the sensing line pair to at least one of the first and second bit lines accordingly.

Description

Method for updating memory device

technical field

The present invention relates to a method for updating a memory device, and in particular to a method for updating a memory device for reducing leakage current and noise.

Background technique

DRAM is currently the most widely used memory. DRAM uses capacitors to store data. Since the charges stored in the capacitors will gradually disappear, additional periodic refresh operations are required. FIG. 1 is a schematic structural diagram of a basic unit of a known DRAM. FIG. 2 is a timing diagram illustrating the signals in FIG. 1 . Please refer to FIG. 1 and FIG. 2 at the same time. During the equipotential period T21, since the levels of the signals EQL11, EQL12, MUX11 and MUX12 are maintained at the voltage VINT2, the bit lines (BL11, /BL11, BL12 and /BL12) and the sensing lines ( BLM11 and BLM12) are electrically connected to each other and equipotentially to the reference voltage VEQL2, wherein the level of the reference voltage VEQL2 is set to half of the highest level of the bit line VBLH2.

Afterwards, in order to refresh the memory cells 131 connected to the word line WLR0, the memory cell array 130 is enabled in the refresh period T22. At this time, the levels of the signals EQL12 and MUX11 will transition to the voltage VSS2, so that the bit lines BL12 and /BL12 are not conducted to each other, and the sense amplifier 120 and the memory cell array 110 are not connected to each other. Afterwards, the memory cell to be accessed is addressed through the word line WLR0. In the signal generating phase, the memory unit 131 is turned on, and the signal to be read is generated on the bit lines BL12, /BL12 and the sensing lines BLM11, BLM12. At this time, the sense amplifier 120 will amplify the signals on the sense lines BLM11 and BLM12 to achieve the purpose of updating the memory unit 131 .

It is worth noting that as the DRAM core structure shrinks day by day, the leakage current between the bit lines becomes more and more serious. The main reason is that during the equipotential period, the parasitic capacitance in the memory cell will form an unnecessary conduction path, and a leakage current will be formed between the bit lines, for example: I11 shown in FIG. 1 . This situation can be reduced by adding a current limiter, but the leakage current from the sense amplifier 120, such as I12 shown in FIG. 1, cannot be suppressed.

In order to avoid the leakage current from the sense amplifier 120 , as shown in FIG. 3 , at the initial stage of the refresh period T22 , the prior art switches the signals MUX11 and MUX12 to the voltage VSS2 at the same time. At this time, the sensing lines BLM11 and BLM12 will maintain a floating state, thereby reducing the occurrence of leakage current. However, when the sensing lines BLM11 and BLM12 are kept in a floating state simultaneously, noise will be generated, thereby affecting the noise margin of the entire system.

Contents of the invention

The invention provides a refresh method for reducing leakage current and noise generation in a memory device.

The invention proposes an update method, which is suitable for a memory device. Wherein, the memory device includes a sense amplifier, a first memory cell array and a second memory cell array, the sense amplifier has a sense line pair, and is used to amplify a signal from a first bit line pair in the first memory cell array, and signals from a second bit line pair in the second memory cell array. The update method includes the following steps. Firstly, a sleep mode is set, wherein the memory device cannot be read and written in the sleep mode. Afterwards, the first and second memory cell arrays are automatically updated sequentially.

It is worth noting that the above-mentioned steps of automatically updating the first and second memory cell arrays each include: switching the potentials of the sensing line pair, the first bit line pair, and the second bit line pair to a reference voltage during an equipotential period , wherein the pair of sensing lines and the pair of second bit lines are electrically disconnected from each other; and, during a refresh period, the potentials of the pair of first and second bit lines are adjusted according to the refresh order of the first and second memory cell arrays, And according to this, the pair of sensing lines is electrically connected to at least one of the first and second bit lines.

In an embodiment of the present invention, the step of switching the potentials of the sensing line pair, the first bit line pair, and the second bit line pair to the reference voltage includes firstly, providing a first and a second equipotential control signals to respectively control the conduction states of the two bit lines in the first bit line pair and the second bit line pair. Afterwards, a first and a second sensing control signal are provided to respectively control the conduction states of the sensing line pair, the first bit line pair, and the second bit line pair.

Furthermore, in order to cause the potentials of the respective line pairs to switch to the reference voltage, the levels of the first and second equibit control signals are maintained at a first voltage, so as to respectively cause the first bit line pair and the second bit line The two wires in the circuit conduct with each other and equipotentially reach the reference voltage. In addition, the level of the first sensing control signal is further maintained at the first voltage, so that the sensing line pair is electrically connected to the first bit line pair. Here, the level of the second sensing control signal is switched to a second voltage, so that the sensing line pair is electrically disconnected from the second bit line pair.

In an embodiment of the present invention, in the process of automatically updating the second memory cell array, during the update period, the first and second bit line pairs are adjusted according to the update order of the first and second memory cell arrays. The step of maintaining the potential of the first bit line pair includes maintaining the level of the first equipotential control signal, so that the two bit lines in the first bit line pair are mutually conducted and are equipotentially equal to the reference voltage. And, switch the level of the second equal bit control signal to the second voltage, so that the two bit lines in the second bit line pair are not conducted with each other.

In an embodiment of the present invention, the step of electrically connecting the sensing line pair to at least one of the first and second bit lines in the process of automatically updating the second memory cell array includes, first, connecting The level of the first sensing control signal is switched to the second voltage, so that the sensing line pair and the first bit line pair are electrically disconnected from each other. And, increasing the level of the second sensing control signal in a stepwise manner, so as to cause the sense amplifier to amplify the signal from the second bit line pair.

Based on the above, for the automatic refresh of the first and second memory cell arrays, the present invention reduces the leakage current between the bit lines by using the way that the sensing line pair and the second bit line pair are electrically disconnected from each other during the equipotential period. In addition, the present invention electrically connects the pair of sensing lines to at least one of the first and second bit lines during the updating period, so as to reduce the generation of noise.

Description of drawings

FIG. 1 is a schematic structural diagram of a basic unit of a known DRAM.

FIG. 2 is a timing diagram for illustrating the signals in FIG. 1 .

FIG. 3 is another timing diagram for illustrating the signals in FIG. 1 .

FIG. 4A is a flowchart of an update method according to an embodiment of the present invention.

FIG. 4B is a timing diagram for illustrating the signals in FIG. 4A.

FIG. 5 is a flowchart for illustrating step S421.

Reference number

110, 130: memory cell array

111, 131: storage unit

120: Sense Amplifier

BL11, /BL11, BL12, /BL12: bit lines

PBL11, PBL12: bit line pair

BLM11, BLM12: induction line

PBLM: sense line pair

T11～T14: Receiver

WLR0, WLR1, WLL0, WLL1: word lines

VEQL2: reference voltage

I11, I12: leakage current

T21, T41, T43: equipotential period

T22, T42, T44: during update

VINT2, VSS2, VPP2, VBLH2, VBLH4: voltage

EQL11, EQL12, MUX11, MUX12, SWLR, SWLL, SBLM11, SBLM12: Signal

S410～S430, S421～S425, S431～S435: used to illustrate the steps of the embodiment in Figure 4A

EQL41: First-level control signal

EQL42: Second-level control signal

MUX41: the first sensing control signal

MUX42: Second sensing control signal

VINT4: first voltage

VSS4: second voltage

VPP4: third voltage

S510-S550: used to illustrate each step of step S421

Detailed ways

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Before describing the embodiments of the present invention, it must be understood that the update method of the present invention is applicable to a memory device. For ease of description, the following will take the dynamic random access memory (DRAM) shown in FIG. 1 as an example to illustrate the embodiments of the present invention.

As shown in FIG. 1 , the DRAM includes memory cell arrays 110 - 120 and a sense amplifier 120 . Wherein, the memory cell arrays 110 and 130 each include a plurality of bit line pairs, for example: the memory cell array 110 includes a first bit line pair PBL11 composed of bit lines BL11 and /BL11, and the memory cell array 130 includes a bit line pair PBL12 The second bit line pair PBL12 formed with /BL12. The sense amplifier 120 has a sense line pair PBLM formed by the sense lines BLM11 and BLM12, and is used to amplify signals from the bit line pair PBL11 and PBL12. In the process described below, the receiving terminals T11 - T13 in FIG. 1 are respectively used to receive the signals EQL41 , MUX41 , MUX42 and EQL42 defined in the following embodiments.

FIG. 4A is a flow chart of an updating method according to an embodiment of the present invention, and FIG. 4B is a timing diagram for explaining each signal in FIG. 4A . Please refer to FIG. 1 , FIG. 4A and FIG. 4B at the same time. First, in step S410, a sleep mode in which the memory device cannot be read and written is set. For example: step S410 will set a sleep mode, and the memory cell arrays 110 and 130 cannot be read and written in the sleep mode. After that, through step S420 , during the sleep mode, the second memory cell array, for example, the memory cell array 130 in FIG. 1 is automatically refreshed.

For example, as shown in FIG. 4B , in this embodiment, the memory cell array 130 is refreshed through the equipotential period T41 and the refresh period T42 . In this process, firstly, in step S421 , the potentials of the sensing line pair PBLM, the first bit line pair PBL11 and the second bit line pair PBL12 are switched to a reference voltage VEQL2 .

Regarding the detailed flow of step S421, as shown in FIG. 5, during the equipotential period T41, firstly, in step S510, a first equipotential control signal EQL41 and a second equipotential control signal EQL42 are provided to respectively control The conduction states of the two bit lines in the first bit line pair PBL11 and the second bit line pair PBL12. In step S520 , a first sensing control signal MUX41 and a second sensing control signal MUX42 are provided to respectively control the conduction states of the sensing line pair PBLM and the first bit line pair PBL11 and the second bit line pair PBL12 .

Afterwards, in step S530 , the levels of the first equivalence control signal EQL41 and the second equivalence control signal EQL42 are maintained at the first voltage VINT4 . At this time, the two-bit lines BL11 and /BL11 in the first bit-line pair PBL11 are turned on to each other, and are at the same potential as the reference voltage VEQL2 . Similarly, the two-bit lines BL12 and /BL12 in the second bit-line pair PBL12 are also electrically connected to each other, and are at the same potential as the reference voltage VEQL2 .

Next, in step S540 , the level of the first sensing control signal MUX41 is maintained at the first voltage VINT4 . At this time, the sensing line pair PBLM is electrically connected to the first bit line pair PBL11 and is equipotentially connected to the reference voltage VEQL2 . On the other hand, in step S550, the level of the second sensing control signal MUX42 is switched to a second voltage VSS4. Thereby, the sensing line pair PMLM and the second bit line pair PBL12 are electrically disconnected from each other, thereby helping to reduce the leakage current between the bit lines.

Please continue to refer to FIG. 4A . After the potentials of the sensing line pair PBLM, the first bit line pair PBL11 and the second bit line pair PBL12 are switched to the reference voltage during the equipotential period T41, steps S422-S425 will be used in the refresh period T42 to carry out the related memory cell array 130 updates. In more detail, in the update period T42, firstly, in step S422, the level of the first equivalence control signal EQL41 is maintained. Thereby, the first equipotential control signal EQL41 will be maintained at the first voltage VINT4 , so that the two-bit lines BL41 and /BL41 in the first bit-line pair PBL11 are mutually conducted and equipotentially reach the reference voltage VEQL2 .

Then, in step S423 , the level of the second equivalence control signal EQL12 is switched to the second voltage VSS4 . At this time, the two-bit lines BL12 and /BL12 in the second bit-line pair PBL12 are not connected to each other, and can be used to transmit signals from the memory cell array 130 respectively. Next, in step S424 , the level of the first sensing control signal MUX41 is switched to the second voltage VSS4 , so that the sensing line pair PBLM and the first bit line pair PBL11 are electrically disconnected from each other. On the other hand, in step S425, the level of the second sensing control signal MUX42 is incremented in a stepwise manner.

At this time, the level of the second sensing control signal MUX42 will switch from the second voltage VSS4 to the first voltage VINT4, and then switch from the first voltage VINT4 to a third voltage VPP4. Wherein, the third voltage VPP4>the first voltage VINT4>the second voltage VSS4, and the second voltage VSS4 is, for example, the ground voltage of the system. In this way, the formation of the conduction path between the sense line pair PBLM and the second bit line pair PBL12 can be strengthened, so that the sense amplifier 120 can amplify the signal from the second bit line pair PBL12 .

It should be noted that in the stage of signal generation, the memory cells (such as the memory cell 131 ) connected to the second bit line pair PBL12 will be turned on according to the signal SWLR transmitted by the word lines WLR0 and WLR1. At this time, the signals from the memory cells in the second bit line pair PBL12 will be generated on the bit lines BL12, /BL12 and the sensing lines BLM11, BLM12, and the signals SBLM11 and SBLM12 will be obtained in the refresh period T42 through the amplification of the sense amplifier 120 .

Please continue to refer to FIG. 4A . After the automatic update of the second memory cell array (that is, the memory cell array 130 ) is completed, the automatic update of the first memory cell array (that is, the memory cell array 110 ) will be performed in step S430 .

For example, as shown in FIG. 4B , in this embodiment, the memory cell array 110 is refreshed through the equipotential period T43 and the refresh period T44 . In this process, first, through step S431 , during the equipotential period T43 , the potentials of the sensing line pair PBLM, the first bit line pair PBL11 and the second bit line pair PBL11 are switched to the reference voltage VEQL2 . Wherein, the detailed flow of step S431 is the same as that of step S421, so it will not be repeated here.

Next, during the refresh period T44, steps S432-S435 are used to refresh the memory cell array 110. Referring to FIG. In more detail, in the update period T44, first, in step S432, the level of the first equipotential control signal EQL41 is switched to the second voltage VSS4, so that the two-bit line BL11 of the first bit-line pair PBL11 It is not connected with /BL11. Afterwards, in step S433 , the level of the second equipotential control signal EQL42 is maintained, so that the two-bit lines BL12 and /BL12 in the second bit-line pair are mutually conducted and equipotentially reach the reference voltage VEQL2 .

Next, in step S434, the level of the first sensing control signal MUX41 is switched to the third voltage VPP4, so that the sense amplifier 120 can amplify the signal from the first bit line pair PBL11. And in step S435, the level of the second sensing control signal MUX42 is maintained at the second voltage VINT4, so that the sensing line pair PBLM and the second bit line pair PBL12 are electrically disconnected from each other.

Similarly, in the stage of signal generation, the memory cells (such as the memory cell 111 ) connected to the first bit line pair PBL11 will be turned on according to the signal SWLL transmitted by the word lines WLL0 and WLL1. At this time, the signals from the memory cells in the first bit line pair PBL11 will be generated on the bit lines BL11, /BL11 and the sensing lines BLM11, BLM12, and the signals SBLM11 and SBLM12 will be obtained in the refresh period T44 through the amplification of the sense amplifier 120 .

In general, the above-mentioned processes of automatically updating the first and second memory cell arrays each include an equipotential period and a refresh period. In addition, regardless of updating the first memory cell array or the second memory cell array, this embodiment switches the potentials of the sensing line pair, the first bit line pair, and the second bit line pair to the reference voltage during the equipotential period. , and thereby reduce the leakage current between the bit lines. On the other hand, in this embodiment, during the refresh period, the potentials of the first and second bit line pairs are adjusted according to the refresh order of the first and second memory cell arrays, and accordingly the sensing line pair is at least connected to the first, second, and second memory cell arrays. One of the electrical connections for the second bit line. In this way, the two sensing lines in the sensing line pair will not be in a floating state at the same time during the update period, thereby reducing the generation of noise.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The protection scope of the invention shall be determined by the scope defined in the claims.

Claims (9)

1. the update method of a storage arrangement; It is characterized in that said update method is applicable to a storage arrangement, wherein said storage arrangement comprises an induction amplifier, one first memory cell array and one second memory cell array; Said induction amplifier has an inductive line pair; And in order to amplifying from the right signal of one first bit line in said first memory cell array, and from the right signal of one second bit line in said second memory cell array, said update method comprises:

Set the sleep pattern that said storage arrangement can't be read and write; And

During said sleep pattern, renewal said first and said second memory cell array automatically in regular turn, and:

Automatically the step of upgrading said first memory cell array comprises:

During an equipotential, with said inductive line pair, said first bit line to and the right current potential of said second bit line switch to a reference voltage, wherein said inductive line pair and said second bit line be not to electrically link to each other each other; And

In a reproducting periods; The more new sequences of foundation said first and said second memory cell array; Adjust said first with the right current potential of said second bit line; And according to this: with said inductive line pair and said first bit line to being electrically connected, perhaps with said inductive line pair and said second bit line to being electrically connected, perhaps with said inductive line pair and said first bit line to be electrically connected, and said second bit line to being electrically connected;

Automatically the step of upgrading said second memory cell array comprises:

During an equipotential, with said inductive line pair, said first bit line to and the right current potential of said second bit line switch to a reference voltage, wherein said inductive line pair and said first bit line be not to electrically link to each other each other; And

In a reproducting periods; The more new sequences of foundation said first and said second memory cell array; Adjust said first with the right current potential of said second bit line; And according to this: with said inductive line pair and said first bit line to being electrically connected, perhaps with said inductive line pair and said second bit line to being electrically connected, perhaps with said inductive line pair and said first bit line to be electrically connected, and said second bit line to being electrically connected.

2. update method as claimed in claim 1 is characterized in that, between said isoelectric period, with said inductive line pair, said first bit line to and the right current potential of said second bit line step that switches to said reference voltage comprise:

One first and one second equipotential control signal is provided, with control respectively said first bit line to and the conducting state of said second bit line pairs, two bit lines;

One first and one second sensing control signal is provided, to control said inductive line pair and said first bit line respectively to, the right conducting state of said second bit line;

Maintain one first voltage with said first with standard of said second equipotential control signal position, the first equipotential control signal causes: two bit line mutual conduction that said first bit line pairs is comprised and equipotential be said reference voltage extremely; The second equipotential control signal causes: two bit line mutual conduction that said second bit line pairs is comprised and equipotential to said reference voltage;

The standard of said first sensing control signal position is maintained said first voltage, right to cause said inductive line pair to be electrically connected to said first bit line; And

The standard of said second sensing control signal position is switched to one second voltage, to cause said inductive line pair and said second bit line to electrically not linking to each other.

3. update method as claimed in claim 2; It is characterized in that; Automatically upgrading in the process of said second memory cell array; In said reproducting periods, according to said first with the more new sequences of said second memory cell array, adjust said first and comprise with the step of the right current potential of said second bit line:

Keep the accurate position of the said first equipotential control signal, with two bit line mutual conduction and equipotential to the said reference voltage that causes said first bit line pairs; And

The standard position of the said second equipotential control signal is switched to said second voltage, to cause two bit line not conductings each other of said second bit line pairs.

4. update method as claimed in claim 2; It is characterized in that; Automatically upgrading in the process of said second memory cell array; According to this: with said inductive line pair and said first bit line to being electrically connected, perhaps with said inductive line pair and said second bit line to being electrically connected, perhaps with said inductive line pair and said first bit line to be electrically connected, and said second bit line step that is electrically connected is comprised:

The standard of said first sensing control signal position is switched to said second voltage, to cause said inductive line pair and said first bit line to electrically not linking to each other each other; And

Increase progressively the accurate position of the said second sensing control signal with stepped mode, amplify from the right signal of said second bit line to cause said induction amplifier.

5. update method as claimed in claim 4 is characterized in that, the step that increases progressively the accurate position of the said second sensing control signal with stepped mode comprises:

The standard position of the said second sensing control signal is switched to said first voltage from said second voltage; And

The standard position of the said second sensing control signal is switched to a tertiary voltage from said first voltage, and wherein said tertiary voltage is greater than said first voltage, and said first voltage is greater than said second voltage.

6. update method as claimed in claim 2; It is characterized in that; Automatically upgrading in the process of said first memory cell array; In said reproducting periods, according to said first with the more new sequences of said second memory cell array, adjust said first and comprise with the step of the right current potential of said second bit line:

The standard position of the said first equipotential control signal is switched to said second voltage, to cause two bit line not conductings each other of said first bit line pairs; And

Keep the accurate position of the said second equipotential control signal, with two bit line mutual conduction and equipotential to the said reference voltage that causes said second bit line pairs.

7. update method as claimed in claim 2; It is characterized in that; Automatically upgrading in the process of said first memory cell array; According to this: with said inductive line pair and said first bit line to being electrically connected, perhaps with said inductive line pair and said second bit line to being electrically connected, perhaps with said inductive line pair and said first bit line to be electrically connected, and said second bit line step that is electrically connected is comprised:

The standard position of the said first sensing control signal is switched to a tertiary voltage, amplify from the right signal of said first bit line to cause said induction amplifier; And

The standard position of the said second sensing control signal is maintained said second voltage; To cause said inductive line pair and said second bit line to electrically not linking to each other each other; Wherein said tertiary voltage is greater than said first voltage, and said first voltage is greater than said second voltage.

8. update method as claimed in claim 2 is characterized in that, said second voltage is a ground voltage.

9. update method as claimed in claim 1 is characterized in that said memory device is changed to dynamic RAM.

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