CN101741373B - Low voltage differential signal driver adaptive to various IO power supplies - Google Patents

Abstract

The invention discloses a low-voltage differential signal driver adaptive to multiple IO power sources, which includes: a differential conversion module, which is used to convert the low-voltage digital signal of the core into a differential voltage signal; a pre-amplifier, which is used to convert the differential voltage signal. Amplifying processing, outputting positive and negative two-way voltage signals; driving amplifying circuit, used for amplifying the positive and negative two-way output signals of the pre-amplifier to obtain the output of the driver. The invention uses the bias to change automatically with the change of the power supply, and transforms the control range of the operational amplifier to form a new circuit device. This topology separated by the low-voltage core circuit and the high-voltage IO circuit, and the bias derived from the core low-voltage and flexible adaptation to the high-voltage IO, adapt to the core voltage from low-voltage 0.9v to 1.5v, and the IO voltage from 1.8v to high-voltage 5v. In microelectronic circuits, and can be used in multi-channel LVDS drivers, the rate of data that can be transmitted reaches 1G bit rate (bps).

Description

The low-voltage differential signal driver of the multiple IO power supply of a kind of self adaptation

Technical field

The present invention relates to a kind of circuit of LVDS (Low Voltage Differential Signal, low-voltage differential signal) driver of deep-submicron, in particular a kind of microelectronic circuit that adapts to the lvds driver of multiple IO power supply.

Background technology

In the design of modem electronic circuitry, with a large amount of differential lines come in plate or plate between long distance High-speed rate signal, and wherein use maximum, be LVDS differential lines.But along with the reduction of the supply voltage of integrated circuit, integrated circuit kernel (core) voltage can fall to such an extent that form very soon very littlely, but the reduction of speed of the voltage of IO is slowly higher than core voltage, and both reductions of speed are disproportionate.

So in order to adapt to the gap of core voltage and IO power supply, people can only ceaselessly revise the circuit of lvds driver, the redesign as biasing, has brought the bottleneck of many designs.Such as, in prior art, there is a kind of technology of using the lvds driver of low-voltage, it is to utilize switchable current source to control LVDS switching tube, although can be used in the application under low pressure, but, the common-mode voltage of lvds driver output is easily unstable first, if adopt common mode feedback circuit, higher to the requirement of common mode feedback circuit; Second for biasing, describe not, cause high-pressure and low-pressure to differ and use surely simultaneously.

Visible, in prior art, there is certain problem, need to further improve.

Summary of the invention

The invention provides a kind of low-voltage differential signal driver that adapts to multiple IO power supply, it utilizes the feature that general core voltage is lower than IO power supply dexterously, for IO drive circuit provides stable biasing, and then makes IO driver can adapt to the requirement of multiple IO power supply.

For achieving the above object, the present invention adopts following technical scheme:

The low-voltage differential signal driver of the multiple IO power supply of adaptation of the present invention, it comprises: differential conversion module, for converting the digital signal of kernel low pressure to differential voltage signal; Prime amplifier, for described differential voltage signal is amplified to processing, exports positive and negative two-way voltage signal; Drive amplification circuit, amplifies processing for the positive and negative two-way output signal to described prime amplifier, obtains the output of described driver;

Biasing module, be used for only according to kernel low pressure and five bias voltages of IO power generation, these five bias voltages are VREF1, VREF2, VREF3, VREF_POP and VREF_NOP, wherein, in biasing circuit, kernel low pressure is connected to the drain electrode of NMOS pipe MLN1 by a resistance R L1, the grid leak of NMOS pipe MLN1 is connected, the source ground of NMOS pipe MLN1; The grid of NMOS pipe MLN2 is connected with the grid of NMOS pipe MLN1, the source ground of NMOS pipe MLN2; The drain electrode of NMOS pipe MLN2 is connected with the drain electrode of PMOS pipe MBP3, the grid leak of PMOS pipe MBP3 is connected, the source electrode of PMOS pipe MBP3 connects IO power supply, the grid of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is connected with the grid of PMOS pipe MBP3, and the source electrode of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is received IO power supply; The drain terminal of PMOS pipe MBP4 is connected with the drain terminal of NMOS pipe MBN3, and the source electrode of NMOS pipe MBN3 is connected with the drain electrode of NMOS pipe MBN1, and the grid of NMOS pipe MBN3 and the drain electrode of PMOS pipe MBP6 and the drain electrode of NMOS pipe MBN6 are connected; The grid leak of PMOS pipe MBP6 is connected, and the grid leak of NMOS pipe MBN6 is connected, and the source electrode of PMOS pipe MBP6 connects IO power supply, the source ground of NMOS pipe MBN6;

The drain electrode of PMOS pipe MBP5 is connected with the drain electrode of NMOS pipe MBN4, and the source electrode of NMOS pipe MBN4 is connected with the drain electrode of NMOS pipe MBN2, and bias voltage VREF1 is provided, and the grid of NMOS pipe MBN4 is connected with the output of inverter INV2 with inverter INV1;

The source ground of NMOS pipe MBN2, the grid of NMOS pipe MBN2 is connected with the grid of NMOS pipe MBN1, and the drain electrode of PMOS pipe MBOP is connected with the drain electrode of NMOS pipe MBON1, and the grid leak of NMOS pipe MBON1 is connected, and output offset voltage VREF_NOP, and the source ground of NMOS pipe MBON1;

One end of the input of inverter INV1 and resistance R L2 and one end of resistance R L3 are connected, the other end of resistance R L2 is connected to IO power supply, resistance R L2, resistance R L3, resistance R L4 are connected in series successively, that terminal that resistance R L4 is connected in series with resistance R L3 is connected with the input of inverter INV2, another connecting terminals of resistance R L4 is received the drain electrode of NMOS pipe MBN5, the grid of NMOS pipe MBN5 is connected to described bias voltage VREF1, the source electrode of NMOS pipe MBN5 is connected with one end of resistance R L6, and the other end of resistance R L6 is connected to ground; The source electrode of NMOS pipe MBN4 is connected with the grid of NMOS pipe MBN9, and source electrode and the grounded drain of NMOS pipe MBN9, formed a mos capacitance;

The source electrode of the normal phase input end of one N-type operational amplifier 1 and NMOS pipe MBN8 is all connected to kernel low pressure; The output of described N-type operational amplifier 1 is received the grid of PMOS pipe MBP9 and PMOS pipe MBOP1, and forms bias voltage VREF_POP; The source electrode of PMOS pipe MBP9 connects IO power supply, and the drain electrode of PMOS pipe MBP9 is connected to one end of resistance R L7 and the negative-phase input of described N-type operational amplifier 1, forms buffer structure; N-type operational amplifier 1 be biased to bias voltage VREF_NOP; The other end ground connection of resistance R L7, the drain electrode output offset voltage VREF3 of PMOS pipe MBOP1;

The grid leak of NMOS pipe MBN8 is connected to form bias voltage VREF2, and the drain electrode of PMOS pipe MBP8 is connected with the grid of NMOS pipe MBN8; The source electrode of PMOS pipe MBP8 connects IO power supply, and the grid of PMOS pipe MBP8 is extremely connected with the grid leak of PMOS pipe MBP7; The source electrode of PMOS pipe MBP7 connects IO power supply, the grid leak of PMOS pipe MBP7 is extremely connected, and the grid of PMOS pipe MBP7 is connected with the drain electrode of the grid of PMOS pipe MBP8, NMOS pipe MBN7, the source ground of NMOS pipe MBN7, the grid of NMOS pipe MBN7 connects bias voltage VREF1.

Described driver, wherein, described driver also comprises: be connected on the output of described prime amplifier and the buffer cell between described drive amplification circuit input end.

Described driver, wherein, described drive amplification circuit comprises: two PMOS pipe MU1 and MU2, two NMOS pipe MD1 and MD2 and resistance unit; The positive output of described prime amplifier is divided two-way, and the described buffer cell of wherein leading up to connects the grid of PMOS pipe MU1, and the described buffer cell of separately leading up to connects the grid of NMOS pipe MD1; The negative output of described prime amplifier is divided two-way, and the described buffer cell of wherein leading up to connects the grid of PMOS pipe MU2, and the described buffer cell of separately leading up to connects the grid of NMOS pipe MD2; The source electrode of two PMOS pipe MU1 and MU2 is connected, and is connected to positive bias power end VHIGH; The source electrode of two NMOS pipe MD1 and MD2 is connected, and is connected to negative bias power end VLOW; The drain electrode of PMOS pipe MU1 is connected with the drain electrode of NMOS pipe MD1, and is connected to the positive output end VOUTP of described driver; The drain electrode of PMOS pipe MU2 is connected with the drain electrode of NMOS pipe MD2, and is connected to the negative output terminal VOUTN of driver; Between described positive output end VOUTP and negative output terminal VOUTN, by described resistance unit, be connected.

Between bias voltage VREF3 and ground, be connected in series with successively resistance R 1, resistance R 2, resistance R 3 and resistance R 4; The place's of being connected in series access kernel low pressure of resistance R 2 and resistance R 3, the voltage at the place of being connected in series of resistance R 1 and resistance R 2 is the normal phase input end that bias voltage Vh is access in N-type operational amplifier, and the voltage at the place of being connected in series of described resistance R 3 and resistance R 4 is the normal phase input end that bias voltage V1 is access in P type operational amplifier.

Described driver, wherein, described positive bias power end VHIGH is connected to the drain electrode of PMOS pipe MU0, and the source electrode of PMOS pipe MU0 connects IO power supply, and the grid of PMOS pipe MU0 connects a control signal.

Driver according to claim 4, it is characterized in that, the positive supply of described positive bias power end VHIGH is to utilize bias voltage Vh to input in the buffer structure consisting of described N-type operational amplifier to obtain, and is specially the normal phase input end that bias voltage Vh inputs to described N-type operational amplifier; The negative supply of described negative bias power end VLOW is to utilize bias voltage V1 to input in the buffer structure consisting of described P type operational amplifier to obtain, and is specially the normal phase input end that bias voltage Vh inputs to described P type operational amplifier.

Described driver, wherein, described prime amplifier comprises: PMOS pipe MN3, PMOS pipe MN4, NMOS pipe MN1, NMOS pipe MN2 and NMOS pipe MNO; The differential voltage signal forming through described differential conversion module is received respectively the grid of NMOS pipe MN1 and the grid of NMOS pipe MN2, the source electrode of NMOS pipe MN1 is connected with the source electrode of NMOS pipe MN2, and connect the drain electrode of NMOS pipe MN0, the grid of NMOS pipe MN0 meets described bias voltage VREF1, the source ground of NMOS pipe MN0; The drain electrode of NMOS pipe MN1 connects the source electrode of PMOS pipe MN3, the drain electrode of NMOS pipe MN2 connects the source electrode of PMOS pipe MN4, the grid of the grid of PMOS pipe MN3 and PMOS pipe MN4 meets described bias voltage VREF2, and the drain electrode of the drain electrode of PMOS pipe MN3 and PMOS pipe MN4 connects the output of described prime amplifier; The drain electrode of PMOS pipe MN3 is connected to the drain electrode of high-voltage tube MPP1 by resistance R 1, the drain electrode of PMOS pipe MN4 is connected to the drain electrode of high-voltage tube MPP1 by resistance R 2; The source electrode of high-voltage tube MPP1 connects IO power supply.

Invention effect: the present invention utilizes biasing automatically to change with power source change, and transforms the control range of amplifier, forms new line unit.This topological structure separating by low pressure kernel circuitry and high pressure IO circuit, with derive from kernel low pressure and adapt to flexibly again the biasing of IO high pressure, adapt to core voltage from low pressure 0.9v to 1.5V, the microelectronic circuit of IO power supply from 1.8V to high pressure 5V, and can be used in multichannel lvds driver, the speed of the data that can transmit reaches 1G bit rate (bps).

Accompanying drawing explanation

Fig. 1 is the circuit block diagram of the lvds driver of the multiple IO power supply of self adaptation that proposes of the present invention;

Fig. 2 is the internal structure schematic diagram of the prime amplifier in Fig. 1 of the present invention,

Fig. 3 is the bias circuit construction schematic diagram of the multiple IO of adaptation of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in further detail.

As Fig. 1, lvds driver of the present invention comprises on the whole: connect the differential conversion module S2D of digital signal, and the prime amplifier PREDRIVER of S2D and then, and drive amplification circuit 200.Differential conversion module is for converting the digital signal of kernel low pressure to differential voltage signal; Prime amplifier, for described differential voltage signal is amplified to processing, is exported positive and negative two-way voltage signal; Drive amplification circuit, for the positive and negative two-way output signal of described prime amplifier is amplified to processing, obtains the output of described driver.

As Fig. 1, buffer BUFFER1, BUFFER2, BUFFER3 and BUFFER4 formation are connected on the buffer cell between the output of prime amplifier and the input of drive amplification circuit.Two NMOS pipes, two PMOS manage and resistance unit 201 formation drive amplification circuit 200.

The positive output end of prime amplifier PREDRIVER is connecting buffer BUFFER1 and BUFFER2, the negative output terminal of prime amplifier PREDRIVER is connecting buffer BUFFER3 and BUFFER4, the output of buffer BUFFER1 is connecting the grid of PMOS pipe MU1, the output of buffer BUFFER2 is connecting the grid of NMOS pipe MD1, the output of buffer BUFFER3 is connecting the grid of PMOS pipe MU2, and the output of buffer BUFFER4 is connecting the grid of NMOS pipe MD2.Differential conversion module S2D is kernel low pressure vddcore power supply completely.Here buffer BUFFER1, BUFFER2, BUFFER3 and BUFFER4 is used for making up the gap between different pieces of information processing speed speed.The effect of prime amplifier PREDRIVER is the driving force that increases differential signal.

PMOS pipe MU1 is connected with the source electrode of PMOS pipe MU2, and is connected to positive bias power end VHIGH end; NMOS pipe MD1 is connected with the source electrode of NMOS pipe MD2, and is connected to negative bias power end VLOW end.The VHIGH end is here the output of the buffer structure OP1 of N-type operational amplifier formation; And VLOW end is the output of the buffer structure OP2 of P type amplifier formation.For the LVDS common mode range to 1.525V at 0.875V, the input voltage Vh that can recommend buffer structure OP1 is 1.5v, and the input voltage V1 of buffer structure OP2 is 0.9v.The acquisition principle of input voltage Vh and V1 will be described in detail below.

NMOS pipe MD1 is connected with the drain electrode of PMOS pipe MU1, and is connected to the positive output end VOUTP of driver; NMOS pipe MD1 is connected with the drain electrode of PMOS pipe MU1, and is connected to the negative output terminal VOUTN of driver.The PMOS pipe MU1 here and the size of MU2 are the same large, and the size of NMOS pipe MD1 and MD2 is the same large.And, conventionally between the positive output end VOUTP of driver and the negative output terminal VOUTN of driver, by external resistance unit, be connected, such as connecting by 100 Europe resistance, as shown in Figure 1, two 50 Europe that it adopts series connection, are equivalent to 100 Europe modes.

Above-mentioned VHGH end is connected to the drain electrode of PMOS pipe MU0, and the source electrode of PMOS pipe MU0 meets IO power supply vddio, and the grid of PMOS pipe MU0 connects control signal PWDN signal, and this PWDN signal is realized lvds driver is carried out to necessary power down function.

Foregoing circuit total needs 5 biasing: VREF1, VREF2, and VREF3, VREF_POP, VREF_NOP, by biasing circuit, as Fig. 3 produces.

Fig. 3 describes biasing VREF1, VREF2, VREF3, VREF_POP, the generation circuit of VREF_NOP.From kernel low-voltage vddcore, by a resistance R L1, be connected to the drain electrode of NMOS pipe MLN1, the grid leak of NMOS pipe MLN1 pipe is connected, the source ground of NMOS pipe MLN1; The grid of NMOS pipe MLN2 is connected with the grid of NMOS pipe MLN1, and the source electrode of NMOS pipe MLN2 is ground connection also, and NMOS pipe MLN1 is the same large with the size of NMOS pipe MLN2.The drain electrode of NMOS pipe MLN2 is connected with the drain electrode of PMOS pipe MBP3, the grid leak of PMOS pipe MBP3 is also connected, the source electrode of PMOS pipe MBP3 meets IO power supply vddio, the grid of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is connected with the grid of PMOS pipe MBP3, the source electrode of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is received IO power supply vddio, and the size of PMOS pipe MBP3, PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is equally large.The drain terminal of PMOS pipe MBP4 is connected with the drain terminal of NMOS pipe MBN3, the source electrode of NMOS pipe MBN3 is connected with the drain electrode of NMOS pipe MBN1, the grid of NMOS pipe MBN3 is connected with the drain electrode of PMOS pipe MBP6 and NMOS pipe MBN6, the size of NMOS pipe MBN3, NMOS pipe MBN4 pipe is equally large, and the size of MBN1 and MBN2 pipe is the same large.PMOS pipe MBP6 and NMOS pipe MBN6 are that grid leak is connected, and MBP6 source electrode meets kernel low-voltage v ddcore, the source ground of NMOS pipe MBN6.NMOS pipe MBN1 is also that grid leak is connected, the source ground of NMOS pipe MBN1.

PMOS pipe MBP5 is connected with the drain electrode of NMOS pipe MBN4, and the source electrode of NMOS pipe MBN4 is connected with the drain electrode of NMOS pipe MBN2, and this root connecting line is reference offset voltage VREF1, and the grid of NMOS pipe MBN4 is connected with the output of inverter INV2 with inverter INV1.The source ground of NMOS pipe MBN2, the grid of NMOS pipe MBN2 is connected with the grid of NMOS pipe MBN1, and the grid leak of MBN1 is connected.The drain electrode of PMOS pipe MBOP is connected with the drain electrode of NMOS pipe MBON1, and the grid leak of NMOS pipe MBON1 is connected, and is output as bias voltage VREF_POP, and the grid leak of NMOS pipe MBON1 is connected, and the source ground of NMOS pipe MBON1.

The input of inverter INV1 with one end of resistance R L2, one end of resistance R L3 be connected, the other end of resistance R L2 is connected to IO power supply vddio, resistance R L2, resistance R L3, resistance R L4 are connected in series successively, the other end of resistance R L3 is connected with the input of INV2, one end of resistance R IM is connected to the drain electrode of NMOS pipe MBN5, the grid of NMOS pipe MBN5 is connected to bias voltage VREF1, and the source electrode of NMOS pipe MBN5 is connected with resistance R L6, and the other end of resistance R L6 is connected to ground.The output of bias voltage VREF1 is also connected with the grid of NMOS pipe MBN9, source electrode and all ground connection that drains of NMOS pipe MBN9, and MBN9 has just formed a mos capacitance like this.

The source electrode of the normal phase input end of one N-type operational amplifier and NMOS pipe MBN8 is also connected to kernel low-voltage vddcore together.

The output of N-type operational amplifier is received the grid of PMOS pipe MBP9 and PMOS pipe MBOP1, and form bias voltage VREF_POP, the source electrode of PMOS pipe MBP9 meets IO power supply vddio, the drain electrode of PMOS pipe MBP9 is connected to the negative-phase input of resistance R L7 and N-type operational amplifier, also become a kind of buffer structure, N-type operational amplifier be biased to bias voltage VREF_NOP.The other end ground connection of resistance R L7.And the drain electrode of PMOS pipe MBOP1 is exactly bias voltage VREF3.

The grid leak of NMOS pipe MBN8 is connected, and forms bias voltage VREF2, and is connected with the drain electrode of PMOS pipe MBP8.The source electrode of PMOS pipe MBP8 meets IO power supply vddio, and the grid of PMOS pipe MBP8 is extremely connected with the grid leak of PMOS pipe MBP7, and the size of PMOS pipe MBP7, PMOS pipe MBP8 pipe is equally large.The source electrode of PMOS pipe MBP7 meets 1O power supply vddio, the grid leak of PMOS pipe MBP7 is extremely connected, except being connected with the grid of PMOS pipe MBP8, and the grid of PMOS pipe MBP7 is connected with the drain electrode of the grid of PMOS pipe MBP8, NMOS pipe MBN7, the source ground of NMOS pipe MBN7, the grid of NMOS pipe MBN7 connects bias voltage VREF1.

The grid of NMOS pipe MBP8 connects the drain electrode of PMOS pipe MBP11 and the grid of NMOS pipe MBN11, the source ground of NMOS pipe MBN11, the drain electrode of PMOS pipe MBP11 connects the drain electrode of NMOS pipe MBN11 and the grid of PMOS pipe MBP11, and the source electrode of PMOS pipe MBP11 connects IO power supply vddio.

As shown in Figure 1, between bias voltage VREF3 and kernel low pressure vddcore, by series resistance R1, R2, R3, R4, receive ground successively.At R2 and R3, directly access kernel low-tension supply vddcore, at R1 and R2, directly access vh, at R3 and R4, directly access vl.For the LVDS common mode range to 1.525V at 0.875V, can recommend Vh is 1.5v, and V1 is 0.9v.Vh accesses the normal phase input end of above-mentioned N-type operational amplifier OP1, and N-type operational amplifier OP1 is connected into buffer structure, and output is connected with negative-phase input, and its output is VHIGH end, and N-type operational amplifier OP1 is biased to bias voltage VREF_NOP.

The anode of above-mentioned V1 access P type operational amplifier OP2, P type operational amplifier OP2 is also connected into buffer structure, i.e. and output is connected with negative-phase input, and its output is that VLOW holds, and P type operational amplifier OP2 is biased to bias voltage VREF_POP.

For the prime amplifier structure shown in Fig. 2, low voltage digital signal becomes differential signal VINP, VINN through differential conversion module S2D, and receive respectively the grid of NMOS pipe MN1 and NMOS pipe MN2, NMOS pipe MN1 is connected with the source electrode of NMOS pipe MN2, and the drain electrode of receiving NMOS pipe MN0, the grid of NMOS pipe MN0 meets bias voltage VREF1, the source ground of NMOS pipe MN0.The drain electrode of NMOS pipe MN1 and MN2 connects respectively the source electrode of PMOS pipe MN3 and PMOS pipe MN4, and the grid of PMOS pipe MN3 and PMOS pipe MN4 meets bias voltage VREF2, and the drain electrode of PMOS pipe MN3 and PMOS pipe MN4 meets output VOUTP and the VOUTN of prime amplifier.Meanwhile, PMOS pipe MN3 is connected to respectively the drain electrode of high-voltage tube MPP1 with the drain electrode of PMOS pipe MN4 together with resistance R 2 by resistance R 1.PMOS pipe MN3 is the same large with the size of PMOS pipe MN4, and NMOS pipe MN1 is the same large with the size of NMOS pipe MN2.The grid of high-voltage tube MPP1 connects control signal PWDN signal equally, and the source electrode of high-voltage tube MPP1 meets IO power supply vddio.The PWDN signal of MPP1 is also that lvds driver is carried out to necessary power down function, can close when being necessary the output of LVDS.Prime amplifier PREDRIVER (as Fig. 2), be to be powered by IO power supply vddio, but each biasing is that circuit provides as shown in Figure 3 like this.When practical application, can set approx the kernel low-tension supply value of biasing VREF1=1/3; The high voltage source value of the IO power supply of biasing VREF2=2/3.

From said structure, can find out, the present invention first the digital signal of kernel low pressure by singly turning two voltage signals that convert difference to, then by prime amplifier, convert the differential signal of IO high pressure to; Meanwhile, utilize kernel low pressure as the biasing in the circuit of IO high pressure, the feedback arrangement by design forms and to comprise that the many places such as pre-driver, N-type operational amplifier, P type amplifier, syntype bias setover, and makes them be adaptive to neatly the variation of IO power supply; Then by different buffer delay line, drive two couples of PMOS pipe NMOS to manage, by alternately opening PMOS pipe and NMOS, manage, make electric current from high potential through the external resistance electronegative potential of flowing through, generation Low Voltage Differential Signal.

The course of work of above-mentioned integrated circuit is described below:

First, the digital signal of kernel low pressure by singly turning two voltage signals that convert difference to, then by pre-driver, convert differential signal under IO high pressure to, by four delay line BUFFER1, BUFFER2, BUFFER3, BUFFER4 drives two couples of PMOS pipe MU1, MU2 and two NMOS pipes MD1, MD2.The time of delay of BUFFER1 and BUFFER2 is the same, and due to very zero conducting of gate pmos, NMOS tube grid is high conducting, and MU1 is conducting together with MD2; In like manner, the time of delay of BUFFER3 and BUFFER4 is the same, and MU2 is conducting together with MD1.Like this, by alternately opening PMOS pipe and NMOS, manage, make electric current from high potential through the external resistance electronegative potential of flowing through, generation Low Voltage Differential Signal.But the time of delay of BUFFER1 and BUFFER3 is more a little bit smaller a little than the time of delay of BUFFER2 and BUFFER4, be because avoid like this, MU1 and MD1, or the transient switching of MU2 and MD2, form short circuit current.

N-type operational amplifier OP1, P type operational amplifier OP2, N-type operational amplifier have been all here the effects of buffer, be because, these signals take out from resistance string, be not suitable for directly connecing capacitive load, with operational amplifier, be connected into buffer, solve well this with the ability of capacitive load.

Biasing circuit for Fig. 3, the vddcore of low pressure, by resistance R L1 and MBN1, produce stable electric current, because MBN1 and MBN2 are mirror current sources, MBP3, MBP4, MBP5, MBOP is also mirror current source, and, the electric current of MBP4, MBN3, MBN1 branch road and MBP5, MBN4, MBN2 branch road equates.What form due to MBN6 and MBP6 is the structure of two DIODE, and the grid voltage of MBN3 is exactly vddio/2, and the grid voltage of MBN1 has just been determined like this, and VREF1 is just only decided by the grid voltage of MBN4.

And in RL2, RL3, RL4, MBN5, RL6 branch road, the gate bias voltage of MBN9 is fixed, to the RL2 of proper proportion, RL3, RIM, RL6 value (as 1:8:2:0.3, or the active pull-up that RL4 is arranged to be controlled by VREF2), the input voltage of INV1 is higher, and the input voltage of INV2 is on the low side, and the grid voltage of MBN4 is just easily set vddio/2 for like this, the Size dependence of the main and current mirror MBN2 of VREF1 like this, only and vddcore, vddio be correlated with very little.When the size of MBN2 is determined, when vddcore is constant, when vddio changes (when changed to 2.5V or 1.8V from 5v or 3.3V), VREF1 can correspondingly change, but changes very littlely.When the digital signal of input is overturn, can cause that VREF1 rises or declines, and supposes to rise, the equivalent resistance of MBN5 can decline like this, thereby causes that the grid voltage of INV1 and INV2 all declines, thereby causes that the grid voltage of MBN4 rises, the equivalent resistance of MBN4 increases, and causes VREF1 to decline; Otherwise when VREF1 declines, feedback promotes VREF1 equally.And mos capacitance MBN9 also can carry out to VREF1 the effect of elimination ripple, VREF1 remains stable substantially like this.As a kind of approximate calculation, can draw

$V_{\mathrm{vref}1}\≈\frac{1}{3}{V}_{\mathrm{vddcore}}.$

In above-mentioned formula, V _vref1the size that represents bias voltage VREF1; V _vddcorethe size that represents kernel low pressure vddcore.

Due to the relation of the image current of MBP7 and MBP8, the voltage of the grid leak utmost point VREF2 of MBN8 pipe is also only relevant with the equivalent resistance of vddcore and MBN8.Because MBN11 and MBP11 are all connected into the diode structure that drain-gate joins, therefore the equivalent resistance of MBN8 is only relevant with vddio, so VREF2 is only relevant with vddcore and vddio, and VREF2 is lower than vddio, is suitable as the high-voltage tube MN3 of Fig. 2 and the bias voltage of MN4.As a kind of approximate calculation, can draw equally

$V_{\mathrm{vref}2}=V_{\mathrm{vddcore}}+R_{\mathrm{mbn}8}\≈V_{\mathrm{vddcore}}+\frac{1}{3}{V}_{\mathrm{vddio}}$

In above-mentioned formula, V _vref2the size that represents bias voltage VREF2; V _vddiothe size that represents IO power supply vddio, R _mbn8the size that represents the equivalent resistance of MBN8.

Due to the relation of the image current of MBOP and MBP3, the grid leak utmost point VREF_NOP of MBON1 pipe is only relevant with vddcore, as a kind of approximate calculation, can draw

$V_{\mathrm{vref}\_\mathrm{nop}}=\frac{V_{\mathrm{vddio}}}{V_{\mathrm{vddcore}}}\×V_{\mathrm{MLN}1}\≈1.7\×V_{\mathrm{vref}1}$

In above-mentioned formula, V _{vref_nop}the size that represents bias voltage VREF_NOP; V _mLN1the drain-source voltage that represents NMOS pipe MLN1.

The output of N-type operational amplifier drives PMOS pipe MBP9, MBP9, RL7 branch road form dividing potential drop feedback arrangement, the grid of MBP9 pipe is connected with the output stage of N-type operational amplifier, N-type operational amplifier plays the effect of buffer, like this output of N-type operational amplifier obtain one less than IO power supply vddio, the stable biasing VREF_POP relevant to vddcore only, along with the setting of the resistance of RL7, as a kind of approximate calculation, can draw

$V_{\mathrm{vref}\_\mathrm{pop}}=V_{\mathrm{vddcore}}\×\frac{R_{\mathrm{RL}7}+R_{\mathrm{mbp}9}}{R_{\mathrm{RL}7}},$

In above-mentioned formula, V _{vref_pop}the size that represents bias voltage VREF_POP; R _rL7the size that represents resistance R L7, R _mbp9the size that represents the equivalent resistance of MBP9.The value of bias voltage VREF_POP can be adjusted to the bias voltage that is applicable to very much doing P type operational amplifier.。

VREF_POP controls PMOS pipe MBOP1, obtains like this one and changes less VREF3's than vddio.Due to the effect of series circuit, the vddcore accessing between R2 and R3, for R1, R2, R3, the R4 resistance of proper proportion, the variation of voltage vh and voltage vl is also very little, and voltage vh and voltage vl are very stable.

From analysis above, the variation of visible IO power supply vddio, except impelling the Voutp of PREDRIVER and the variation of Voutn flexible adaptation vddio with moving of VREF2, VREF1, VREF3 and VREF_NOP, VREF_POP are very little with the variation of vddio, the stable LVDS signal common mode range of output that makes again of vh and v1 is little, here refer generally to 0.875v to the arrowband LVDS common mode range of 1.525v, thereby while being highly suitable for IO power source change, the variation of circuit energy self adaptation IO.Consider that LVDS broadband signal common mode range also allows the scope from 0.5v to 2.4v, adaptability of the present invention is wider, for RSDS (Reduced Swing DifferentialSignal, low-swing difference signal) and Mini-LVDS (Mini Low Voltage DifferentialSignal, little low-voltage differential signal) be also to support.

This topological structure separating by low pressure kernel circuitry and high pressure IO circuit, and derive from the biasing that kernel low pressure vddcore adapts to again IO high pressure vddio, can directly adapt to core voltage from low pressure 0.9v, to 1.5v, the microelectronic circuit of IO power supply from 1.8v to high pressure 5v, and can be used in multichannel lvds driver.Further, if from the principle of whole invention, be also can adapt to core voltage to be low to moderate 0.65v, IO power supply surpasses in the microelectronic circuit of lvds driver of high pressure 5V, but above approximate calculation formula does not re-use.

Owing to determining that the speed of whole lvds driver is mainly the switching speed of pre-driver PREDRIVER and MU1, MU2, MD1, MD2, and the gain of pre-driver PREDRIVER of the present invention is very little therefore bandwidth can be very large, and the maximum current limit that the switching speed of MU1, MU2, MD1, MD2 only tolerates, the speed of the data that therefore whole lvds driver can transmit is very high, can reach 1.3G bit rate (bps).

Should be understood that; the above-mentioned description for the specific embodiment of the invention is comparatively detailed; but can not therefore be interpreted as the restriction to scope of patent protection of the present invention; the simple and easy reasoning of all processes and conversion are all the included scopes of the present invention, and scope of patent protection of the present invention should be as the criterion with claims.

Claims (7)

1. A low-voltage differential signal driver for adaptive multiple IO power supplies, characterized in that the driver comprises: The differential conversion module is used to convert the core low-voltage digital signal into a differential voltage signal; A pre-amplifier is used to amplify the differential voltage signal and output two voltage signals, positive and negative; A driving amplifier circuit for amplifying the positive and negative output signals of the pre-amplifier to obtain the output of the driver; The bias module is used to generate five bias voltages according to the core low voltage and IO power supply. The five bias voltages are VREF1, VREF2, VREF3, VREF_POP and VREF_NOP. In the bias module, the core low voltage passes through a resistor RL1 Connected to the drain of the NMOS transistor MLN1, the gate of the NMOS transistor MLN1 is connected to the drain, the source of the NMOS transistor MLN1 is grounded; the gate of the NMOS transistor MLN2 is connected to the gate of the NMOS transistor MLN1, and the source of the NMOS transistor MLN2 is grounded; The drain of MLN2 is connected to the drain of PMOS transistor MBP3, the gate and drain of PMOS transistor MBP3 are connected, the source of PMOS transistor MBP3 is connected to the IO power supply, the gate of PMOS transistor MBP4, PMOS transistor MBP5, PMOS transistor MBOP is connected to the gate of PMOS transistor MBP3 The gates are connected, the sources of the PMOS transistor MBP4, PMOS transistor MBP5, and PMOS transistor MBOP are connected to the IO power supply; the drain of the PMOS transistor MBP4 is connected to the drain of the NMOS transistor MBN3, and the source of the NMOS transistor MBN3 is connected to the drain of the NMOS transistor MBN1 The gate of the NMOS transistor MBN3 is connected to the drain of the PMOS transistor MBP6 and the drain of the NMOS transistor MBN6; the gate of the PMOS transistor MBP6 is connected to the drain, the gate of the NMOS transistor MBN6 is connected to the drain, and the source of the PMOS transistor MBP6 is connected to the IO power supply , the source of NMOS tube MBN6 is grounded; The drain of the PMOS transistor MBP5 is connected to the drain of the NMOS transistor MBN4, the source of the NMOS transistor MBN4 is connected to the drain of the NMOS transistor MBN2, and a bias voltage VREF1 is provided, the gate of the NMOS transistor MBN4 is connected to the inverter INV1 and the inverter The output of the phase device INV2 is connected; The source of NMOS transistor MBN2 is grounded, the gate of NMOS transistor MBN2 is connected to the gate of NMOS transistor MBN1, the drain of PMOS transistor MBOP is connected to the drain of NMOS transistor MBON1, the gate and drain of NMOS transistor MBON1 are connected, and the output bias Voltage VREF_NOP, and the source of NMOS tube MBON1 is grounded; The input terminal of the inverter INV1 is connected to one end of the resistor RL2 and one end of the resistor RL3, the other end of the resistor RL2 is connected to the IO power supply, the resistor RL2, the resistor RL3, and the resistor RL4 are connected in series in sequence, and the resistor RL4 and the resistor RL3 are connected in series The terminal is connected to the input terminal of the inverter INV2, the other terminal of the resistor RL4 is connected to the drain of the NMOS transistor MBN5, the gate of the NMOS transistor MBN5 is connected to the bias voltage VREF1, the source of the NMOS transistor MBN5 is connected to the resistor RL6 One end of the resistor RL6 is connected to the ground; the source of the NMOS transistor MBN4 is connected to the gate of the NMOS transistor MBN9, and the source and drain of the NMOS transistor MBN9 are grounded to form a MOS capacitor; The non-inverting input terminal of an N-type operational amplifier 1 and the source of the NMOS transistor MBN8 are all connected to the core low voltage; the output terminal of the N-type operational amplifier 1 is connected to the gates of the PMOS transistor MBP9 and the PMOS transistor MBOP1, and forms a bias Set the voltage VREF_POP; the source of the PMOS tube MBP9 is connected to the IO power supply, and the drain of the PMOS tube MBP9 is connected to one end of the resistor RL7 and the negative input terminal of the N-type operational amplifier 1 to form a buffer structure; the N-type operational amplifier 1 The bias is the bias voltage VREF_NOP; the other end of the resistor RL7 is grounded, and the drain of the PMOS tube MBOP1 outputs the bias voltage VREF3; The gate and drain of the NMOS transistor MBN8 are connected to form a bias voltage VREF2, the drain of the PMOS transistor MBP8 is connected to the gate of the NMOS transistor MBN8; the source of the PMOS transistor MBP8 is connected to the IO power supply, the gate of the PMOS transistor MBP8 is connected to the gate of the PMOS transistor MBP7 The drain is connected; the source of the PMOS transistor MBP7 is connected to the IO power supply, the gate and drain of the PMOS transistor MBP7 are connected, and the gate of the PMOS transistor MBP7 is connected to the gate of the PMOS transistor MBP8 and the drain of the NMOS transistor MBN7, and the drain of the NMOS transistor MBN7 The source is grounded, and the gate of the NMOS transistor MBN7 is connected to the bias voltage VREF1. the 2. The driver according to claim 1, further comprising: a buffer unit connected in series between the output terminal of the pre-amplifier and the input terminal of the driving amplifier circuit. the 3. The driver according to claim 2, wherein the drive amplifier circuit comprises: two PMOS transistors MU1 and MU2, two NMOS transistors MD1 and MD2, and a resistance unit; The positive output of the pre-amplifier is divided into two paths, one of which is connected to the gate of the PMOS transistor MU1 through the buffer unit, and the other is connected to the gate of the NMOS transistor MD1 through the buffer unit; the negative output of the pre-amplifier is divided into two One of them is connected to the gate of PMOS transistor MU2 through the buffer unit, and the other is connected to the gate of NMOS transistor MD2 through the buffer unit; the sources of the two PMOS transistors MU1 and MU2 are connected and connected to the positive bias Power supply terminal VHIGH; the sources of the two NMOS transistors MD1 and MD2 are connected and connected to the negative bias power supply terminal VLOW; the drain of the PMOS transistor MU1 is connected to the drain of the NMOS transistor MD1 and connected to the positive output of the driver terminal VOUTP; the drain of the PMOS transistor MU2 is connected to the drain of the NMOS transistor MD2, and connected to the negative output terminal VOUTN of the driver; the positive output terminal VOUTP and the negative output terminal VOUTN are connected through the resistance unit. the 4. The driver according to claim 3, wherein a resistor R1, a resistor R2, a resistor R3 and a resistor R4 are sequentially connected in series between the bias voltage VREF3 and the ground; the serial connection of the resistor R2 and the resistor R3 is connected to Into the core low voltage, the voltage at the series connection of resistor R1 and resistor R2 is the bias voltage Vh is connected to the non-inverting input terminal of the N-type operational amplifier, the voltage at the series connection of the resistor R3 and resistor R4 is the bias voltage V1 is connected to the non-inverting input of the P-type operational amplifier. the 5. The driver according to claim 3, wherein the positive bias power supply terminal VHIGH is connected to the drain of the PMOS transistor MU0, the source of the PMOS transistor MU0 is connected to the IO power supply, and the gate of the PMOS transistor MU0 is connected to a control signal. the 6. The driver according to claim 4, wherein the positive power supply of the positive bias power supply terminal VHIGH is obtained by inputting the bias voltage Vh into the buffer structure formed by the N-type operational amplifier, specifically The bias voltage Vh is input to the positive phase input terminal of the N-type operational amplifier; the negative power supply of the negative bias power supply terminal VLOW is input into the buffer structure composed of the P-type operational amplifier by using the bias voltage V1 The obtained, specifically, the bias voltage Vh is input to the non-inverting input terminal of the P-type operational amplifier. the 7. The driver according to claim 1, wherein the pre-amplifier comprises: PMOS transistor MN3, PMOS transistor MN4, NMOS transistor MN1, NMOS transistor MN2, and NMOS transistor MN0; The voltage signal is respectively connected to the gate of NMOS transistor MN1 and the gate of NMOS transistor MN2, the source of NMOS transistor MN1 is connected to the source of NMOS transistor MN2, and connected to the drain of NMOS transistor MN0, and the gate of NMOS transistor MN0 is connected to The bias voltage VREF1, the source of the NMOS transistor MN0 is grounded; the drain of the NMOS transistor MN1 is connected to the source of the PMOS transistor MN3, the drain of the NMOS transistor MN2 is connected to the source of the PMOS transistor MN4, and the gate of the PMOS transistor MN3 and The gate of the PMOS transistor MN4 is connected to the bias voltage VREF2, the drains of the PMOS transistor MN3 and the drain of the PMOS transistor MN4 are connected to the output end of the pre-amplifier; the drain of the PMOS transistor MN3 is connected to the high voltage transistor MPP1 through a resistor R1 The drain of the PMOS tube MN4 is connected to the drain of the high-voltage tube MPP1 through the resistor R2; the source of the high-voltage tube MPP1 is connected to the IO power supply. the

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