CN101740410B - Manufacturing process of chip packaging structure - Google Patents

Abstract

The manufacturing process of a chip package structure is as follows. First, a patterned conductive layer and a patterned solder mask layer are provided, wherein the patterned solder mask layer is disposed on the patterned conductive layer. And then, bonding a plurality of chips to the patterned conductive layer so that the chips and the patterned solder mask layer are respectively arranged on two opposite surfaces of the patterned conductive layer. Then, the chip is electrically connected to the patterned conductive layer by a plurality of wires, wherein the chip and the wires are located on the same side of the patterned conductive layer. And finally, forming a packaging colloid to coat the patterned conductive layer, the chip and the lead. Then, the encapsulant, the patterned conductive layer and the patterned solder mask layer are separated. The manufacturing process of the chip packaging structure can manufacture the chip packaging structure under the condition of not using a core dielectric layer, so that the thickness of the manufactured chip packaging structure is smaller than that of the conventional chip packaging structure.

Description

Manufacturing process of chip packaging structure

technical field

The present invention relates to a manufacturing process of a chip packaging structure, and in particular to a manufacturing process of a thinner chip packaging structure.

Background technique

In the semiconductor industry, the manufacturing process of integrated circuits (IC) is mainly divided into three stages: integrated circuit design, integrated circuit manufacturing and integrated circuit packaging.

In the manufacturing process of an integrated circuit, a chip is completed through steps such as wafer fabrication, circuit design, and wafer dicing. The wafer has an active surface, which is the surface on which a plurality of active devices are formed. After forming the integrated circuits in the wafer, a plurality of pads are formed on the active surface of the wafer, so that chips formed by dicing the wafer can be electrically connected to the carrier through the pads. The carrier can be a lead frame or a circuit board. The chip is electrically connected to the carrier through wire bonding or flip chip bonding, wherein the pads of the chip are electrically connected to the pads of the carrier to form a chip package structure.

Generally speaking, the existing circuit board manufacturing process must use the core dielectric layer, and the patterned circuit layer and the patterned dielectric layer are fully additive process or semi-additive process. , subtractive process or other suitable methods are alternately stacked on the core dielectric layer. It can be known from the foregoing that the thickness of the core dielectric layer is the main part of the total thickness of the circuit board. Therefore, if the thickness of the core dielectric layer cannot be effectively reduced, it will be unfavorable to reduce the total thickness of the chip packaging structure.

Contents of the invention

The invention provides a manufacturing process of a chip packaging structure, which can produce a thinner chip packaging structure.

The present invention proposes a manufacturing process of a chip packaging structure as follows. Firstly, a patterned conductive layer and a patterned solder resist layer are provided, and the patterned solder resist layer is disposed on the patterned conductive layer. Then, a plurality of chips are bonded to the patterned conductive layer, so that the chips and the patterned solder resist layer are respectively arranged on two opposite surfaces of the patterned conductive layer. Then, the chip is electrically connected to the patterned conductive layer by a plurality of wires, wherein the chip and the wires are located on the same side of the patterned conductive layer. After that, at least one encapsulation compound is formed to cover the patterned conductive layer, the chip and the wires. Then, the encapsulant, the patterned conductive layer and the patterned solder resist layer are separated to form at least one package.

In an embodiment of the present invention, a method for providing a patterned conductive layer and a patterned solder resist layer is as follows. First, a conductive layer is provided. Next, a solder resist layer is formed on the conductive layer. Then, the solder resist layer is patterned to form a patterned solder resist layer, wherein the patterned solder resist layer exposes part of the conductive layer. Afterwards, the conductive layer is patterned to form a patterned conductive layer.

In an embodiment of the present invention, a method for providing a patterned conductive layer and a patterned solder resist layer is as follows. First, a solder mask is provided. Next, a conductive layer is formed on the solder resist layer. Then, the solder resist layer is patterned to form a patterned solder resist layer, wherein the patterned solder resist layer exposes part of the conductive layer. Afterwards, the conductive layer is patterned to form a patterned conductive layer.

In an embodiment of the present invention, a method for providing a patterned conductive layer and a patterned solder resist layer is as follows. First, a conductive layer is provided. Then, a solder resist layer is formed on the conductive layer. Afterwards, the conductive layer is patterned to form a patterned conductive layer. Then, the solder resist layer is patterned to form a patterned solder resist layer, wherein the patterned solder resist layer exposes part of the patterned conductive layer.

In an embodiment of the present invention, a method for providing a patterned conductive layer and a patterned solder resist layer is as follows. First, a solder mask is provided. Next, a conductive layer is formed on the solder resist layer. Then, the conductive layer is patterned to form a patterned conductive layer. After that, the solder resist layer is patterned to form a patterned solder resist layer, wherein the patterned solder resist layer exposes part of the patterned conductive layer.

In an embodiment of the invention, a plurality of chip pads and a plurality of pins are formed on the patterned conductive layer.

In an embodiment of the invention, a plurality of openings are formed on the patterned solder resist layer.

In an embodiment of the present invention, the manufacturing process of the chip package structure further includes forming an external electrode in each opening, and the external electrode is electrically connected to the patterned conductive layer through the opening.

In an embodiment of the present invention, the manufacturing process of the chip packaging structure further includes forming an adhesive layer between the chip and the patterned conductive layer.

In an embodiment of the present invention, the adhesive layer between the chip and the patterned conductive layer is a B-stage adhesive layer.

In one embodiment of the present invention, the B-stage adhesive layer is pre-formed on a backside of the chip.

In one embodiment of the invention, before the chip is attached to the patterned conductive layer, a B-stage adhesive layer is formed on the patterned conductive layer.

Based on the above, the manufacturing process of the chip packaging structure of the present invention can produce a chip packaging structure without using a core dielectric layer, so the thickness of the chip packaging structure produced by the manufacturing process of the chip packaging structure of the present invention is less than The thickness of the existing chip packaging structure.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

1A to 1G are cross-sectional views of a chip packaging structure according to an embodiment of the present invention.

Description of main component symbols:

100, 100': chip package structure

110: conductive layer

110': patterned conductive layer

112: First Surface

114: second surface

116: chip pad

118: pin

120: patterned solder mask

122: opening

130: chip

132: active surface

134: back

136: Pad

140: Adhesive layer

150: wire

160, 160': encapsulation colloid

170: External electrode

Detailed ways

The embodiments of the present invention can refer to the corresponding drawings, and parts with the same number in the drawings or descriptions are the same or similar to each other.

1A to 1G are cross-sectional views of a chip packaging structure according to an embodiment of the present invention. Referring to FIG. 1A , a conductive layer 110 and a patterned solder resist layer 120 are provided, wherein the conductive layer 110 has a first surface 112 and a second surface 114 opposite to each other, and the patterned solder resist layer 120 has a plurality of openings 122 . In addition, the patterned solder resist layer 120 is disposed on the first surface 112 of the conductive layer 110 , and the opening 122 exposes part of the first surface 112 of the conductive layer 110 . In a preferred embodiment, a brown oxidation process or a black oxidation process may be applied to the conductive layer 110 to increase the surface roughness of the conductive layer 110 . In this way, the bonding degree between the conductive layer 110 and the patterned solder resist layer 120 can be improved.

In this embodiment, the method for forming the patterned solder resist layer 120 is to attach a B staged film (B staged film) on the first surface 112 of the conductive layer 110, wherein the B staged film is also a solder resist layer, And the solid solder resist layer can be patterned to form the patterned solder resist layer 120 before or after being attached to the conductive layer 110 . In one embodiment, the patterned solder resist layer 120 is formed by coating a liquid solder resist material (such as a B-stage liquid solder resist material) on the first surface 112 of the conductive layer 110 to form a liquid solder resist layer. The material layer is then cured and patterned to form the patterned solder resist layer 120. The curing method can be by heating or irradiating ultraviolet light.

Next, referring to FIG. 1B , the conductive layer 110 is patterned by exposure, development and etching to form a patterned conductive layer 110 ′, wherein the patterned conductive layer 110 ′ has a plurality of chip pads 116 and a plurality of pins 118 , And the patterned solder resist layer 120 exposes part of the first surface 112 of the patterned conductive layer 110 ′. It should be noted that the sequence of the aforementioned patterning process for forming the patterned conductive layer 110' and the patterned solder resist layer 120 is not intended to limit the present invention. In a preferred embodiment, a plating process can be performed to form a plating conductive layer (not shown) on the pin 118 . The aforementioned electroplated conductive layer can be a nickel/gold laminate or other suitable metal layers.

Then, referring to FIG. 1C , a plurality of chips 130 are adhered to the second surface 114 of the patterned conductive layer 110 ′, and the chips 130 are respectively disposed on the chip pads 116 . Then, a plurality of wires 150 are formed to connect the pins 118 and the chip 130, wherein each chip 130 has an active surface 132, a back surface 134 opposite to the active surface 132, and a plurality of contacts disposed on the active surface 132. Pad 136. Each chip 130 is adhered to the patterned conductive layer 110' by an adhesive layer 140 disposed between the chip 130 and the patterned conductive layer 110'.

In this embodiment, the wires 150 are formed by wire bonding, and each wire 150 is electrically connected to a pin 118 and a pad 136 . The wire 150 is, for example, a gold wire.

In this embodiment, the adhesive layer 140 is, for example, a B-stage adhesive layer. The B-stage adhesive layer can be ABLESTIK's 8008 or 8008TH. In addition, the B-stage adhesive layer can also be 6200, 6201 or 6202 of ABLESTIK or SA-200-6 and SA-200-10 provided by HITACHI Chemical CO., Ltd. In one embodiment of the invention, the B-stage adhesive layer 140 is formed on the backside of the wafer. When the wafer is diced, a plurality of chips 130 may be formed, and the chips 130 have an adhesive layer 140 on the backside 134 thereof. Therefore, the B-stage adhesive layer 140 is favorable for mass production. In addition, the formation method of the B-stage adhesive layer 140 includes spin coating, printing or other suitable processes. More specifically, the adhesive layer 140 is formed on the backside 134 of the chip 130 . Specifically, a wafer can be provided first, which has a plurality of chips 130 arranged in an array. Then, a second-stage adhesive layer is formed on the back surface 134 of the chip 130 , and the second-stage adhesive layer is partially cured by heating or irradiating ultraviolet light to form the B-stage adhesive layer 140 . In addition, the B-stage adhesive layer 140 may be pre-formed on the patterned conductive layer 110' before the chip 130 is adhered to the patterned conductive layer 110'.

In this embodiment, the B-stage adhesive layer 140 is fully cured after the chip 130 is adhered to the patterned conductive layer 110', or after the chip 130 is coated with an encapsulant. In other embodiments, a curing process may be performed on the B-stage adhesive layer 140 to be completely cured.

Next, please refer to FIG. 1D , an encapsulant 160 covers the patterned conductive layer 110 ′, the chip 130 and the wire 150 . The material of the encapsulant 160 is, for example, epoxy resin. Then, a plurality of external electrodes 170 are respectively formed in the openings 122 to electrically connect the patterned conductive layer 110'. The external electrodes 170 are, for example, solder balls.

Please refer to FIG. 1E , compared to FIG. 1D which forms encapsulant 160 to cover patterned conductive layer 110 ′, patterned solder mask 120 , chip 130 and wire 150 , FIG. 1E forms multiple encapsulant 160 ′ to enclose Overlay the patterned conductive layer 110 ′, the patterned solder resist layer 120 , the chip 130 and the wire 150 .

Please refer to FIG. 1F and FIG. 1G, the structure in FIG. 1D or FIG. 1E can be separated into multiple chip packaging structures 100 (as shown in FIG. 1F) or multiple chip packaging structures 100' (as shown in FIG. 1G ), wherein Methods of separation include punching or sawing.

As shown in FIG. 1F , the chip packaging structure 100 of this embodiment mainly includes a patterned conductive layer 110 ′, a patterned solder resist layer 120 , a chip 130 , a plurality of wires 150 and an encapsulant 160 . The patterned conductive layer 110' has a first surface 112 and a second surface 114 opposite to each other. The patterned solder mask layer 120 is disposed on the first surface 112 . The patterned solder resist layer 120 exposes a portion of the first surface 112 . The chip 130 is disposed on the second surface 114 of the patterned conductive layer 110'. The wire 150 is electrically connected to the chip 130 and the patterned conductive layer 110'. The encapsulant 160 covers the patterned conductive layer 110 ′, the chip 130 and the wire 150 .

To sum up, compared with the existing manufacturing process of the chip packaging structure, the manufacturing process of the present invention can produce a chip packaging structure with no core dielectric layer and a smaller thickness. Therefore, the present invention can reduce manufacturing cost and increase yield.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (10)

1. A manufacturing process of a chip packaging structure, comprising: providing a patterned conductive layer and a patterned solder resist layer, wherein the patterned solder resist layer is disposed on the patterned conductive layer; bonding a plurality of chips to the patterned conductive layer, so that the chips and the patterned solder resist layer are respectively disposed on two opposite surfaces of the patterned conductive layer; electrically connecting the chips to the patterned conductive layer via a plurality of wires, wherein the chips and the wires are located on the same side of the patterned conductive layer; forming at least one encapsulant to cover the patterned conductive layer, the chips and the wires; and separating the packaging colloid, the patterned conductive layer and the patterned solder resist layer, Wherein an adhesive layer is formed between the chips and the patterned conductive layer, and the adhesive layer is a B-stage adhesive layer. 2. The manufacturing process of the chip package structure according to claim 1, wherein the method for providing the patterned conductive layer and the patterned solder resist layer comprises: providing a conductive layer; forming a solder resist layer on the conductive layer; patterning the solder resist layer to form the patterned solder resist layer, wherein the patterned solder resist layer exposes a portion of the conductive layer; and The conductive layer is patterned to form the patterned conductive layer. 3. The manufacturing process of the chip package structure according to claim 1, wherein the method for providing the patterned conductive layer and the patterned solder resist layer comprises: Provide a solder mask; forming a conductive layer on the solder resist layer; patterning the solder resist layer to form the patterned solder resist layer, wherein the patterned solder resist layer exposes a portion of the conductive layer; and The conductive layer is patterned to form the patterned conductive layer. 4. The manufacturing process of the chip package structure according to claim 1, wherein the method for providing the patterned conductive layer and the patterned solder resist layer comprises: providing a conductive layer; forming a solder resist layer on the conductive layer; patterning the conductive layer to form the patterned conductive layer; and The solder resist layer is patterned to form the patterned solder resist layer, wherein the patterned solder resist layer exposes a portion of the patterned conductive layer. 5. The manufacturing process of the chip package structure according to claim 1, wherein the method for providing the patterned conductive layer and the patterned solder resist layer comprises: Provide a solder mask; forming a conductive layer on the solder resist layer; patterning the conductive layer to form the patterned conductive layer; and The solder resist layer is patterned to form the patterned solder resist layer, wherein the patterned solder resist layer exposes a portion of the patterned conductive layer. 6. The manufacturing process of the chip packaging structure as claimed in claim 1, wherein a plurality of chip pads and a plurality of leads are formed on the patterned conductive layer. 7. The manufacturing process of the chip packaging structure as claimed in claim 1, wherein a plurality of openings are formed on the patterned solder resist layer. 8. The manufacturing process of the chip packaging structure according to claim 7, further comprising: An external electrode is formed in each of the openings, and the external electrodes are electrically connected to the patterned conductive layer through the openings. 9. The manufacturing process of the chip packaging structure as claimed in claim 1, wherein the B-stage adhesive layer is pre-formed on a back surface of the chip. 10 . The process for manufacturing a chip package structure as claimed in claim 1 , wherein the B-stage adhesive layer is formed on the patterned conductive layer before the chip is adhered to the patterned conductive layer. 11 .

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