CN101740102B - Multichannel flash memory chip array structure and writing and reading method thereof - Google Patents

Abstract

The invention relates to a multi-channel flash memory chip array structure and a writing and reading method thereof, which solve the defect of low data reading and writing speed of a flash memory in the prior art. The flash memory chip comprises a plurality of channels formed by flash memory chips, data buses, control buses and chip selection signal lines, wherein each flash memory chip corresponds to one chip selection signal line, the chip selection signal lines of each chip are independent, and all flash memory chips in each channel share one data bus and one control bus which are independent of other channels. When data is written, the command and the address information are transmitted to the command analysis unit through the command interface; starting a data interface management unit and a channel arbitration unit; the channel arbitration unit pre-allocates the channel according to the address information and transmits the pre-allocated channel to the channel arbitration unit and the data allocation unit; writing the data into the cache of the corresponding channel, and starting a corresponding flash memory time sequence generation module by a channel arbitration unit; and finally writing the data into the flash memory chip. The flash memory has high read-write speed and high data write reliability.

Description

A multi-channel flash memory chip array structure and writing and reading methods thereof

technical field

The invention relates to a storage device and its writing and reading method, in particular to a multi-channel flash memory array structure and its writing and reading method.

Background technique

As a new non-volatile storage medium, flash memory has become very popular in the field of consumer electronics due to its many advantages such as high storage density, easy portability, low power consumption, long data retention time after power failure, and good shock resistance. In the field of industry and military industry, it has also received more and more attention and popularity. In some large-capacity data storage applications, there are often multiple slices of flash memory cascaded or used as an entire column to expand storage space and improve data throughput. However, since the flash memory needs to wait for a long time after data is written, to ensure that the data is written correctly. Typically, a write needs to wait for 200us, and the maximum waiting time needs to be 700us. If you follow the normal operation idea and wait after writing data into the flash memory, the data writing speed will be very slow, which cannot meet the actual use requirements.

In the process of using flash memory, the core issue is how to improve the read and write speed of data. Among the existing solutions, some also use multiple channels, but share one data bus, which cannot realize parallel processing in the true sense; some use multiple buses, and each bus also has multiple chips , but the management method of multiple chips on each channel cannot be processed in parallel, and the write waiting time of each chip is sacrificed in order to achieve high write speed, which will reduce the unreliability of data.

Contents of the invention

The purpose of the present invention is to solve the defect of slow read and write speed of flash memory data in the prior art, and provide a multi-channel flash memory array structure capable of fast reading and writing of flash memory and its writing and reading methods.

Technical solution of the present invention is:

A multi-channel flash memory chip array structure, including a plurality of channels composed of flash memory chips, a data bus connected to the flash memory chip, a control bus, and a chip selection signal line, each flash memory chip corresponds to a chip selection signal line, each The chip selection signal line of the chip is independent, and its special features are:

All the flash memory chips in each channel share a data bus and a control bus independent of other channels.

A multi-channel flash memory chip array structure, including a plurality of channels composed of flash memory chips, a data bus connected to the flash memory chip, a control bus, and a chip selection signal line, and its special features are:

The flash memory chips in each channel are cascaded after forming a flash memory chipset, and all chipsets in each channel share a data bus and a control bus independent of other channels, and the chips in each chipset share a control bus and chip select signal bus.

A multi-channel flash memory writing method whose special features are:

Contains the following steps:

1], command and address information are passed to the command parsing unit through the command interface;

2], after the order analysis unit receives the order, start the data interface management unit and the channel arbitration unit;

3], the channel arbitration unit performs channel pre-allocation according to the address information, and at the same time, the data interface management unit reads data from the data interface and passes it to the channel arbitration unit and the data allocation unit;

4], the data allocation unit directly writes the data into the cache of the corresponding channel according to the allocated channel number, and then the channel arbitration unit starts the corresponding flash memory timing generation module;

5], the corresponding flash memory sequence generation module writes the data in the channel cache into the flash memory chip through the common control bus and data bus in the channel corresponding to the flash memory sequence generation module;

6], when the data distribution unit finishes writing data to a certain channel, when there is still data to be written, it can read data from the data interface again, and carry out the data writing work of the next cycle.

When the data in the above step 5] is written into the flash memory chip, the following steps are included:

501], occupying the actual writing time of the first flash memory chip in the corresponding channel, and writing data to the first flash memory chip through the control bus and the data bus;

502], using the write waiting time of the current flash memory chip, continue to write data to the next flash memory chip through the control bus and the data bus;

503], according to the method of step 502], using the write waiting time of the first flash memory chip, write data to the remaining flash memory chips in the channel in turn, until all the flash memory chips in the channel complete a data writing work, and when The write waiting time of the first flash memory chip is over, and the write operation in the corresponding channel is completed for one week;

504], return to step 501], re-write data to the first flash memory chip, and start a new write operation until all data writing is completed, and the cycle writing operation is completed.

A multi-channel flash memory readout method, its special features are:

Contains the following steps:

1], command and address information are passed to the command parsing unit through the command interface;

2], after the command analysis unit analyzes the data and commands, the converted commands and addresses are passed to the channel arbitration and data allocation unit;

3], start the timing generation module of the corresponding channel through the channel arbitration unit;

4], read data from the flash memory chip through the common control bus and data bus in the channel corresponding to the flash memory timing generation module, and store it in the corresponding channel cache;

5], notify the channel arbitration and data allocation unit, read data from the channel buffer, and pass the data to the data interface through the data interface management unit;

6] When the data interface management unit completes the data readout to a certain channel, when there is still data to be read out, it can read data from the flash memory chip again, and perform the data readout work of the next cycle.

The present invention has the following advantages:

1. The read and write speed of flash memory is fast. In terms of speed, it can break through the theoretical reading and writing speed of flash memory, so that the reading and writing speed of flash memory can reach more than 100MByte/s, so as to adapt to high-speed interface standards such as PATA, SATA, 1394 and USB.

2. High reliability of data writing. In terms of reliability, wait strictly according to the time characteristics of flash memory operation to ensure the reliability of data under various conditions.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a flash memory chip array according to the present invention.

FIG. 2 is a schematic diagram of the method for managing the read-write pipeline of the flash memory chip in each channel of the present invention.

Fig. 3 is a flowchart of reading and writing data of a flash memory chip according to the present invention.

Detailed ways

A multi-channel flash memory chip array structure of the present invention includes a plurality of channels formed by flash memory chips, a data bus connected to the flash memory chip, a control bus, and a chip selection signal line, and each flash memory chip corresponds to a chip selection signal line , the chip select signal line of each chip is independent, and all flash memory chips in each channel share a data bus and a control bus independent of other channels. When the flash memory chips in each channel form a cascaded flash memory chipset, the chipset is composed of 2 or 4 chips into a 16-bit or 32-bit wide data bus. The purpose of building the chipset is to increase the bit width and increase the unit The writing speed of the data within the time, the chips in the chipset share the control bus and the chip select bus, and the data bus is not shared.

The present invention adopts a multi-channel, that is, a multi-dimensional array method to manage flash memory chips, and the structure of the flash memory chip array is shown in FIG. 1 . A row-column structure is composed of multiple chips. Form a flash array. For example, there are 16 flash memory chips in each row, and every two flash memory chips form a pair to form a 16-bit data bus, and each pair of chips shares a control bus and a chip select signal line. Eight pairs of flash memory chips share a 16-bit data bus and a common control bus. The chip select signal lines of each pair of chips are independent. A 16-bit data bus and a control bus shared by the 8 pairs of chips, and chip select signal lines corresponding to each pair of chips together form an independent channel.

The flash memory chips in each channel share a data bus and a control bus through cascading, and each chip has its own independent chip select signal. Since there are multiple chips on one bus, for example, multi-channel 4-pair chip cascading as shown in Figure 1 can be adopted, and the method for reading and writing flash memory chips of the present invention improves the bus utilization rate, thereby increasing the writing speed of data. In the present invention, each flash memory channel has its own independent channel cache, an independent timing generation module, and a byte-independent data and control bus. In this way, multiple channels can work in parallel without affecting each other. Moreover, the automatic allocation of data to each channel is realized by hardware logic, which greatly improves the data transmission speed. The entire flash memory chip array is composed of multiple channels. Theoretically, the reading and writing speed of data is doubled for each additional channel, which breaks through the limit of the ultimate reading and writing speed of flash memory. While expanding the storage capacity, it can also double the data throughput. Throughput rate. The number of channels of the array can be determined according to actual needs. Theoretically, if the resources of the MCU or FPGA controlling the flash memory are sufficient, and there is no speed bottleneck at the front end, then the read/write speed of the flash memory has no upper limit by adopting the method provided by the present invention.

The flash memory array management method of the present invention is realized based on FPGA. The dotted line in Figure 3 describes the management unit of the multi-channel flash memory array structure, where the management unit consists of the following parts: command analysis unit, data interface management unit, channel arbitration and data allocation unit, each channel cache and each channel Flash timing generation unit.

Each channel corresponds to its own independent channel buffer and flash timing generation unit, and each flash timing generation unit corresponds to a flash memory data bus and data bus, that is, it controls a row of flash memory chips. in,

The command parsing unit is responsible for communicating with the external microcontroller, parsing the incoming commands from the outside, and passing these commands to the internal modules of the management unit, which is the command channel of the entire management unit.

The data interface management unit is responsible for data transfer, similar to the function of a DMA controller. The Chinese name of DMA is direct memory access. It is a computer working mode that directly exchanges data with memory without going through the CPU. Its advantage is that it reduces the burden on the CPU and greatly improves the speed of data interaction.

The channel arbitration and data allocation unit is responsible for the allocation of data to the channel.

The data interface is responsible for reading data from the external data memory or external data bus or transmitting data to the outside, and is the data channel of the entire management unit. The data interface can be an external memory or the data bus of the microcontroller.

The command interface can be a dual-port RAM memory, or the control bus of a microcontroller.

A kind of multi-channel flash memory writing method of the present invention comprises the following steps:

1], command and address information are passed to the command parsing unit through the command interface;

2], after the order analysis unit receives the order, start the data interface management unit and the channel arbitration unit;

3], the channel arbitration unit performs channel pre-allocation according to the address information, and at the same time, the data interface management unit reads data from the data interface and passes it to the channel arbitration unit and the data allocation unit;

4], the data allocation unit directly writes the data into the cache of the corresponding channel according to the allocated channel number, and then the channel arbitration unit starts the corresponding flash memory timing generation module;

5], the corresponding flash memory sequence generation module writes the data in the channel cache into the flash memory chip through the common control bus and data bus in the channel corresponding to the flash memory sequence generation module;

6], when the data distribution unit finishes writing data to a certain channel, when there is still data to be written, it can read data from the data interface again, and carry out the data writing work of the next cycle.

In Figure 3, several units on the left side of the channel cache work together, and are only responsible for moving data on the data interface to the idle channel cache; the flash timing generation module on the right side of the channel cache is responsible for writing data to each flash memory chip in this channel. These two parts work in parallel without affecting each other, which greatly improves the data throughput.

When the timing generation module of each channel manages the chips of the channel, for example, there are 4 chips in the channel, the pipeline management method for reading and writing flash memory chips in each channel as shown in FIG. 2 is adopted. After writing the first chipset, let the chips of the current chipset be in the write waiting state, and immediately transfer to the operation of the next chip, and do not make the bus idle because the first group of chips is in the write waiting state. By analogy, when the loop operation returns to the first chip set after one week, the write waiting time of the first set of chips is completed, and the next round of operation can be performed. This method of pipeline management chipset ensures that the data bus of each channel is always in a busy state, thereby improving the data transmission speed of each channel. Moreover, since the write waiting time of each chip is guaranteed, the reliability of data writing is guaranteed.

Therefore, in the above step 5], the data writing of each single channel may also include the following steps:

501], occupying the actual writing time of the first flash memory chip in the corresponding channel, and writing data to the first flash memory chip through the control bus and the data bus;

502], utilizing the write waiting time of the first flash memory chip, continue to write data to the next flash memory chip through the control bus and the data bus;

503], according to the method of step 502], using the write waiting time of the current flash memory chip, write data to the remaining flash memory chips in the channel in turn, until all the flash memory chips in the channel complete a data writing work, and when the first The write waiting time of a flash memory chip is over, and the write operation in the corresponding channel is completed for one week;

504], return to step 501], re-write data to the first flash memory chip, and start a new write operation until all data writing is completed, and the cycle writing operation is completed.

The meaning of the step 504] is that when the flash memory chip still has data to be written after one cycle of writing is completed, the data is written in a cycle according to steps 501] to 503] until the writing of all data is completed . This ensures that the data bus in each channel is always in a busy state, and the speed will not be reduced due to the waiting time for data writing, thereby increasing the data transmission speed of each channel.

The flash memory data reading method of the present invention is opposite to the above-mentioned flash memory data writing method.

A kind of multi-channel flash memory reading method of the present invention comprises the following steps:

1], command and address information are passed to the command parsing unit through the command interface;

2], after the command analysis unit analyzes the data and commands, the converted commands and addresses are passed to the channel arbitration and data allocation unit;

3], start the timing generation module of the corresponding channel through the channel arbitration unit;

4], read data from the flash memory chip through the common control bus and data bus in the channel corresponding to the flash memory timing generation module, and store it in the corresponding channel cache;

5], notify the channel arbitration and data allocation unit, read data from the channel buffer, and pass the data to the data interface through the data interface management unit;

6] When the data interface management unit completes the data readout to a certain channel, when there is still data to be read out, it can read data from the flash memory chip again, and perform the data readout work of the next cycle.

When reading data, the channel arbitration and data allocation unit can start multiple channels at one time for data read operation. After each channel reads data, it will be stored in the corresponding channel buffer. The channel arbitration and data allocation unit is responsible for the data. Read forward pass. After the channel cache data is read out, if the channel still has commands waiting to be read, the next read operation can be performed. Therefore, during a read operation, the unit on the right side of the channel cache is only responsible for reading data from the flash memory array and writing it into the channel cache. The units on the left side of the channel buffer work together to read data from the channel buffer and transfer it to the data interface. The two parts still work in parallel without interfering with each other.

The method for writing flash memory data of the present invention ensures that the operation timing of each chip is correct, and ensures that the waiting time for writing data into the flash memory chip operates strictly according to the maximum value of the parameters provided by the flash memory chip, thus ensuring , the data can still be reliably written into the flash memory chip. Specifically, when the previous chip is in the state of waiting for writing, it immediately transfers to the flash memory chip at the next location for writing operations, and so on, and writes the flash memory chips sequentially. When the chips in a single channel have completed a data After the write operation, the first chip in the single channel, that is, the flash memory chip that performs the data write operation for the first time, is just waiting for completion, so that the next data write can be performed. While ensuring the writing speed of data, it also ensures the writing reliability of data. Moreover, since the write waiting time of each chip is sufficiently guaranteed, the reliability of data writing is realized. And in the multi-channel flash memory that single channel is formed, every increase of a single channel described in the present invention will make the reading and writing speed of the formed multi-channel flash memory double than the original single-channel reading and writing speed, thereby greatly improving the flash memory. read and write speed.

Claims (3)

1. A multi-channel flash memory writing method is characterized in that:

comprises the following steps:

1], transmitting the command and the address information to a command analysis unit through a command interface;

2, after receiving the command, the command analysis unit starts the data interface management unit and the channel arbitration unit;

3, the channel arbitration unit pre-allocates the channel according to the address information, and meanwhile, the data interface management unit reads data from the data interface and transmits the data to the channel arbitration unit and the data allocation unit;

the data distribution unit directly writes the data into the cache of the corresponding channel according to the distributed channel number, and then the channel arbitration unit starts the corresponding flash memory time sequence generation module;

the corresponding flash memory time sequence generation module writes the data in the channel cache into the flash memory chip through the public control bus and the data bus in the channel corresponding to the flash memory time sequence generation module;

6] when the data distribution unit finishes writing data into a certain channel and still needs to write the data, the data distribution unit can read the data from the data interface again and perform data writing work of the next period;

the command analysis unit, the data interface management unit, the channel arbitration unit and the data distribution unit work cooperatively and are only responsible for moving data on the data interface to the idle channel cache; the flash memory time sequence generation module is responsible for writing data into each flash memory chip in the channel; the two parts work in parallel;

when the flash memory time sequence generation module of each channel manages the chips of the channel, after the first chip set is written, the chip of the current chip set is in a write waiting state, and the operation of the next chip is immediately switched to, and the bus is not idle because the first chip set is in the write waiting state; and by analogy, when the first chip set is returned after one cycle of the circular operation, the writing waiting time of the first chip set is just finished, and the next round of operation can be carried out.

2. A method as claimed in claim 1, wherein:

when the data in the step 5] is written into the flash memory chip, the method comprises the following steps:

501], occupying the actual writing time of the first flash memory chip in the corresponding channel, and writing data into the first flash memory chip through a control bus and a data bus;

502], continuously writing data into the next flash memory chip through the control bus and the data bus by using the writing waiting time of the current flash memory chip;

503], according to the way of the step 502], writing data into the remaining flash memory chips in the channel in sequence by using the writing waiting time of the first flash memory chip until all the flash memory chips in the channel finish the data writing work, and when the writing waiting time of the first flash memory chip is finished, the writing operation in the corresponding channel is finished for one week;

504] and returning to the step 501], writing data into the first flash memory chip again, starting new writing operation until the writing work of all data is finished, and finishing the circular writing operation.

3. A multi-channel flash memory readout method, comprising:

comprises the following steps:

1], transmitting the command and the address information to a command analysis unit through a command interface;

2, after analyzing the data and the command, the command analysis unit transmits the converted command and address to the channel arbitration unit and the data distribution unit;

3, starting a time sequence generating module of a corresponding channel through a channel arbitration unit;

reading data from the flash memory chip through a common control bus and a data bus in a channel corresponding to the flash memory time sequence generation module, and storing the data in a corresponding channel cache;

5, informing a channel arbitration unit and a data distribution unit to read data from the channel cache and transmitting the data to a data interface through a data interface management unit;

6, when the data interface management unit finishes data reading to a certain channel and still has data to be read, reading the data from the flash memory chip again and performing data reading work of the next period;

when reading data, the channel arbitration unit and the data distribution unit start a plurality of channels at a time to read the data, each channel reads the data and then stores the data in a corresponding channel cache, and the channel arbitration unit and the data distribution unit are responsible for reading the data and transmitting the data forwards; after the channel cache data is read out, if the channel has a command waiting for reading, the next reading operation can be carried out; therefore, when in read operation, the flash memory time sequence generation module is only responsible for reading data from the flash memory array and writing the data into the channel cache; the command analysis unit, the data interface management unit, the channel arbitration unit and the data distribution unit work cooperatively and are responsible for reading data from the channel cache and transmitting the data to the data interface; the two parts still work in parallel and do not interfere with each other.

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