CN101739370B - Bus system and its method of operation - Google Patents

Abstract

An operation method for a bus system used for non-sequential execution includes: linking instructions using the bus system into dependent links with a sequence according to dependent restriction conditions; and processing the instructions in sequence according to each dependent link.

Description

Bus system and its method of operation

technical field

The present invention relates to an operation method of an out-of-order bus system, and more particularly to a method for establishing a dependent link according to a dependency constraint in the out-of-order bus system.

Background technique

Traditional bus protocols are executed in an in-order manner, such as Advanced High Performance Bus (AHB, Advanced High Performance BUS), which executes sequentially according to the order of each instruction. However, such an execution method has a disadvantage, that is, when there is a large data transaction (transaction), many subsequent data transactions will be delayed, and when the system becomes larger and larger, the bus architecture for sequential execution will not be sufficient use. Therefore, the current large-scale systems turn to out-of-order bus systems, such as Advanced Extended Interface (AXI, AdvancedeXtensible Interface) and Open Core Protocol (OCP, Open Core Protocol) bus systems. These non-sequential execution bus systems can enable the master and slave devices on the bus to have more space to process instructions transmitted from the bus. In a non-sequentially executed bus system, the order of data is not in order. For example, the command transmitted through the command channel of the bus system corresponds to the transmission through the write-data channel of the bus system. The data written in this command is not sequentially entered into the slave device, therefore, thread ID (threadID) or tag ID (tagID) is often used to process these non-sequentially entered but interrelated commands. However, when these thread IDs or tag IDs are transmitted out of order on the bus, related instructions cannot be executed sequentially, and errors are likely to occur.

A related solution has been proposed in US Patent Publication No. 2007/0067549 (hereinafter referred to as Patent No. 549), which adopts the traditional first-in-first-out concept. In order to avoid possible data hazard (data hazard) between the outstanding write command and the subsequent read command, the '549 patent temporarily stores the relevant information of the outstanding write command in the first-in-first-out memory. When it is detected that there will be a data hazard in the subsequent read operation, the read operation is suspended until the unfinished write command is completed before the suspended read operation is executed to avoid data hazards. There are still some problems with this method, for example, when the read operation is suspended, all the read operations after the read operation are also suspended, even if they are executed first, data corruption will not occur. Therefore, it can be seen that if the method of the '549 patent is adopted, the overall performance of the system will be reduced.

Contents of the invention

In order to solve the above problems, the present invention proposes an operation method applied to an out-of-order bus system, so as to improve the overall performance of the system and avoid data corruption. The method includes: linking the instructions using the bus system into dependent links with a sequence according to the dependent constraints; and processing the instructions in sequence according to the dependent links.

The present invention also proposes a bus system, comprising: a command register for receiving and temporarily storing a new incoming command, wherein the new incoming command includes at least a link flag; and a dependency link generator coupled to the command register, Generate N dependent links according to the dependency constraints of the N link tags of the new instruction, and N is any positive integer; wherein, each link tag included in the new instruction is used to indicate that the new instruction is related to multiple The sequential link relationship between the previously unexecuted incoming instructions.

Description of drawings

FIG. 1 is a flowchart of an operating method of a bus system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a memory scheduler according to an embodiment of the invention.

FIG. 3 shows the structure of an instruction in a chain of dependent instructions established using a single dependency constraint.

FIG. 4 is a diagram illustrating the link relationship between instructions received by the memory scheduler at different times.

FIG. 5 shows another structure of an instruction in a chain of dependent instructions established using a single dependency constraint.

FIG. 6 shows yet another structure of an instruction in a chain of dependent instructions established using a single dependency constraint.

FIG. 7 shows the structure of each instruction in the dependent instruction chain established by using two dependent constraints.

FIG. 8 illustrates the link relationship between instructions received by the memory scheduler 200 at different times.

FIG. 9 is a schematic diagram of tracking and debugging data transmitted on the bus according to an embodiment of the present invention.

[Description of main component labels]

110, 120, 130 step 200 memory scheduler 210 instruction register 220 Dependency Link Generator 230 command selector 240 Link Relationship Remover 300, 500, 600, 700 instruction 310, 710, 720 end tag 320, 520, 620, 730 command content 330, 530, 740, 750 link tag 510 start tag 610 priority mark

Detailed ways

FIG. 1 is a flowchart of an operating method of a bus system according to an embodiment of the present invention. The method 100 for operating a bus system comprises the following steps:

Step 110: Link the multiple instructions using the bus system into at least one dependent link with sequence according to at least one dependent constraint condition;

Step 120: Process the instructions in the sequence according to each dependent link; and

Step 130: Reset the dependent link to which the executed instruction belongs according to the related link flag.

The operation method 100 of the bus system will be described in detail in conjunction with the following figures and embodiments.

FIG. 2 is a block diagram of a memory scheduler according to an embodiment of the invention. The memory scheduler 200 includes a request queue 210 , a dependency link generator 220 , a command selector 230 and a link relationship remover 240 . Wherein, the dependent link generator 220 is coupled to the command register 210, the command selector 230 is coupled to the command register 210, and the link relationship remover 240 is coupled to the command register 210 and the command selector device 230. The memory scheduler 200 is coupled to a non-sequential execution bus (not shown in FIG. 2 ), links multiple instructions using the bus system to each other into at least one dependent link with a sequence according to at least one dependency constraint, and then according to Each dependent link selects instructions that are eligible to be served, so that these instructions can be processed according to the sequence.

The instructions on the bus are transmitted non-sequentially. In order to avoid errors such as data hazards, some instructions with dependencies should be executed sequentially. Instruction thread identification code (threadID), memory page number (memory page number) and other information to judge. For example, according to the bus protocol, instructions with the same thread identification code (for example, the thread identification codes are all 0) have dependencies, and there are also dependencies between instructions that access the same memory page number. Avoid data hazards. Therefore, the dependency link can be established according to the thread identification code or the memory page number as the dependency restriction condition. Please note that the above is only used as an example, and those skilled in the art can use other dependency restriction conditions to determine the dependency between instructions. sex.

The command register 210 receives and stores the command R from the bus. FIG. 3 shows the structure of an instruction in a chain of dependent instructions established using a single dependency constraint. The command 300 stored in the command register 210 has a plurality of fields, which are respectively used to record the end mark 310, the command content 320 and the link mark 330. Please note that the order of the fields of the command 300 shown in FIG. 3 is for illustration only , should not be considered as a limitation of the present invention. The end mark 310 is used to indicate whether the instruction is the end of the dependent link, the instruction content 320 stores the content to be executed by the instruction, and the link mark 330 is used to indicate that the instruction is stored in the instruction register 210 and has not yet been executed before. The sequential link relationship among the instructions, in one embodiment, when the link mark 330 shows that the instruction 300 has no link relationship with other instructions, then the instruction 300 is the starting end of at least one dependent link.

FIG. 4 illustrates the link relationship between instructions received by the memory scheduler 200 at different times. Assume that at time T5, instructions R0(0), R1(0), and R3(0) with a thread identification code of 0 and received at times T0, T1, and T3 have been stored in the instruction register 210, and stored Instructions R2(1) and R4(1) received at time T2 and T4 with thread identification code 1 respectively, the link mark of instruction R0(0) indicates that it does not link forward to any instruction, in other words, It is the starting end of the dependent link whose thread identification code is 0 (abbreviated as the first link). The link mark of R1(0) indicates that it is linked after the instruction R0(0), and the link mark of R3(0) indicates that It is chained after instruction R1(0), and R3(0)'s end-marker indicates that it is the end of the first link; furthermore, instruction R2(1)'s link-marker indicates that it does not link forward to Any instruction, that is, it is the starting end of the dependent link (abbreviated as the second link) whose thread identification code is 1, the link mark of R4(1) is to illustrate that it is linked after the instruction R2(1), and R2( The end marker of 1) is to indicate that it is the end of the second linkage. At time T5 , the memory scheduler 200 receives the incoming instruction R5 with the thread identification code being 0, and stores it in the instruction register 210 . According to the dependent constraint condition (such as thread identification code 0, 1), the dependent link generator 220 searches for the end of the link whose thread identification code is 0, that is, instruction R3(0), so that the new incoming instruction R5 is linked to the end of the first link, Set the link label of instruction R5 to be linked to instruction R3(0) (as in step 110), and set its end label to be the end of the first link, and change the end label of instruction R3(0) so that it is no longer the first link end of a link. Please note that if the thread ID of the instruction R5 is 1, the dependent link generator 220 links it to the end of the second link in a similar manner to the above; if there is no instruction and instruction R5 in the instruction register 210 The thread identification codes of all threads are the same, that is, when the new instruction R5 does not meet any dependency restriction condition, the dependency link generator 220 sets the link tag of the instruction R5 to make it the start of the new link, and sets the end tag of the instruction R5 to make it Also becomes the end of the newly created link.

As for the execution instructions, the instruction selector 230 selects the instructions that are eligible to be executed according to the instructions stored in the instruction register 210 that have not yet been executed and the corresponding dependent links. Among them, one is selected to be executed, such as the instruction R0(0), and the instruction selector 230 outputs the instruction R0(0) qualified to be executed, which means that the instruction R0(0) has been executed (such as step 120), and the link relationship The remover 240 searches for the instruction R1(0) linked to the instruction R0(0) according to the link mark of each instruction. If the link mark of the instruction R1(0) indicates that it is linked after the instruction R(0), then the link The relationship remover 240 removes the instruction R1(0) and resets the link flag of the instruction R1(0), so that it replaces the instruction R0(0) executed by the instruction selector 230 and becomes the initial instruction of the first link (such as Step 130). When the instruction selector 230 selects the instruction to be executed again, the instruction selector 230 selects the instruction R1(0) as the instruction to be executed according to the link mark of the instruction R1(0), and outputs the instruction R1(0) for execution.

FIG. 5 shows another structure of an instruction in a chain of dependent instructions established using a single dependency constraint. The instruction 500 stored in the instruction register 210 has a plurality of fields, respectively recording the start tag 510, the instruction content 520 and the link tag 530. Please note that the order of the fields of the instruction 500 shown in FIG. 5 is for illustration only , should not be considered as a limitation of the present invention. The start mark 510 is used to indicate whether the command is the start command of a dependent link, the command content 520 stores the content to be executed by the command, and the link mark 530 is used to indicate that the command is stored in the command register 210 Linkage relationship of other instructions, for example, there are first instruction and second instruction in the bus system, and the link mark of the first instruction indicates that the first instruction is linked before the second instruction. Those skilled in the art can use instructions in the form of instruction 500 to establish dependent links and select and execute instructions under the guidance of the relevant descriptions of the above-mentioned instruction 300 for establishing dependent links and selecting and executing instructions. Therefore, for the sake of brevity, hereby No longer.

FIG. 6 shows yet another structure of an instruction in a chain of dependent instructions established using a single dependency constraint. The instruction 600 stored in the instruction register 210 has a plurality of fields, which respectively record the priority flag 610 and the instruction content 620. Please note that the order of the fields of the instruction 600 shown in FIG. Limitations of the Invention. The priority mark 610 is used to describe the sequence of the instruction in any dependent link, and the instruction content 620 is the content to be executed by the instruction. Those skilled in the art can use the instructions in the form of instruction 600 to establish dependent links and select and execute instructions under the teaching of the relevant descriptions of the above-mentioned instruction 300 for establishing dependent links and selecting and executing instructions. Therefore, for the sake of brevity, hereby Will not repeat them.

In addition to using a single dependency constraint to establish dependencies between instructions using the bus system, multiple dependency constraints can also be used to establish dependencies, for example, to establish dependencies based on thread IDs and memory page numbers. FIG. 7 shows the structure of each instruction in the dependent instruction chain established by using two dependent constraints. The instruction 700 stored in the instruction register 210 has a plurality of fields, respectively recording the first end tag 710, the second end tag 720, the instruction content 730, the first link tag 740 and the second link tag 750, please note that the The order of the fields of the instruction 700 shown in 7 is for illustration only, and should not be considered as a limitation of the present invention. The first end mark 710 is used to indicate whether the instruction is the first end instruction of the first dependent link established according to the first dependency restriction condition (such as a thread identification code), and the second end mark 720 is used to indicate whether the instruction is It is the second end instruction of the second interdependence link established according to the second interdependence restriction condition (for example, the memory page number), the instruction content 730 is to store the content to be executed by the instruction, and the first link mark 740 is used to illustrate the instruction and storage The link relationship of other instructions in the instruction register 210 in terms of the first dependency constraint, and the second link label 750 is used to illustrate the instruction and other instructions stored in the instruction register 210 in the second dependency constraint Conditional link relationship.

FIG. 8 illustrates the link relationship between instructions received by the memory scheduler 200 at different times. Assume that at time T3, the command register 210 has stored the commands R0(0)P0, R1(0)P1, and R2(1)P0 received at times T0, T1, and T2 respectively. The thread identification code of the instruction R0(0)P0, R1(0)P1 is 0, the memory page number of the instruction R0(0)P1, R2(1)P1 is 0, and the memory page number of the instruction R1(0)P1 is 1, Among them, the first link mark of instruction R0(0)P0 is to indicate that it has not previously linked any instruction whose thread identification code is 0, so it is the initial instruction of the dependent link (abbreviated as the first link) whose thread identification code is 0 , and the second link flag of instruction R0(0)P0 indicates that it is not linked to any instruction with memory page number 0 before, which is the initial instruction of the dependent link with memory page number 0 (referred to as the second link for short).

The first link label of instruction R1(0)P1 indicates that it is chained after instruction R0(0)P0 in terms of the dependency constraints of the thread ID, and the first end label of instruction R1(0)P1 indicates that it is also chained after instruction R0(0)P0. is the end instruction of the first link; and the second link tag of instruction R1(0)P1 indicates that it has not previously linked any instruction with a memory page number of 1 in terms of memory page dependency constraints, which is a memory page number of 1 The start instruction of the dependent link (referred to as the third link for short), and the second end tag of the instruction R1(0)P1 indicates that it is also the end instruction of the third link.

The first link mark of instruction R2(1)P0 is to explain that it has not linked any instruction whose thread identification code is 1 before, so it is the initial instruction of the dependent link (abbreviated as the fourth link) whose thread identification code is 1, The first end tag of instruction R2(1)P0 indicates that it is also the end instruction of the fourth chain. And the second link mark of instruction R2(1)P0 shows that it is chained after instruction R0(0)P0 in terms of the dependency constraints of the memory page number, and the second end mark of instruction R2(1)P2 shows that it is also End directive for the second link.

The first, second, third, and fourth links are the four dependent links generated by the dependent link generator 220 according to the dependent restriction conditions of the new incoming instruction link mark. Please note that the dependent link generator 220 has N links according to the new incoming instruction The dependent constraint condition of the tag generates N dependent links, and N is any positive integer, and the dependent link generator 220 has to indicate that the new instruction is the N dependent links according to the N end tags included in the new instruction. The terminal command of the command will be described in detail as a new command below.

At time T3 , the memory scheduler 200 receives the instruction R3(0)P0 whose thread ID is 0 and memory page number is 0, and stores it in the instruction register 210 . According to each dependent constraint condition (such as thread identification code 0, 1), the dependent link generator 220 searches for the end instruction of the link whose thread identification code is 0, that is, instruction R1(0)P1, so that the new incoming instruction R3(0)P0 is linked At the end of the first link, set the first link tag of instruction R3(0)P0 to be linked to instruction R1(0)P1, and set its first end tag to be the end instruction of the first link, and change instruction R1 (0) The first end of P1 marks such that it is no longer the end instruction of the first chain. According to each dependent constraint condition (such as memory page number 0, 1), the dependent link generator 220 searches for the end instruction of the link whose memory page number is 0, that is, instruction R2(1)P0, so that the new incoming instruction R3(0)P0 is linked to the first At the end of the second link, set instruction R3(0)P0 the second link label to be linked to instruction R2(1)P0, and set its second end label to be the end instruction of the second link, and change instruction R2(1) The second end mark of P2 makes it no longer the end instruction of the second chain.

Please note that if there is no instruction in the instruction register 210 that has the same thread identification code as the incoming instruction, that is, when the incoming instruction does not meet any dependency constraint condition, then the dependency link generator 220 sets the thread ID of the incoming instruction. The first link mark makes it the beginning of the new link in terms of the dependency constraints of the thread ID, and sets the first end mark of the new incoming instruction to make it the end of the new link; if the instruction register 210 If there is no instruction with the same memory page number as the new incoming instruction, the dependent link generator 220 sets the second link flag of the new incoming instruction to be the start of the new link in terms of the dependency constraint on the memory page number, and sets The second end marker of the incoming instruction makes it the end of the newly created link.

As for the execution instructions, the instruction selector 230 selects instructions that are eligible to be executed according to the instructions stored in the instruction temporary register 210 that have not yet been executed and a plurality of dependent links, and the instruction selector 230 interprets multiple (such as N) According to the N link tags contained in the dependent link, judge whether the instruction is an initial instruction according to the link tag to which it belongs, and find out the M initial instructions at the starting ends of the N dependent links, and select one of them to execute, among which Each of the M initial instructions includes at least one link flag indicating that it is an executable initial instruction, and M and N are positive integers, and M is smaller than N. For example, the link marks of the instruction R0(0)P0 in terms of the dependent constraints (thread identification code and memory page number) all indicate that it is the initial instruction, then the instruction R0(0)P0 is the instruction eligible to be executed, and Instruction R1(0)P1 is an initial instruction in terms of memory page number, but not an initial instruction in terms of thread ID, so instruction R1(0)P1 is not an instruction eligible to be executed. In another embodiment, if the link marks of the instruction R1(0)P1 in each dependency condition have a majority indicating that it is the initial instruction, then the instruction R0(0)P0 is also an instruction eligible to be executed. In yet another embodiment, the instruction R0(0)P0 is also an instruction eligible to be executed if at least one linking flag of the instruction R1(0)P1 in terms of each dependency constraint indicates that it is the initial instruction. Assume that the instruction selector 230 outputs the instruction R0(0)P0 that is qualified to be executed, and the link relationship remover 240 searches for the instruction R0(0)P0 that is linked after the instruction R0(0)P0 in terms of the dependency constraints according to each link flag of each instruction. Instructions, in terms of thread identification codes, the first link flag of instruction R1(0)P1 is to indicate that it is linked after instruction R0(0)P0, and the link relationship remover 240 resets the first link of instruction R1(0)P1. The link mark makes it replace the executed instruction R0(0)P0 as the initial instruction of the first link; in terms of memory page number, the second link mark of the instruction R2(1)P0 is to point out that it is linked in the instruction R0(0) ) P0, the link relation remover 240 resets the second link flag of the instruction R2(1)P0, so that it replaces the executed instruction R0(0)P0 as the start instruction of the second link.

In addition, instruction 700 has a form similar to instruction 500, that is, it has a plurality of start tags corresponding to a plurality of dependent constraints and a plurality of link tags corresponding to a plurality of dependent constraints, and the link tags indicate that the instruction is Those skilled in the art can easily understand how to establish dependent links and execute instructions in this form under the teachings of the above-mentioned embodiments. Therefore, for the sake of brevity, details will not be repeated here.

Furthermore, the instruction 700 has a form similar to that of the instruction 600, that is, it has a plurality of priority tags corresponding to a plurality of dependent constraints, and wherein the priority tags indicate the dependency link established by the instruction in terms of each dependent constraint According to the sequence in the above-mentioned embodiment, those skilled in the art can easily understand how to establish a dependency link and execute instructions in this form under the teaching of the above-mentioned embodiments. Therefore, for the sake of brevity, details will not be repeated here.

It is also very difficult to perform transfer alignment on a multi-threaded and non-sequentially executed bus. However, if you want to debug and trace the data transferred on the bus, you must perform transfer alignment. No. An embodiment of the present invention utilizes the technique of establishing inter-command dependencies to debug and trace the data transmitted on the bus. FIG. 9 is a schematic diagram of debugging and tracking data transmitted on the bus according to an embodiment of the present invention. As shown in the figure, the bus has a command channel (command channel) CC, a write data channel (write data channel) WC, and a response channel (response channel) DC. On the instruction channel CC, instructions R0 to R5 appear from time T0 to T5 respectively, among which the thread identification codes of instructions R0(0) and R5(0) are both 0, and instructions R1(1), R2(1), and R4 The thread identification codes of (1) are all 1, and the thread identification code of instruction R3(2) is 2. Instructions with the same thread identification code must be executed in sequence, so the thread identification code is used as a dependent constraint condition. At time T2, the debug tracking module (not shown in FIG. 9 ) finds that instruction R2(1) and instruction R1( 1) have the same thread ID, so set the link flag of instruction R2(1) in its instruction register (not shown in Figure 9) to illustrate that it is linked to instruction R1(1), set R2( 1) to indicate that it is the end instruction of a dependent link with thread ID 1 (abbreviated as the first link), and reset the end label of instruction R1(1) to indicate that it is no longer the end instruction of the first link ; At time T4, the debugging tracking module finds that the thread identification codes of instruction R4(1), instruction R1(1) and instruction R2(1) on the bus are both 1, and then make instruction R4( 1) Become the end command of the first link, and modify the link relationship of the first link.

At time T5, a piece of response data D1(1) appears in the response channel DC, its thread identification code is 1, and there are outstanding commands R1(1), R2(1), R4(1) in the bus )’s thread identification codes are all 1, and according to the above-mentioned method of using the end mark and the link mark, it can be determined that only the start command R1(1) can be executed among the three commands, so it can be determined that the command R1(1) and the response data D1(1) is the same transaction, so the data transaction of the bus can be tracked and recorded by the above method. Please note that those skilled in the art can, under the teachings of the above-mentioned embodiments, use multiple dependent constraints to debug and track the bus, or use methods such as start flags, link flags, and priority flags to trace the bus. Debugging and tracking will not be repeated here.

To sum up, the embodiments of the present invention provide a method for establishing dependencies between instructions in a non-sequentially executed multithreaded bus system by using at least one dependency constraint, so that when performing related processing on each instruction, it can be based on The dependencies among the commands are implemented to reduce the probability of data hazards.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (18)

1. A method of operating a bus system, comprising: receiving and temporarily storing a new incoming order, wherein the new incoming order includes at least a link mark; Generate N dependent links according to the dependent restriction conditions of the N link tags of the new instruction, and N is any positive integer; Find out the M initial instructions of the start ends of the N dependent links from the unexecuted new instructions, and select one of them to execute, wherein the M initial instructions all include at least one link flag to indicate the M The initial instruction is executable, and M is a positive integer less than or equal to N; and removing the executed first initial instruction, and supplementing at least one new initial instruction according to the dependent constraint condition of the first initial instruction, Wherein, each link tag included in the new instruction is used to represent the sequential link relationship between the new instruction and a plurality of previously unexecuted new instructions. 2. The method of claim 1, further comprising: linking the incoming instruction at the end of at least one dependent link according to each dependency constraint, or setting the incoming instruction as the start of a newly created link if the incoming instruction does not meet any of the dependency constraints, and the incoming instruction The incoming command is also the end of the newly created link. 3. The method according to claim 1, wherein each of the instructions includes at least one end flag, which is used to represent whether each instruction is the end of the dependent link to which it belongs. 4. The method as claimed in claim 1, wherein when the link mark shows that the first start command has no link relationship with other commands, the first start command is the start end of at least one dependent link. 5. The method according to claim 3 , wherein the first start instruction includes at least a first link flag to indicate that the first start instruction is linked before the at least one new start instruction, or that the at least one new start instruction The initial instruction includes at least a second link flag, which is used to indicate that the at least one new initial instruction is linked after the first initial instruction. 6. The method according to claim 1, wherein each of the instructions includes at least one priority flag, which is used to represent the sequence of each instruction in any dependent link to which it belongs. 7. The method according to claim 5, wherein generating N dependent links according to the dependent restriction conditions of the N link tags of the new instruction, comprising: Finding a first start instruction, wherein the first end mark included in the first start instruction indicates that the first start instruction is located at the end of the first dependent link; linking an incoming instruction corresponding to the first dependent link after the first initiating instruction; Set the tag of the incoming instruction to be the end of the first dependent link. 8. The method as claimed in claim 7, wherein the first initiating instruction is executed when the first linking flag or the second linking flag indicates that the first initiating instruction is the initiating instruction of the first dependent link. 9. The method of claim 7, further comprising: Find a start tag indicating that the first start instruction is the start instruction of the first dependent link. 10. The method according to claim 7, finding the M initial instructions of the N dependent link origins from the unexecuted new incoming instructions, and selecting one of them to execute, including: interpreting a plurality of link tokens contained in a plurality of dependent links; and judging whether the first initial instruction is executed according to the link marks; Wherein, the link flags are used to indicate whether the first initial command is the initial command of the dependent links, and the dependent links include the first dependent link. 11. The method according to claim 10, wherein if the link flags all indicate that the first initial instruction is an initial instruction of the first dependent link, then the first initial instruction is executed. 12. The method according to claim 10, wherein if a majority of the link flags indicate that the first initial instruction is an initial instruction of the first dependent link, then the first initial instruction is executed. 13. The method according to claim 1, wherein the dependency constraint condition comprises at least one of a thread ID, a memory page number, and a data failure. 14. The method according to claim 1, wherein the bus system performs at least one of memory scheduling and debugging and tracking for the instructions according to the sequence. 15. The method according to claim 1, applied to a non-sequentially executed bus system. 16. A bus system comprising: an instruction register for receiving and temporarily storing a new incoming instruction, wherein the incoming instruction at least includes a link mark; A dependent link generator, coupled to the instruction register, generates N dependent links according to the dependency constraints of the N link flags of the new instruction, and N is any positive integer; An instruction selector, coupled to the instruction register, is used to find out the M initial instructions at the start ends of the N dependent links from the unexecuted new instructions, and select one of them to execute, wherein the Each of the M initial instructions includes at least one link flag indicating that the M initial instructions are executable, and M is a positive integer less than or equal to N; and A link relationship remover, coupled to the instruction register and the instruction selector, is used to remove the first initial instruction executed by the instruction selector, and supplement at least one new start command, Wherein, each link tag included in the new instruction is used to represent the sequential link relationship between the new instruction and a plurality of previously unexecuted new instructions. 17. The bus system according to claim 16, wherein the dependent link generator further indicates that the incoming instruction is an end instruction of the N dependent links according to the N end tags included in the incoming instruction. 18. The bus system according to claim 16, being a non-sequential execution bus system.

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