CN101739235A - Processor device that seamlessly mixes 32-bit DSP and general-purpose RISC CPU - Google Patents

Abstract

The invention discloses a processor device that seamlessly mixes 32-bit DSP and general-purpose RISC CPU. Based on the same hardware platform, the processor device can not only run special 32-bit DSP instructions and SIMD instructions based on DSP processing, but also can Compatibly run general-purpose RISC CPU instructions through instruction reconstruction. In addition, a single DSP instruction supports 32-bit data operations, or two parallel 16-bit data operations. The processor adopts a 4-channel launch mechanism to increase the parallelism of the processor, thereby improving the DSP calculation efficiency of the processor and the execution control efficiency of the CPU. The processor realizes the unification and transparency of DSP processing and CPU processing, inherits the software resources and development tools carried by general-purpose RISCCPU, and the calculation function of DSP is provided through the function library, which saves the development resources of DSP processing system and is convenient for users to develop the system. develop.

Description

Processor device that seamlessly mixes 32-bit DSP and general-purpose RISC CPU

technical field

The present invention relates to the technical field of processor architecture. More specifically, the present invention is a processor device that seamlessly mixes 32-bit DSP and general-purpose RISC CPU. The processor device can run special 32-bit DSP instructions and based on SIMD instructions processed by DSP, and can be compatible with general RISC CPU instructions through instruction reconstruction.

Background technique

The traditional general-purpose reduced instruction set processor (RISC CPU) operates on registers. The advantage is that the instruction format of the RISC CPU is usually simple, the structure is regular, and the software and hardware design are relatively simple. But on the other hand, RISC CPU can only rely on load/store instructions to access storage units, the addressing mode is single, and the types of operation instructions it can support are too simple compared to DSP processors. Therefore, RISC CPU is very suitable for ordinary control applications with relatively small data volume. However, with the continuous advancement of technology, people have higher and higher requirements for processor applications. It seems that the simple structure of RISC CPU alone is not competent for digital signal processing. The single addressing mode and insufficient computing power of RISC CPU have become the bottleneck of data processing performance.

Digital Signal Processor (DSP) is designed to address the shortcomings of RISC CPUs in a large number of digital signal processing applications. It focuses on improving data processing capabilities, especially for digital signal processing such as FFT and FIR filters. ability. A general DSP processor includes an independent address generation module (DAG), which can support multiple addressing modes. Another difference between a DSP processor and a RISC CPU is that the DSP processor contains a fast multiply-accumulate module that can support a variety of arithmetic instructions. These two points make the DSP processor have a flexible mode and fast speed for data processing, but because DSP is focused on digital signal processing, its ability to control the system is often not as good as RISC CPU.

In traditional processor chip design, a simple RISC CPU processor or a DSP processor is generally selected. In order to make better use of the advantages of the two, some solutions try to combine the two. In a common fusion scheme, the RISC CPU and DSP processor are still two independent units, and the DSP is used as an acceleration device for the general-purpose processor. But this structure is simply a patchwork of two processors, the hardware overhead is the sum of the two processors, and the transmission of data and control signals between the two will be very complicated, requiring a set of peripheral circuits for processing. Makes the system not easy to use. There are also some solutions to achieve structural integration through a completely customized set of brand-new instruction sets with RISC CPU instructions and DSP instructions. Although this method can optimize all aspects of hardware, the corresponding set of new instructions The set and hardware structure, and the supporting software system also need to be redeveloped, which increases the cost of development.

Contents of the invention

(1) Technical problems to be solved

In view of this, if based on some existing RISC CPU instruction sets, without changing the instruction encoding and execution order, a pure fusion structure of RISC CPU and DSP processor on the chip architecture can be proposed, which can be generalized with RISC. The processor is used as the main control, and the user can continue to develop through the software resources and development tools carried by the RISC CPU when using it. The development of the DSP is completed in the form of a function library. When using the DSP function, it is similar to a form of subroutine call, such as FFT , FIR, some commonly used matrix processing, etc. can be made into a function library through the development of DSP instructions in advance. When the software is compiled and found to use such functions, it can be called directly. When users use the processor, it is as if they are still using an ordinary RISC CPU. In this way, the existing software resources and hardware resources can be better used to complete various processing needs, which will undoubtedly better meet people's applications.

Therefore, the present invention mainly solves the problem that RISC CPU and DSP processor structures cannot be effectively integrated in existing embedded development systems, and proposes a processor device that seamlessly mixes 32-bit DSP and general-purpose RISCCPU.

(2) Technical solution

In order to achieve the above object, the present invention provides a processor device that seamlessly mixes 32-bit DSP and general-purpose RISC CPU. The processor device consists of an instruction memory module, a data memory module, a load storage unit, a register file module, Refers to the module, instruction pre-decoding and distribution module, parallelism control module, coprocessor module, and four instruction execution channels, used to run dedicated 32-bit DSP instructions and SIMD instructions based on DSP processing, and can be reconfigured through instructions Compatible with running general-purpose RISC CPU instructions.

In the above solution, the instruction memory module is used to store instruction programs, adopts a program ROM/RAM or cache structure, and supports a multi-way group connection structure when the cache structure is adopted.

In the above scheme, the data memory module is used to store data and intermediate calculation results, and can be configured as a complete D-cache (data cache memory) structure, or as a D-cache and high-speed scratchpad memory (Scratchpad Memory) structure. ) combined structure. The high-speed temporary storage memory is used to provide high-speed data storage for the processor to use when executing DSP instructions; a part of the space in the high-speed temporary storage memory is specially used as a stack space for DSP stack to support the processing of stack instructions , the storage bit width of the stack is 256bit, and the 256bit of each row is used to store 8 32-bit general-purpose register values, which can realize the simultaneous push or pop operation of 8 register data in one clock cycle, and the 8 register data at the same time Stack the data into the stack or take out the data from the stack and store them in the corresponding registers among the 8 registers according to the requirements of the pop-out instruction.

In the above scheme, the load storage unit is mainly used for the processor to support the operation of the Load/Store instruction in the RISC CPU mode, and it is connected to the system bus and the data cache memory.

In the above scheme, the register file module is formed by adding 32 DSP-specific 32-bit registers on the basis of the existing RISC general-purpose processor register file. The 32 DSP-specific 32-bit registers are divided into 4 groups of data registers and 8 groups of Address register, data register and address register are composed of 16 32bit registers respectively.

In the above scheme, each group of data registers has the same composition type, and each group of data registers includes four 32bit registers, wherein two 32bit registers are merged to form a 64bit multiplication and accumulation register, one 32bit multiplier register M and A 32bit temporary register T, the multiplier register is used as an operand in the multiplication instruction, and the temporary register is used to save the intermediate result data.

In the above scheme, the composition type of each group of address registers is the same, and each group of address registers includes 4 16bit address registers, wherein a 16-bit address base register (ARB), a 16-bit address register (AR), and a 16-bit address register (AR). address offset register (ARO) and a 16-bit circular/global addressing address register (ARC).

In the above scheme, the register file module has the same number of visible registers and functions for the existing RISC CPU instructions, and the RISC CPU instructions apply and modify the registers visible to the CPU; the register file module is for DSP special instructions, Ability to access the entire register file and modify its values.

In the above scheme, the register file module also includes a 32-bit special-purpose control register, which is used to indicate the page address of the DSP program and data; DSP data page address and 4-bit status bits of DSP instructions; the page address in the special control register is used in the DSP jump instruction to form a global access address with the address register, and the DSP jump can only be within the page range Jump, the special control register DSP itself cannot be modified, it is set and changed by the general-purpose processor as its own coprocessor register.

In the above solution, the instruction fetch module is used to fetch instructions from the program memory, and the maximum instruction distribution parallelism that the processor can support is 4. In order to ensure the correct distribution of instructions, the instruction slot width is 16 instructions. After the instructions are distributed, the instruction fetching module takes out 8 new instructions from the program memory and puts them into the instruction slot.

In the above scheme, the pre-decoding and distribution module of the instruction is used to identify whether the instruction belongs to a RISC CPU instruction, a DSP instruction or a SIMD instruction by decoding the first 8 bits of the instruction, and distribute the instruction according to the degree of parallelism embodied in the instruction .

In the above solution, the parallelism control module is used to generate a parallelism control signal and feed it back to the distribution module according to the instruction class and corresponding bit information decoded by the pre-decoding module.

In the above scheme, the coprocessor is used to control the overall processor, and is consistent with the control of the existing RISC general-purpose processor, including various status register controls, operating modes and interrupt control; meanwhile, the coprocessor also Provide a floating point operation unit to further enhance the data processing capability of the processor.

In the above scheme, the four instruction execution channels inside the processor have the same structure, and each channel can independently complete all instructions; each channel includes an instruction decoding unit, a program flow control unit, a state control unit, an address generation unit, A state register and multiple execution units; the execution units include: a data storage control unit, an operation logic unit, a multiply-accumulate unit and a shift unit.

In the above solution, the processor device adopts a multi-stage pipeline structure, and the pipeline mainly includes fetching IA, distributing DP, decoding ID, accessing MEM, transmitting TR, executing EX and writing back WB.

In the above solution, the processor device internally provides three bypass logics for reducing data conflicts, namely: a bypass logic path from the EX level to the ID level, a bypass logic path from the TR level to the ID level, and a bypass logic path from the Bypass logic path from EX stage to TR stage.

In the above solution, the processor device further uses an internal lock mechanism to resolve pipeline or data conflicts. Once a conflict occurs, the internal lock mechanism will automatically stop the pipeline operations before the EX level.

In the above solution, the dedicated DSP instruction is used to operate on register data, or directly operate on memory data; the DSP instruction can support 32-bit data operations, or support parallel operations of two 16-bit data.

In the above scheme, in the special-purpose DSP instruction coding, the first 6 bits are instruction identifiers, and 2 bits are used to identify the degree of parallelism between it and the front and rear instructions, and the latter 24 bits are specific DSP instructions; the special-purpose DSP instructions mainly include arithmetic, multiply and accumulate , logic, shift, conditional jump and data storage instructions, and provides a variety of addressing modes and fast data stack processing.

In the above scheme, the first 8 bits of the SIMD instruction encoding are instruction identifiers, and the following 24bit encoding rules are the same as the DSP instruction rear 24bit encoding rules, and the operations are also the same; The same instruction operates, but the corresponding registers are different; SIMD instructions themselves have no parallelism, and each clock can only process one SIMD instruction.

In the above solution, the processor device adopts a 4-channel instruction parallel issuing mechanism, and supports a maximum of 4 instructions in one clock cycle.

(3) Beneficial effects

From above-mentioned technical scheme, the beneficial effect that the present invention has is:

First of all, the processor device provided by the present invention realizes the seamless mixed chain of DSP and general-purpose RISC CPU, and inherits the embedded operating system, compiler and various control protocol stacks carried by the 32-bit RISC CPU instruction set;

The second, the DSP instruction supports multiple addressing modes and data operation modes, and various algorithms based on the DSP instruction are just realized by expanding the function library and the link library of the compiler, and these function libraries can make the processor of the present invention operate in the DSP state Effectively complete the function of intensive data calculation in signal processing, so as to realize the "transparency" of user DSP calculation;

Thirdly, the 4-channel launch mechanism of the processor of the present invention increases the parallelism of program processing and greatly improves the processor's ability to process and calculate intensive data.

Description of drawings

FIG. 1 is a schematic diagram of the overall structure of a processor device provided by the present invention;

Fig. 2 is a schematic diagram of the pipeline of the processor device provided by the present invention;

Fig. 3 is a schematic diagram of the encoding structure of DSP instructions and SIMD instructions in the processor device provided by the present invention;

Fig. 4 is a schematic diagram of the allocation of 32 extended 32-bit DSP special registers in the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The invention starts from the integration of DSP and RISC CPU into one, unifies the architecture of DSP and CPU for embedded processing, and proposes a processor device with seamless mixed chain of 32-bit DSP and general RISC CPU. Based on the same hardware platform, the processor device can not only run dedicated 32-bit DSP instructions and SIMD (Single Instruction Multiple Data) instructions based on DSP processing, but also can run general-purpose RISC CPU instructions through instruction reconstruction. The architecture prototype of the processor can support the mature embedded CPU instruction set with open IP commercial authorization through instruction reconstruction, and the architecture prototype can also switch the DSP processing state through instruction reconstruction. On the other hand, a single DSP instruction can support 32-bit data operations, or two parallel 16-bit data operations. The processor adopts a 4-channel launch mechanism to increase the parallelism of the processor, thereby improving the DSP calculation efficiency of the processor and the execution control efficiency of the CPU. The processor realizes the unification and transparency of DSP processing and CPU processing, and is directly compatible with software resources and development tools carried by mature general-purpose RISC CPUs. The calculation function of DSP is provided through the function storehouse way. The processor device saves development resources of a DSP processing system and facilitates system development for users.

The hardware structure of the processor is fully integrated and can freely execute instructions in various instruction formats. There is no situation where the RISC CPU data channel and the DSP data channel have to process different instructions independently. Therefore, for some applications such as digital signal processing or matrix processing with a large amount of data, the extended DSP instructions and the provided SIMD instructions can be used to complete, thereby liberating the RISC general-purpose processor functions from heavy data processing tasks, and more Focus on control applications.

The processor's DSP instruction set not only operates on registers, but also provides instructions that directly operate on memory, which not only saves the program space occupied by instructions, but also enables the processor to process data faster. Greatly improve. On the other hand, the extended DSP instructions not only support 32-bit data operations, but also support two parallel 16-bit data operations, making the data processing forms more diverse and the scope of application wider. The DSP instructions mainly include arithmetic, multiply-accumulate, logic, shift, conditional jump and data storage instructions, and provide multiple addressing modes and fast data stack processing methods. In order to give full play to the respective advantages of DSP processor and RISC CPU, the design of DSP instructions is mainly used to meet the high-speed calculation requirements, but leave the control of the system to the RISC general processor instructions to complete, so the DSP instructions There are not too many instructions for interrupt control and other aspects designed. This also saves the number of instructions in the overall instruction set and reduces the burden on the decoding module.

The processor uses a 4-channel transmission mechanism to increase the parallelism of the processor. In the DSP instruction code, there are 2 bits in the first 8 bits to identify its parallelism with the previous and subsequent instructions, and the last 24 bits are specific DSP operation instructions. This makes it possible to identify parallelism through the parallel identification bits in the adjacent DSP instructions even if there is no information identifying the degree of parallelism in the original RISC CPU instruction, thus achieving the largest possible degree of parallelism in processor instruction distribution.

The instruction set of the processor of the present invention also supports part of the SIMD instruction, which can be regarded as a special case of the DSP instruction, and is mainly used for data operations, including ALU, MAC and load/store operations. The SIMD instruction is especially suitable for some Matrix processing and other operations. The first 8 bits of the SIMD instruction code are used as an identification to let the processor know that the instruction is a SIMD instruction. The subsequent 24-bit encoding rules are the same as the 24-bit encoding rules after the DSP instruction, and the operations are also the same. When using SIMD instructions, all four channels start to work and perform the same instruction operation, but the corresponding registers are different. SIMD instructions themselves have no parallelism and can only process 1 SIMD instruction per clock.

As shown in Figure 1, Figure 1 is a schematic diagram of the overall structure of the processor device provided by the present invention, the processor device consists of an instruction memory module, a data memory module, a load storage unit, a register file module, an instruction fetch module, an instruction predecoder and Distribution module, parallelism control module, coprocessor module, and four instruction execution channels are used to run dedicated 32-bit DSP instructions and SIMD instructions based on DSP processing, and can run general-purpose RISC CPU instructions through instruction reconstruction .

The instruction memory module is used to store instruction programs, adopts program ROM/RAM or cache structure, and supports multi-way group connection structure when adopting cache structure. The instruction memory can be a program ROM/RAM or a cache structure (I cache). The I cache adopts a multi-way group associative structure, which can be configured in different group associative forms according to the size of the Icache.

The data storage module is used to store data and intermediate calculation results, and can be configured as a complete cache structure, or as a combination of cache and scratchpad memory. The complete cache structure is mainly used to cooperate with existing RISC CPU functions to avoid problems in compatible applications. The high-speed temporary storage memory is used to provide high-speed data storage for the processor to use when executing DSP instructions; a part of the high-speed temporary storage memory is specially used as a stack space, which is used as a DSP stack to support the processing of stack instructions. The storage bit width is 256bit, and the 256bit of each row is used to store 8 32-bit general-purpose register values, which can realize the simultaneous push or pop operation of 8 register data in one clock cycle, and stack 8 register data into the stack at the same time In the stack or the data in the stack is taken out and stored in the corresponding registers in the 8 registers according to the requirements of the pop-out instruction. Such a bit-wide stack processing design can save the value in the current register with fewer clock cycles when an accident or interruption occurs in the system, which improves the system response speed.

The load storage unit is mainly used for the processor to support the operation of the Load/Store instruction in the RISC CPU mode, and it connects the system bus and the data cache memory.

The register file module is formed by adding 32 DSP-specific 32-bit registers (RD0~RD31) on the basis of the existing RISC general-purpose processor register file (R1~Rn). These registers are mainly used to store complex calculation results such as multiplication and accumulation. And memory access address, etc. The 32 DSP-specific 32bit registers are divided into 4 groups of data registers and 8 groups of address registers, and the data registers and address registers are composed of 16 32bit registers respectively. Each group of data registers has the same composition type. Each group of data registers contains 4 32bit registers, of which 2 32bit registers (ah, al) are combined to form a 64bit multiply-accumulate (ACC) register and a 32bit multiplier register. M and a 32bit temporary register T, the multiplier register is used as an operand in the multiplication instruction, and the temporary register is used to save the intermediate result data. Each group of address registers has the same composition type, and each group of address registers contains 4 16bit address registers, including a 16-bit address base (ARB) register, a 16-bit address (AR) register, and a 16-bit address offset (ARO) registers and a 16-bit cyclic/global addressing (ARC) register. Among them, the contents of ARB and AR are unsigned numbers, the contents of ARO are signed numbers, and ARC is an unsigned number. AR, ARB, ARO, and ARC can form multiple addressing modes according to different instructions. This kind of register allocation allows the four channels to use a set of registers in the process of doing calculations, so that there is no conflict in the use of registers. 32 DSP-specific 32-bit registers and execution units form a multiplication-accumulation structure for memory access, which can efficiently complete DSP calculation functions.

For RISC CPU instructions, the register file module has the same number of visible registers and functions, so RISC CPU instructions can only apply and modify its visible registers. For DSP instructions, it can access the entire register file and modify the value of the register.

In addition, the register file module also includes a 32-bit special control register (dspCtrlReg), which is used to specify the page address of the DSP program and data; this special control register is not in the general register file, and contains the 14-bit DSP program page Data page address and status bits of 4bit DSP instructions. The status bits of 4bit DSP instructions include overflow, carry, and so on. The page address in the special control register is used in the jump instruction of the DSP to form a global access address with the address register. The jump of the DSP can only jump within the page range, and the special control register DSP itself cannot be modified. It is set and changed by the general processor as its own coprocessor register. In order to avoid errors, this register should be set when the system is initialized or before using the DSP program.

The instruction fetch module is used to fetch instructions from the program memory. The maximum instruction distribution parallelism that the processor can support is 4. In order to ensure the correct distribution of instructions, the instruction slot width is 16 instructions. It means that the module fetches 8 new instructions from the program memory and puts them into the instruction slot.

The instruction pre-decoding and distribution module is used to identify whether the instruction belongs to RISC CPU instruction, DSP instruction or SIMD instruction by decoding the first 8 bits of the instruction, and distribute the instruction according to the degree of parallelism embodied in the instruction.

The parallelism control module is used to generate a parallelism control signal and feed it back to the distribution module according to the instruction class decoded by the pre-decoding module and the corresponding bit information.

The coprocessor is used to control the overall processor, and is consistent with the control of the existing RISC general-purpose processor, including various status register control, operation mode and interrupt control; at the same time, the coprocessor also provides a floating-point arithmetic unit, Further enhance the data processing capability of the processor.

The present invention uses a 4-launch structure to improve the parallelism of instruction execution. There are 4 instruction execution channels inside the processor, and the 4 channel structures are completely isomorphic. Each channel can independently complete all instructions, so the order of instruction emission Not limited by the channel number. Each execution channel mainly includes: instruction decoding unit, program flow control unit, state control unit, address generation (DAG) unit, state register and multiple execution unit units. The execution components mainly include: storage control unit, ALU (operational logic) unit, MAC (multiply and accumulate) unit and SHF (shift) unit. The instruction decoding unit decodes specific instruction types and required operands. The program flow control unit mainly deals with the program execution sequence, mainly involving jump instructions. The address generation unit is mainly used for DSP instructions to generate corresponding memory access addresses and modify addresses. The state register and the state control unit mainly record various states of the current processor, and provide required information for various judgments that need to be made during instruction execution.

The processor device adopts a multi-stage pipeline structure, and the pipeline structure can perform multi-stage pipeline processing according to application requirements. The main functions completed by the pipeline include instruction fetch (IA), distribution (DP), decoding (ID), memory access (MEM), Steps such as transfer (TR), execute (EX) and write back (WB). The general process of instruction execution is as follows: IA level fetches instructions from the instruction memory; then performs instruction pre-decoding at DP level; generates corresponding parallelism information and then distributes instructions; instructions distributed to each channel complete detailed instruction decoding at ID level ;The MEM level is used to access the data memory and complete the reading and writing of the memory data; the data read from the MEM is stored in the data temporary storage register at the TR level, and at the same time the operation of the logical units such as ALU and MAC starts at this level; Execution; the final data is written to the corresponding registers at the WB level.

A bypass logic (bypass) is provided inside the processor to reduce data conflicts. There are 3 bypass systems in the entire pipeline: a bypass path from the EX stage to the ID stage, a path from the TR stage to the ID stage, and a path from the EX stage to the ID stage. The bypass path from level to TR level. At the same time, the processor also provides an inter-lock mechanism to resolve pipeline or data conflicts. Once a conflict occurs, the inter-lock mechanism will automatically stop the pipeline operations before the EX level.

DSP instructions are used to operate on register data, or directly operate on memory data; DSP instructions can support 32-bit data operations, or support two parallel operations of 16-bit data. In the special DSP instruction coding, the first 6 bits are the instruction identification, another 2 bits are used to identify the degree of parallelism between it and the preceding and following instructions, and the last 24 bits are specific DSP instructions; the special DSP instructions mainly include arithmetic, multiply and accumulate, logic, shift, Conditional jump and data storage instructions, and provides a variety of addressing modes and fast data stack processing. The first 8 bits of the SIMD instruction code are the instruction identifier, and the following 24bit encoding rules are the same as the 24bit encoding rules of the DSP instruction, and the operations are also the same; when using the SIMD instruction, all 4 channels start working and perform the same instruction operation, but The corresponding registers are different; SIMD instructions themselves have no parallelism, and each clock can only process 1 SIMD instruction. The processor device adopts a 4-channel instruction parallel emission mechanism, and supports a maximum of 4 instructions in one clock cycle.

Referring to FIG. 1 again, FIG. 1 is a schematic diagram of the overall structure of a processor device provided by the present invention. The 4 channels share the same register file and memory space. After fetching the instruction from the I cache, the pre-decoding and distribution unit judges the instruction type and sends the instruction type to the parallel degree control module. The parallel degree control module judges the degree of parallelism according to the instruction signal, and the distribution unit performs instruction distribution. If the instruction parallelism is 1, one instruction is put into lane 1; if the instruction parallelism is 2, two instructions are put into lanes 1 and 2; if the instruction parallelism is 3, three instructions are put into lanes 1, 2, and 3. Each channel completes its own tasks according to different instructions. If there is a channel conflict and the pipeline needs to be temporarily stopped, all channels will be suspended at the same time.

Fig. 2 is a schematic diagram of the pipeline of the processor device provided by the present invention. in,

IA: Read instruction data from the I cache (read 4word instructions at a time), and send the corresponding instructions to the instruction slot;

DP: pre-decode the first 8-bit opcode of the instruction in the instruction slot, determine the type of instruction and the degree of parallelism, and then distribute the instructions in the instruction slot to each channel according to the degree of parallelism;

DC: Perform instruction decoding. If access to MEM data is required, read the address register to obtain the address of the access memory or register, as well as the corresponding read and write signals and control signals. At the same time, the address register AR also performs addressing in this level. Revise;

MEM: This clock cycle mainly reads and writes memory data according to the instruction type and address;

TR: For data transfer instructions, the write operation of the register is performed, and the data load operation of the register file is completed at this level; the data read from the memory is cached, the data in the temporary register and the data from the register file It is fed into shift and booth coded simple elements for operational simplification. Part of the ALU instruction execution of the RISC general-purpose processor;

EX: Store the intermediate results of the shift and booth encoding calculations into the intermediate result registers, and perform 64-bit addition array simplification and other ALU operations;

WB: Update related registers.

Fig. 3 is a schematic diagram of the encoding structure of DSP instructions and SIMD instructions in the processor device provided by the present invention. DSP instructions mainly include: ALU (arithmetic logic) instructions, MAC (multiply and accumulate) instructions, conditional jump instructions and data storage instructions. In the DSP extended instruction, the first 6 bits are the instruction identification code, and the next 2 bits respectively represent the parallel relationship between the instruction and its preceding and following instructions: 1 means parallel, 0 means no parallel. The last 24bit is the specific DSP instruction, aaa represents one of the 8 address register groups used in the instruction operation; iiiiiiiii in the instruction code represents the immediate value; dd represents one of the 4 data register groups used in the instruction operation; ssssss represents the shift Bit control codeword, supports up to 31 bits left and 32 bits right; m indicates whether the operation is 16bit or 32bit; xxxxxxx is the addressing mode, including register addressing and memory addressing, for memory addressing, It further supports address increment, decrement, address + offset, reversed address and linked address modes. The first 8 bits of the SIMD type instruction are used to identify the instruction type, and the coding rules of the last 24 bits are the same as the coding rules of the last 24 bits of the DSP type instructions. There is no bit indicating the degree of parallelism in the SIMD instruction encoding. For SIMD instructions, 1 instruction is issued per clock cycle, and 4 channels perform the same operation.

Fig. 4 is the allocation situation schematic diagram of 32 32bit bit wide DSP special registers of expansion among the present invention, according to the numbering of register: first 8 registers form 4 64bit multiplication and accumulation (ACC) registers, next 4 32bit multiplier registers (M) is used to store the multiplier used in the multiplication instruction, and then four 32bit temporary registers (T) can be used for data temporary storage, followed by 8 sets of address registers composed of 16 32bit registers.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (21)

1. A processor device for seamlessly mixing a 32-bit DSP with a general RISC CPU is characterized by comprising an instruction memory module, a data memory module, a loading storage unit module, a register file module, an instruction fetching module, an instruction pre-decoding and distributing module, a parallelism control module, a coprocessor module and 4 instruction execution channels, wherein the instruction execution channels are used for running special 32-bit DSP instructions and SIMD instructions based on DSP processing, and can run general RISC CPU instructions in a compatible mode through instruction reconstruction.

2. The processor apparatus of claim 1, wherein the instruction memory module is configured to store an instruction program, to use a program ROM/RAM or cache architecture, and to support a multi-way set associative architecture when using a cache architecture.

3. The processor apparatus of claim 1, wherein the data memory module is configured to store data and intermediate computation results, and can be configured as a full data cache D-cache architecture, or as a combination of D-cache and scratch pad architecture.

4. The processor apparatus for seamlessly chaining a 32-bit DSP and a general purpose RISC CPU as claimed in claim 3, wherein said scratch pad memory is used to provide high speed data storage for use by the processor in executing DSP instructions; a part of space in the high-speed temporary storage memory is specially used as stack space and used for processing DSP stacks to support stack instructions, the storage bit width of the stacks is 256 bits, the 256 bits of each line are used for storing 8 32-bit general register values, the simultaneous stacking or unstacking operation of 8 register data can be realized in one clock cycle, and the 8 register data are simultaneously stacked or the stack data are taken out and stored into corresponding registers in 8 registers according to the requirement of the unstacking instruction.

5. The processor device according to claim 1, wherein said register file module is formed by adding 32 DSP-specific 32-bit registers based on the existing RISC general-purpose processor register file, said 32 DSP-specific 32-bit registers are divided into 4 sets of data registers and 8 sets of address registers, and said data registers and said address registers are respectively formed by 16 32-bit registers.

6. The processor apparatus of claim 5, wherein each set of data registers is of the same type and comprises 4 32-bit registers, wherein 2 32-bit registers are combined to form a 64-bit multiply-accumulate register, a 1-32-bit multiplier register M and a 1-32-bit scratch register T, the multiplier register is used as an operand in a multiply instruction, and the scratch register is used to store intermediate result data.

7. The processor device according to claim 5, wherein each set of address registers is of the same type, each set of address registers comprising 4 16-bit address registers, a 16-bit address base register, a 16-bit address offset register and a 16-bit coefficient address register.

8. The processor apparatus of claim 5, wherein the register file module is configured to seamlessly blend a 32-bit DSP with a general purpose RISC CPU, wherein the number and functions of visible registers of the register file module are unchanged for existing RISC CPU instructions, which apply and modify CPU-visible registers; the register file module can access the whole register file and modify the value of the whole register file for DSP special instructions.

9. The processor apparatus for seamlessly chaining a 32-bit DSP and a general purpose RISC CPU as claimed in claim 5, wherein said register file module further comprises a 32-bit dedicated control register for designating page addresses of DSP programs and data; the special control register is not in the general register file and comprises a 14-bit DSP program page address, a 14-bit DSP data page address and a 4-bit DSP instruction status bit; the page address in the special control register is used in a jump instruction of the DSP and is used for forming a global access address with the address register, the jump of the DSP can only be carried out in a page range, the DSP cannot be modified, and the special control register is used as a coprocessor register of the DSP to be set and changed by a general processor.

10. The processor apparatus according to claim 1, wherein said instruction fetch module is configured to fetch instructions from a program memory, the maximum instruction dispatch parallelism supportable by the processor is 4, the instruction slot width is 16 instructions to ensure correct instruction dispatch, and the instruction fetch module fetches a new 8 instructions from the program memory into the instruction slot each time 8 instructions are dispatched.

11. The processor apparatus according to claim 1, wherein said instruction predecoding and dispatch module is configured to identify whether an instruction belongs to RISC CPU instructions, DSP instructions, or SIMD instructions by decoding the first 8 bits of the instruction, and dispatch the instruction according to the parallelism embodied in the instruction.

12. The processor apparatus according to claim 1, wherein said parallelism control module is configured to generate parallelism control signals for feedback to the distributing module according to the instruction class decoded by the pre-decoding module and the corresponding bit information.

13. The processor apparatus of claim 1, wherein said coprocessor is used to control the entire processor and keep the same with the existing RISC general purpose processor, including various status register control, run mode and interrupt control; meanwhile, a floating point arithmetic unit is also provided in the coprocessor, so that the data processing capability of the processor is further enhanced.

14. The processor apparatus for seamless chaining a 32-bit DSP and a general-purpose RISC CPU according to claim 1, wherein 4 instruction execution channels within said processor are identical in structure, each channel being capable of independently completing all instructions; each channel comprises an instruction decoding unit, a program flow control unit, a state control unit, an address generation unit, a state register and a plurality of execution units; the execution component comprises: the device comprises a data storage control unit, an arithmetic logic unit, a multiply-accumulate unit and a shift unit.

15. The processor apparatus of claim 1, wherein the processor apparatus employs a multi-stage pipeline architecture, the pipeline mainly comprising instruction IA, dispatch DP, decode ID, access MEM, transfer TR, execute EX, and write-back WB.

16. The processor device for seamlessly chaining a 32-bit DSP and a general purpose RISC CPU as claimed in claim 15, wherein said processor device provides 3 bypass logics internally for reducing data collision, respectively: a bypass logic path from the EX stage to the ID stage, a bypass logic path from the TR stage to the ID stage, and a bypass logic path from the EX stage to the TR stage.

17. The processor device for seamlessly chaining a 32-bit DSP and a general purpose RISC CPU as recited in claim 16, wherein said processor device further employs an interlock mechanism to resolve pipeline or data conflicts, wherein said interlock mechanism automatically stalls the pipeline prior to the EX stage once a conflict occurs.

18. The processor apparatus for seamlessly chaining a 32-bit DSP and a general purpose RISC CPU as claimed in claim 1, wherein said dedicated DSP instruction is used to operate either register-oriented data or directly memory-oriented data; the DSP instructions can support 32-bit data operations or 2 parallel operations of 16-bit data.

19. The processor device for seamlessly mixing a 32-bit DSP and a general RISC CPU according to claim 1, wherein in the special DSP instruction coding, the first 6 bits are instruction marks, the other 2 bits are used for marking the parallelism between the special DSP instruction coding and the front and back instructions, and the last 24 bits are specific DSP instructions; the special DSP instruction mainly comprises arithmetic, multiply-accumulate, logic, shift, conditional jump and data storage instructions, and provides various addressing modes and rapid data stack processing.

20. The processor device for seamlessly blending a 32-bit DSP and a general RISC CPU according to claim 1, wherein the first 8 bits of the SIMD instruction encoding is an instruction identifier, the later 24-bit encoding rule is the same as the later 24-bit encoding rule of the DSP instruction, and the operation is the same; when the SIMD instruction is used, 4 channels start working and perform the same instruction operation, but the corresponding registers are different; the SIMD instructions themselves have no parallelism and can only process 1 SIMD instruction per clock.

21. The processor device of claim 1, wherein the processor device employs a 4-channel instruction parallel issue mechanism, supporting 4 instructions issue in a maximum of one clock cycle.

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