CN101738793A - Liquid crystal display panel capable of compensating common voltage and liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a liquid crystal display capable of compensating a common voltage. The liquid crystal display panel comprises a first substrate, a second substrate and a liquid crystal layer. The first substrate comprises a substrate, a common electrode wiring layer, a first insulating layer, a semiconductor layer, a second insulating layer, a data line and a conductive layer. The common electrode wiring layer is formed on the substrate. The first insulating layer is formed on the common electrode wiring layer. The semiconductor layer is formed on the first insulating layer. The second insulating layer is formed on the semiconductor layer, and the second insulating layer has an opening. The data line is formed on the second insulating layer. The conductive layer is formed on the opening and a part of the second insulating layer, and the conductive layer is electrically isolated from the data line. The second substrate is arranged in parallel with the first substrate. The liquid crystal layer is sandwiched between the first substrate and the second substrate.

Description

Liquid crystal display panel and liquid crystal display capable of compensating common voltage

technical field

The invention relates to a liquid crystal display panel and a liquid crystal display, and in particular to a liquid crystal display panel and a liquid crystal display capable of compensating common voltage.

Background technique

In the driving process of the liquid crystal display panel, according to the potential of the common voltage, the appropriate pixel voltage is provided through the data driving circuit to make the pixel display the corresponding gray scale, and the storage capacitor is also used to store the voltage provided by the data line for driving. The pixel voltage of the pixel. A common storage capacitor structure is to arrange a common electrode wiring layer on the lower substrate of the liquid crystal display panel, so as to form a storage capacitor between it and the pixel electrodes.

Referring to FIG. 1A , it shows an equivalent circuit diagram of a pixel of a conventional liquid crystal display panel. In the layout of the liquid crystal display panel, the data line D overlaps with the common electrode wiring layer Ld formed on the lower substrate, so a parasitic capacitance Cxd will be generated between the two, and the data line D also overlaps with the common electrode wiring layer Ld formed on the upper substrate. The electrode layer Lu overlaps, so a parasitic capacitance Cxu will be generated. Since the pixel voltage transmitted by the data line D will change continuously during each scan line selection time, the common voltage Vcomu of the upper substrate and the common voltage Vcomd of the lower substrate are affected by the parasitic capacitance Cxu and Cxd respectively. Due to the influence of the coupling effect, there are continuous changes.

The above-mentioned problems can be alleviated by sequentially transmitting a plurality of pixel voltages of alternating positive and negative AC signals with respect to a common voltage by the data driving circuit. However, in some cases, for example, when the image to be presented is a checkerboard image, the data driving circuit may only drive odd or even data lines. In this way, the single-polarity pixel voltage coupling will cause the common voltage Vcomu and Vcomd of the upper substrate and the lower substrate to be unbalanced and produce obvious changes, resulting in the common voltage of the storage capacitor Cst and the liquid crystal capacitor Clc being unable to be selected in time on the scanning line. Return to the preset voltage level within a certain period of time, so that the LCD monitor cannot display the correct picture.

Referring to FIG. 1B , it is an equivalent circuit diagram of a pixel of a conventional liquid crystal display panel capable of compensating a common voltage. In order to solve the above problems, the known technology is to form an indium tin oxide (Indium Tin Oxide, ITO) layer between the data line D and the common electrode layer Lu of the upper substrate, and apply a common voltage thereon, so that the common voltage of the upper substrate Vcomu is less susceptible to the pixel voltage on the data line D. However, in the above architecture, due to the short distance between the ITO layer and the data line D, a large parasitic capacitance will be generated, which will increase the load on the data driving circuit, which not only consumes more power, but also is far away from the data driving circuit. The storage capacitor of the pixel on the side will be insufficiently charged, so that the liquid crystal display cannot display a correct picture.

Contents of the invention

The invention relates to a liquid crystal display panel and a liquid crystal display, which can compensate the common voltage of the panel to stabilize the level of the common voltage without causing the overload of the data driving circuit to make the liquid crystal display display correct images.

According to a first aspect of the present invention, a liquid crystal display panel is provided, including a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a substrate, a common electrode wiring layer, a first insulating layer, a semiconductor layer, a second insulating layer, data lines and a conductive layer. A common electrode wiring layer is formed on the substrate. The first insulating layer is formed on the common electrode wiring layer. A semiconductor layer is formed on the first insulating layer. A second insulating layer is formed on the semiconductor layer, and the second insulating layer has an opening. The data lines are formed on the second insulating layer. The conductive layer is formed on the opening and part of the second insulating layer, and the conductive layer is electrically isolated from the data line. The second substrate is arranged parallel to the first substrate. The liquid crystal layer is sandwiched between the first substrate and the second substrate.

According to a second aspect of the present invention, a liquid crystal display is provided, including a liquid crystal display panel and a backlight module. The liquid crystal display panel includes a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a substrate, a common electrode wiring layer, a first insulating layer, a semiconductor layer, a second insulating layer, data lines and a conductive layer. A common electrode wiring layer is formed on the substrate. The first insulating layer is formed on the common electrode wiring layer. A semiconductor layer is formed on the first insulating layer. A second insulating layer is formed on the semiconductor layer, and the second insulating layer has an opening. The data lines are formed on the second insulating layer. The conductive layer is formed on the opening and part of the second insulating layer, and the conductive layer is electrically isolated from the data line. The second substrate is arranged parallel to the first substrate. The liquid crystal layer is sandwiched between the first substrate and the second substrate. The backlight module is coupled to the liquid crystal display panel.

In order to make the above content of the present invention more obvious and easy to understand, the preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows

Description of drawings

FIG. 1A is an equivalent circuit diagram of a pixel of a conventional liquid crystal display panel;

FIG. 1B is an equivalent circuit diagram of a pixel of a conventional liquid crystal display panel capable of compensating a common voltage;

FIG. 2A is a cross-sectional view of part of the structure of a liquid crystal display panel according to the first embodiment of the present invention;

FIG. 2B is an equivalent circuit diagram of a pixel of the liquid crystal display panel of FIG. 2A;

FIGS. 3A to 3C show the electric effect circuits of the two pixels in FIG. 1A, FIG. 1B and FIG. 2B respectively;

FIGS. 4A to 4C are simulation waveform diagrams of common voltages according to the equivalent circuits of FIGS. 3A to 3C respectively;

FIG. 5 is a wiring diagram showing a partial structure of a liquid crystal display panel according to a first embodiment of the present invention;

FIG. 6 is a cross-sectional view of part of the structure of a liquid crystal display panel according to a second embodiment of the present invention;

FIG. 7 is an equivalent circuit diagram of a pixel of the liquid crystal display panel of FIG. 6;

FIG. 8 is a schematic diagram of a liquid crystal display using a liquid crystal display panel according to an embodiment of the present invention.

[Description of main component symbols]

100: LCD display panel

101: Substrate

102: common electrode wiring layer

103: first insulating layer

104: semiconductor layer

104a: Amorphous silicon layer

104b: doped layer

105: Second insulating layer

106, D1, D2: data lines

107: Conductive layer

107a: Indium tin oxide layer

108: pixel electrode layer

109: The third insulating layer

110: first substrate

120: second substrate

121: common electrode layer

800: liquid crystal display

820: Liquid crystal display panel

840: backlight module

Clc: liquid crystal capacitance

Cst, Cst1, Cst2: storage capacitor

Cp1, Cp2: equivalent capacitance

Cxd, Cxd1, Cxd1a, Cxd1b, Cxda, Cxdb, Cxu, Cxu1, Cxu2, Cxu2a, Cxu2b: parasitic capacitance

O: open

R1, R2: Region

Sn: scan line

t1, t2: time

TFT: thin film transistor

Vcomu: common voltage of the upper substrate

Vcomd: lower substrate common voltage

V1, Va, Vb, Vc: voltage levels

Vs: constant voltage source

Detailed ways

first embodiment

Referring to FIG. 2A , it is a cross-sectional view of a partial structure of a liquid crystal display panel according to a first embodiment of the present invention. The liquid crystal display panel 100 includes a first substrate 110 , a second substrate 120 and a liquid crystal layer 130 . The first substrate 110 is, for example, a lower substrate. The second substrate 120 is, for example, an upper substrate, which is arranged parallel to the first substrate 110 . The liquid crystal layer 130 is interposed between the first substrate 110 and the second substrate 120 .

The first substrate 110 includes a substrate 101 , a common electrode wiring layer 102 , a first insulating layer 103 , a semiconductor layer 104 , a second insulating layer 105 , a data line 106 and a conductive layer 107 . The common electrode wiring layer 102 is formed on the substrate 101 . The first insulating layer 103 is formed on the common electrode wiring layer 102 . The semiconductor layer 104 is formed on the first insulating layer 103 . The second insulating layer 105 is formed on the semiconductor layer 104 , and the second insulating layer 105 has an opening O. As shown in FIG. The data line 106 is formed on the second insulating layer 105 . The conductive layer 107 is formed on the opening O and part of the second insulating layer 105 , and the conductive layer 107 is electrically isolated from the data line 106 . Wherein, the first insulating layer 103 and the second insulating layer 105 are, for example, silicon nitride (SiNx) layers, but they are not limited thereto.

The semiconductor layer 104 includes, for example, an amorphous silicon layer 104a and a doped layer 104b. Wherein, the amorphous silicon layer 104 a is formed on the first insulating layer 103 . The doped layer 104b is formed on the amorphous silicon layer 104a and is in contact with the conductive layer 107 . The common electrode wiring layer 102 is applied with a common voltage, and the conductive layer 107 is also applied with the common voltage. The common voltage is, for example, the lower substrate common voltage Vcomd. The conductive layer 107 is preferably an indium tin oxide (Indium Tin Oxide, ITO) layer. Since the conductive layer 107 is in contact with the doped layer 104b of the semiconductor layer 104 at the opening O, the semiconductor layer 104 also has the lower substrate common voltage Vcomd. In addition, the second substrate 120 includes a common electrode layer 121 , and the common electrode layer 121 is also applied with another common voltage, such as a substrate common voltage Vcomu.

Referring to FIG. 2A and FIG. 2B at the same time, FIG. 2B is an equivalent circuit diagram of a pixel of the liquid crystal display panel 100 shown in FIG. 2A . In FIG. 2B , the data line 106 is coupled to the liquid crystal capacitor Clc and the storage capacitor Cst via, for example, a thin film transistor (Thin Film Transistor) TFT. The liquid crystal capacitor Clc and the storage capacitor Cst are also respectively coupled to the common voltages Vcomu and Vcomd of the upper substrate and the lower substrate. Referring to FIG. 2A and FIG. 2B , a parasitic capacitance Cxu is formed between the data line 106 and the common electrode layer 121 . A parasitic capacitance Cxd is also formed between the data line 106 and the common electrode wiring layer 102 .

In addition, a parasitic capacitance Cxda is formed between the data line 106 and the semiconductor layer 104 , and another parasitic capacitance Cxdb is formed between the semiconductor layer 104 and the common electrode wiring layer 102 . In this way, since the semiconductor layer 104 is formed between the data line 106 and the common electrode wiring layer 102, the parasitic capacitance Cxd originally expressed as between the data line 106 and the common electrode wiring layer 102 can be regarded as two parasitic capacitors. The series connection of capacitance Cxda and Cxdb. Also, the lower substrate common voltage Vcomd applied to the conductive layer 107 can be regarded as the constant voltage source Vs in FIG. 2 , and the voltage level of the constant voltage source Vs is Vcomd.

Continuing to refer to FIG. 2B , the liquid crystal display panel 100 is applied to a liquid crystal display. The liquid crystal display includes, for example, a data driving circuit (not shown) for transmitting pixel voltages to the data lines 106 . When the polarity of the pixel voltage transmitted by the data line 106 changes, the common voltages Vcomu and Vcomd of the upper substrate and the lower substrate are respectively affected by the pixel voltage transmitted by the data line 106 through the parasitic capacitances Cxu and Cxd, so that the voltage level thereof is changed. pulled high or low. In this embodiment, when the common voltage Vcomd of the lower substrate is affected by the pixel voltage of the data line 106 and fluctuates, the parasitic capacitance Cxdb between the semiconductor layer 104 and the common electrode wiring layer 102 and the constant voltage source Vs can be used to compensate the lower voltage. The common voltage Vcomd of the substrate, so that the common voltage Vcomd of the lower substrate fluctuated by the influence of the pixel voltage can return to the preset voltage level within the scanning line selection time in time.

The equivalent circuits and simulation results of the conventional liquid crystal display panel and the liquid crystal display panel of this embodiment when compensating for the common voltage will be described below. Referring to FIG. 3A to FIG. 3C , they are shown as equivalent circuit diagrams of two pixels according to FIG. 1A , FIG. 1B and FIG. 2B respectively. The data lines D1 and D2 in FIG. 3C are two data lines in two pixels of the data line 106 in the pixel shown in FIG. 2B . In FIGS. 3A to 3C, the data line D1 is driven by the power supply with the maximum driving capability of the data driving circuit, and the data line D2 is not driven, so the data line D2 will not affect the common voltage Vcomu and Vcomd of the upper substrate and the lower substrate. voltage level.

Referring to FIG. 4A to FIG. 4C , they are simulation waveform diagrams of common voltages according to the equivalent circuits of FIG. 3A to FIG. 3C respectively. Taking FIG. 4A as an example, the description is as follows. FIG. 4A is shown as an example of the following substrate common voltage Vcomd. At time t1, the data line D1 changes from a preset voltage level to the highest driving voltage, for example, 6V to 12V, while the voltage of the data line D2 remains unchanged, for example, remains at 6V. At this moment, the lower substrate common voltage Vcomd is pulled up to the voltage level V1 by the influence of the data line D1. After time t1, the common voltage Vcomd of the lower substrate is no longer affected by the data line D1, and gradually recovers to the preset common voltage level (6 volts). At time t2, the data line D1 changes to another voltage, such as the lowest driving voltage of 0 volts. At this time, the lower substrate common voltage Vcomd has not returned to the preset voltage level (6 volts), and drifts to the voltage level Va. Similarly, it can be seen that the common voltage Vcomu of the upper substrate will also be affected and its voltage level will drift.

Detailed simulation results are provided below. In FIG. 4A , the simulation result of the common voltage Vcomd of the lower substrate is the voltage level Va, that is, 6.29 volts, so the common voltage Vcomd of the lower substrate cannot return to the preset voltage level in time within the scan line selection time. In FIG. 4B , the simulation result of the upper substrate common voltage Vcomd compensated by the traditional method is the voltage level Vb, that is, 6.07 volts. Therefore, it is known that the upper substrate common voltage Vcomd still cannot return to the preset voltage level within the scanning line selection time. flat. In FIG. 4C , using the liquid crystal display panel of the embodiment of the present invention, the simulation result of the compensated lower substrate common voltage Vcomd is the voltage level Vc, that is, 5.99 volts. It can be seen that, in the liquid crystal display panel proposed in this embodiment, the lower substrate common voltage Vcomd can return to the preset voltage level within the scanning line selection time.

In addition, the liquid crystal display panel of this embodiment also has the advantage of high aperture ratio. Referring to FIG. 5 , it shows a wiring diagram of a partial structure of a liquid crystal display panel according to a first embodiment of the present invention. In FIG. 5, the conductive layer 107 is preferably an indium tin oxide (Indium Tin Oxide, ITO) layer 107a. The transparent ITO layer 107a is applied with a constant voltage source Vs, the voltage level of the constant voltage source Vs is the lower substrate common voltage Vcomd, and the voltage level of the constant voltage source Vs is transmitted to the data line 106 and the The semiconductor layer 104 between the common electrode wiring layers 102 is used to compensate the lower substrate common voltage Vcomd. The transparent ITO layer 107a can allow light from the backlight module (not shown in FIG. 5 ) to pass through, so the aperture ratio will not be reduced.

And generally speaking, a storage capacitor Cst is formed between the common electrode wiring layer 102 and the pixel electrode layer 108 . In the above embodiment, the common electrode wiring layer 102 can also be formed under the ITO layer 107a to form another storage capacitor Cst', as shown in FIG. 5 . Therefore, compared with the traditional liquid crystal display panel, since the liquid crystal display panel of the embodiment of the present invention has an additional storage capacitor Cst', the area of the storage capacitor Cst can be reduced, and the common electrode wiring layer 102 passes through the pixel electrode 108 The wiring width can be reduced, which further improves the aperture ratio.

In addition, the liquid crystal display panel of the embodiment of the present invention can reduce the load of the data driving circuit, which is described below. Continuing to refer to FIG. 5, the parasitic capacitance Cxu of FIG. 2B is located at the intersection of the data line 106 and the common electrode layer 121 of the second substrate, that is, located in the region R1, and the parasitic capacitance Cxd is located at the intersection of the data line 106 and the common electrode layer 121 of the first substrate. The overlap of the wire layers 102 is located in the region R2. According to the capacitance calculation formula C=εA/d, since the area of the region R2 is smaller than the area of the region R1, it can be deduced that the parasitic capacitance Cxd is smaller than the parasitic capacitance Cxu.

Therefore, in the traditional method of compensating the voltage, another ITO layer is formed between the data line and the common electrode layer of the second substrate, which will increase the parasitic capacitance therebetween and cause an overload of the data driving circuit. However, in the embodiment of the present invention, a current path is provided between the smaller parasitic capacitors Cxd to compensate for the common voltage, so the data driving circuit will not be overloaded.

second embodiment

Referring to FIG. 6 , it is a cross-sectional view of a partial structure of a liquid crystal display panel according to a second embodiment of the present invention. Different from the first embodiment, the first substrate 110 further includes a third insulating layer 109 . The third insulating layer 109 is formed on the data line 106 and covers the data line 106 . The conductive layer 107 also extends to the third insulating layer 109 to partially overlap with the data line 106 . In this way, a parasitic capacitance Cxua is formed between the conductive layer 107 and the data line 106 , and a parasitic capacitance Cxub is formed between the conductive layer 107 and the common electrode layer 121 . In this embodiment, an equivalent circuit diagram of a pixel of the liquid crystal display panel 600 is shown in FIG. 7 .

In FIG. 7, when the common voltage Vcomu of the upper substrate of the second substrate 120 is affected by the pixel voltage of the data line 106 and fluctuates, the parasitic capacitance Cxub between the conductive layer 107 and the common electrode layer 121 and the constant voltage source Vs can be used. The common voltage Vcomu of the upper substrate is compensated so that the common voltage Vcomu of the upper substrate changed by the influence of the pixel voltage can return to the preset voltage level in time within the scan line selection time. Therefore, in this embodiment, not only has the advantage of compensating the common voltage Vcomd of the lower substrate as in the first embodiment, but also compensates the common voltage Vcomu of the upper substrate, so that both the common voltage Vcomu and Vcomd can return to the preset voltage level in real time. flat.

In addition, the liquid crystal display panel provided by the above-mentioned embodiments of the present invention can be applied to a liquid crystal display. Referring to FIG. 8 , it is a schematic diagram of a liquid crystal display using a liquid crystal display panel according to an embodiment of the present invention. The liquid crystal display 800 includes a liquid crystal display panel 820 and a backlight module 840 . The liquid crystal display panel 820 has, for example, the structure of the liquid crystal display panel disclosed in the above embodiments (such as the liquid crystal display panel 100 in FIG. 2A or the liquid crystal display panel 600 in FIG. 6 ). The backlight module 840 is coupled to the liquid crystal display panel 820 for providing the light source LS required by the liquid crystal display panel 820 for displaying images. Since the liquid crystal display panel 820 can stabilize the common voltage of the upper substrate and the lower substrate by compensating the common voltage of the upper substrate and the lower substrate, therefore, the liquid crystal display 800 can be correctly regulated under the operation of the liquid crystal display panel with a stable common voltage. The light source LS provided by the backlight module 840 can display a correct picture.

In the liquid crystal display panel and the liquid crystal display disclosed in the above-mentioned embodiments of the present invention, the common voltage of the common electrode wiring layer is compensated by forming a semiconductor layer between the common electrode wiring layer and the data line of the first substrate, so that the lower substrate The common voltage can return to the normal level within the scanning line selection time in time, so the liquid crystal display can display the correct picture, and the load on the data driving circuit will not be seriously increased. The storage capacitor will not have the problem of insufficient charging. In addition, the aperture ratio is maintained by using a transparent ITO layer as the conductive layer. Furthermore, in another embodiment, a conductive layer is also disposed on the data line to compensate the common voltage of the upper substrate to return to a normal level, thereby simultaneously stabilizing the common voltage of the upper substrate and the lower substrate.

In summary, although the present invention has been disclosed as above with preferred embodiments, they are not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various modifications and variations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.

Claims (12)

1. A liquid crystal display panel, comprising: A first substrate comprising: Substrate; a common electrode wiring layer formed on the substrate; a first insulating layer formed on the common electrode wiring layer; a semiconductor layer formed on the first insulating layer; a second insulating layer formed on the semiconductor layer, the second insulating layer having an opening; a data line formed on the second insulating layer; and a conductive layer formed on the opening and part of the second insulating layer, and the conductive layer is electrically isolated from the data line; a second substrate arranged parallel to the first substrate; and a liquid crystal layer sandwiched between the first substrate and the second substrate; Wherein, a common voltage is applied to the common electrode wiring layer and the conductive layer. 2. The liquid crystal display panel according to claim 1, wherein the first substrate further comprises a third insulating layer, the third insulating layer is formed on the data line and covers the data line, and the conductive layer It also extends to the third insulating layer to partially overlap with the data line. 3. The liquid crystal display panel according to claim 1, wherein the semiconductor layer comprises: an amorphous silicon layer formed on the first insulating layer; and A doped layer is formed on the amorphous silicon layer and is in contact with the conductive layer. 4. The liquid crystal display panel according to claim 1, wherein the conductive layer is an indium tin oxide (Indium Tin Oxide, ITO) layer. 5. The liquid crystal display panel according to claim 1, wherein the first insulating layer and the second insulating layer are silicon nitride layers. 6. The liquid crystal display panel according to claim 1, wherein the second substrate comprises a common electrode layer to which another common voltage is applied. 7. A liquid crystal display, comprising: Liquid crystal display panel, including: A first substrate comprising: Substrate; a common electrode wiring layer formed on the substrate; a first insulating layer formed on the common electrode wiring layer; a semiconductor layer formed on the first insulating layer; a second insulating layer formed on the semiconductor layer, the second insulating layer having an opening; a data line formed on the second insulating layer; and a conductive layer formed on the opening and part of the second insulating layer, and the conductive layer is electrically isolated from the data line; a second substrate arranged parallel to the first substrate; and a liquid crystal layer sandwiched between the first substrate and the second substrate; and a backlight module coupled to the liquid crystal display panel; Wherein, a common voltage is applied to the common electrode wiring layer and the conductive layer. 8. The liquid crystal display according to claim 7, wherein the first substrate further comprises a third insulating layer, the third insulating layer is formed on the data line and covers the data line, and the conductive layer also extending to the third insulating layer to partially overlap with the data line. 9. The liquid crystal display according to claim 7, wherein the semiconductor layer comprises: an amorphous silicon layer formed on the first insulating layer; and A doped layer is formed on the amorphous silicon layer and is in contact with the conductive layer. 10. The liquid crystal display according to claim 7, wherein the conductive layer is an ITO layer. 11. The liquid crystal display according to claim 7, wherein the first insulating layer and the second insulating layer are silicon nitride layers. 12. The liquid crystal display of claim 7, wherein the second substrate includes a common electrode layer to which another common voltage is applied.

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