CN101730932B - Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel - Google Patents

Abstract

A semiconductor die substrate panel is disclosed that includes a minimum kerf width between adjacent semiconductor package outlines on the panel while ensuring electrical isolation of plated electrical terminals. By reducing the width of the border between adjacent package outlines, additional space is obtained on the substrate panel for the semiconductor package.

Description

Double-sided substrate pin connection for minimizing kerf width on semiconductor substrate panels

technical field

Embodiments of the present invention relate to semiconductor die substrate panels that include a minimum kerf width between adjacent semiconductor package outlines on the panel while ensuring electrical isolation of plated contacts.

Background technique

The strong growth in demand for portable consumer electronics drives the demand for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory memory cards, are becoming more widely used to meet the growing demand for digital information storage and exchange. Their portability, versatility, and stable design, as well as their high reliability and large capacity, have made such memory devices ideal for use in many kinds of electronic devices, including, for example, digital cameras, digital music players, Video game consoles, PDAs and cellular phones.

Although many kinds of packaging configurations are known, flash memory cards are typically manufactured as a system-in-package (SiP) or a multi-chip module (MCM), where multiple die are mounted on a substrate. The substrate may typically comprise a rigid dielectric base with a conductive pattern (often copper or copper alloy) etched on each side. An electrical connection is formed between the die and the conductive pattern, and the conductive pattern provides an electrical lead structure for connection between the die and an external electronic system. Once the electrical connections between the die and substrate are made, the assembly is typically encapsulated in a mold to form a protected semiconductor package.

While copper conductive patterns can be etched with high precision, the poor aggressiveness of copper makes it undesirable for certain applications. In the presence of moisture, air, and chlorine, exposed copper is prone to rust, making it unusable for subsequent soldering and die attach operations. Similarly, certain packages, such as Land Grid Array (LGA) and Ball Grid Array (LGA) packages, include contact fingers formed on the lower surface of the package and exposed outside the package. To establish an electrical connection between the package and the external electronic device. If the contact fingers are formed of bare copper, rust and corrosion can damage the fingers over time.

Thus, it is known to plate copper pins at their solder or via points, as well as at contact fingers. Various plating processes are known for applying thin films of resistive materials such as tin, tin-lead, nickel, gold and nickel-gold. In one such process, a resist material such as gold may be selectively plated onto the conductive pattern in an electroplating process. Referring to prior art FIG. 1 , the electroplating process can produce a plurality of gold-plated tails 20 on a substrate 22 . The plated leads 20 may terminate at solder pads 24 , vias 26 and contact fingers 28 that provide for external electrical connections. Not all plated leads 20 , pads 24 and fingers 28 are labeled in FIG. 1 . On the underside of the substrate 22 are plated leads 20 and pads 24 shown in dashed lines in FIG. 1 . The substrate 22 also includes plating bars 30 for shorting the various leads 20 , pads 24 , vias 26 and fingers 28 during the electroplating process.

In performing the electroplating process, the substrate 22 is dipped into a plating bath including metal ions in an aqueous solution. Plated bar 30 is supplied with current, which flows through lead 20 , pad 24 , via 26 and finger 28 . When current is delivered, leads 20, pads 24, vias 26 and fingers 28 are energized and a charge is generated on their surfaces. Metal ions are attracted to areas of the metal that are energized and charged. In this way, a layer of gold or other plated metal can be deposited to a desired thickness.

After electroplating, the plated strip 30 is removed. Importantly, the entire strip 30 is removed. However, due to engineering tolerances, a knife, router, or other device that cuts the substrate and removes the plated bars may deviate up, down, left, and/or right from the desired cut line. For example, an engineering tolerance of 50 micrometers (μm) is normal. When removing the strip, if a strip or part of the strip remains, for example due to deflection of the cutting device, as shown in FIG. This causes failure of the formed integrated circuit.

To prevent this, a cutting knife, router or other device 32 for removing the plated strip is provided with a large width w, as shown in prior art FIG. 3 . Ideally, the width of the removal device 32 is no greater than the width of the plated bar, eg, about 3 to 5 mils. However, engineering tolerances require that the knife be made wider to ensure that if the removal device 32 drifts up/down or left/right while removing the strip, the entire strip is still removed. For example, if the removal device (shown in dashed lines in Figure 3) is changed by a distance Δ from the desired removal path, the removal device must still be of sufficient width to completely remove the plated strip.

As a result of the large width of the removal device required by engineering tolerances in the removal process and the space required on either side of the strip, a relatively large kerf width k must be provided around each strip (Fig. 1 and Fig. 3). Conventional kerf widths may be about 250 μm or greater. Such a large kerf width takes up space on the substrate 22 that could otherwise be used for circuit portions of the substrate.

It is also known to plate substrates in electroless plating processes that do not employ plating bars. In electroless plating, metal ions in an aqueous solution are deposited onto a conductive pattern by a chemical reducing agent in the solution rather than an electric charge. However, such electroless plating processes have disadvantages, including high expense and inability to achieve precise patterning on the substrate.

Contents of the invention

Embodiments of the present invention relate to semiconductor die substrate panels that include a minimum kerf width between adjacent semiconductor package outlines on the panel while ensuring electrical isolation of plated electrical terminals. The substrate panel may be formed with plated bars between adjacent package outlines on the panel. The substrate panel may also include plated electrical terminals, such as pads and contact fingers, and plated leads electrically coupling the electrical terminals to the plated strips.

Each package outline may have electrical terminals connecting the plating strips on only two sides of the package outline. Furthermore, instead of placing the plated bars at the center of the cutouts between adjacent package outlines, the plated bars are located eccentrically in the cutouts. Specifically, the plating strip is closer to the package outline where the plating strip is not electrically coupled. The plating strip is spaced a sufficient distance from the package outline to which it is coupled to ensure that the plating strip is severed from its attached plated lead during the dicing process. This distance can vary according to engineering tolerances and other factors.

Having the plated wires connected on one side only and spaced from the package outlines to which they are connected offers the advantage that the kerf width between adjacent package outlines can have a narrower width than known in the prior art . Firstly, the width of the cutting device need not be greater than the width of the plated bar, since the plated bar does not have to be removed. Second, because part of the plated strips straddles the boundary between adjacent package outlines, even if the path of the cutting device deviates from a straight line due to engineering tolerances, the cut will still cut through the plated bars between adjacent package outlines to isolate the electrical terminals.

By reducing the width of the border between adjacent package outlines according to the invention, additional space is obtained for the semiconductor package on the substrate panel. For example, a portion of the package outline can become the entire package outline. Adding even a single row and/or column of semiconductor packages for a given size panel results in a huge increase in semiconductor package yield.

Description of drawings

FIG. 1 is a top view of a prior art semiconductor die substrate including multiple package outlines and a conventional grid of plated bars.

2 is a top view of a portion of a prior art semiconductor die substrate including a plated bar section partially removed.

3 is a top view of a portion of a prior art semiconductor die substrate showing the kerf width required by a conventional plated bar removal apparatus.

4 is a top view of a semiconductor die substrate including a plurality of package outlines and a grid of plating bars in accordance with an embodiment of the present invention.

5 is a top view of a package outline on the substrate panel of FIG. 4 according to an embodiment of the present invention.

6 is a top view of a package outline cut from a panel using cut lines that generally follow the package outline.

7 is a top view of a package outline cut from a panel using cut lines that generally do not follow the package outline.

8 is a top view of a package outline according to an alternative embodiment of the present invention.

9 is a cross-sectional side view of a semiconductor package formed with a substrate from a panel with plated bars in accordance with an embodiment of the present invention.

FIG. 10 is a rear view of a flash memory formed using the semiconductor package of FIG. 9 .

FIG. 11 is a flowchart of forming conductive patterns and plating on a substrate panel.

Detailed ways

Embodiments of the present invention will now be described with reference to FIGS. 4-11 , which relate to a semiconductor die substrate panel including a minimum kerf width between adjacent semiconductor package outlines on the panel while ensuring electrical isolation of plated contacts. . It should be understood that the invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments which are included within the scope and spirit of the invention as defined by the appended claims. Additionally, in the following detailed description of the invention, certain specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without such specific details.

Referring first to the top view of FIG. 4 , a substrate panel 100 including a plurality of package outlines 102 is shown. The package outline defines where each semiconductor package is formed on the substrate panel. Package outline 102 may or may not be visually discernible on substrate panel 100 .

The substrate panel 100 may be formed from a core having top and bottom conductive layers. The core may be formed from various dielectric materials such as polyimide sheets, epoxy including FR4 and FR5, bismaleimide triazine, and the like. Although not essential to the invention, the core may have a thickness between 40 μm and 200 μm, although in alternative embodiments the core may have a thickness outside this range. In alternative embodiments, the core may be ceramic or organic.

The conductive layer may be formed of copper or copper alloys, plated copper or plated copper alloys, alloy 42 (42Fe/58Ni), copper plated steel, or other metals and materials known for use on substrates. The layer may have a thickness of approximately 10 μm to 24 μm, although in alternative embodiments the thickness of the layer may be outside this range. One or both of the conductive layers can be etched in known photolithographic processes, and the conductive patterns are used for signal and power communication.

FIG. 5 shows a single package outline 102 from FIG. 4 , with plated strips 116 of electrical pin connections within the illustrated package outline 102 . The conductive pattern on one side of the substrate panel 100 may include contact fingers 106 for establishing an electrical connection between the completed semiconductor package and an external electronic device (in the form of an LGA or BGA). The conductive patterns on one or both sides of the substrate panel 100 may include solder pads 110 where electrical contacts for surface mount components, such as semiconductor die, are soldered to the substrate panel. Vias 112 may also be defined on the substrate panel 100 for electrical communication between conductive patterns on opposing surfaces of the substrate panel. The conductive patterns on one or both sides of the substrate panel 100 may further include plating leads 118 used in a plating process explained below.

A process for forming a conductive pattern including contact fingers 106 , pads 110 , via holes 112 , plated bars 116 and plated leads 118 on substrate panel 100 will be explained with reference to the flowchart of FIG. 11 . At step 150, the surface of the conductive layer is cleaned. Then at step 152, a photoresist film is applied over the surface of the conductive layer. Then at step 154, a pattern mask containing the outline of the conductive pattern is placed on the photoresist film. The photoresist film is exposed (step 156) and developed (step 158) to remove the photoresist from the areas on the conductive layer to be etched. Next at step 160, the exposed areas are etched away using an etchant such as ferric chloride to form a conductive pattern on the core. Next, at step 162, the photoresist is removed. Other known methods of forming conductive patterns on the substrate panel 100 are envisioned.

In step 164, after the conductive patterns are formed on one or both surfaces of the substrate panel 100, a resistive metal layer may be plated on the electrical terminals of one or both of the conductive patterns on the substrate panel. In particular, it is possible to short the electrical terminals of the conductive pattern to be plated and electrically isolate those electrical terminals from other parts not to be plated. The electrical terminals of the conductive pattern may include contact fingers 106 , pads 110 and vias 112 . In alternative embodiments, it may only include one or more of these. The electrical terminals are shorted via plated bars 116 and plated leads 118 formed on the substrate. Note that not all pads, vias and contact fingers in the package outline 102 are labeled in FIG. 5 . Plated leads 118 and solder pads 110 shown in dashed lines in FIGS. 4 and 5 are located on the underside of the substrate panel. Additionally, panel 100 may include more pads, vias, and/or contact fingers than shown. Although not shown, some of the electrical terminals may be formed to be electrically coupled to each other, and the electrical coupling between the terminals is later broken in a known etch-back process to isolate each terminal.

The electrical terminals of the conductive pattern can be plated with a metal film, for example gold, in a known manner. In alternative embodiments, other metals, including tin, tin-lead, nickel and nickel-gold, may be plated onto the conductive pattern. The width of the plated strip 116 can be determined by known rules, but can be between 3 mils and 5 mils. In alternative embodiments, the plated strips may be thinner or thicker.

In one embodiment of a process for plating a substrate panel 100, the panel may be dipped into a plating bath comprising metal ions in an aqueous solution. A current is then applied to the plated bar 116 , which flows through the plated bar 116 , through the leads 118 to the pads 110 , through the vias 112 and/or the contact fingers 106 . When a current is delivered, the plating strip 116, the lead 118, the pad 110, the via 112, and the finger 106 are energized and a charge is generated on their surfaces. Metal ions are attracted to areas of the metal that are energized and charged. A thin metal film is thus plated onto the shorted areas of the conductive pattern. The thickness of the coating may vary, in an embodiment it may be between 10 μm and 50 μm, although it may be thinner or thicker in alternative embodiments. In alternative embodiments, other known methods for plating metal films on conductive patterns may be used.

In the embodiment shown in Figures 4 and 5, all areas to be plated are shorted. It should be understood that two or more of the regions to be plated may be electrically isolated from each other. In such an embodiment, a current may be applied to each such shorted region. In such an embodiment, different coating thicknesses can also be obtained by applying more current in some regions relative to other regions, or by applying the same current for a longer period of time. Thus, for example, a thicker plating can be achieved at the contact fingers than at the solder pads and vias. It is also known that the contact fingers can be plated with two layers: a soft gold layer and a hard gold layer, to enhance the performance of the contact fingers. In embodiments a layer may be used on the contact fingers.

After the plating of the substrate is complete, each electrical terminal must be electrically isolated from each other. As explained in the Background of the Invention section, this is traditionally done with a wide cutting device ensuring removal of the plated strip, resulting in a wide kerf width between the package outlines. According to an embodiment of the present invention, the plating strip 116 need not be removed, but rather, the plating strip 116 is cut from the plating lead 118 to ensure that each electrical terminal is electrically isolated from the other.

In one embodiment shown in FIG. 4 and the enlarged view of FIG. 5 , each package outline may have electrical terminals connecting the plating strips 116 only on both sides of the package outline 102 . Furthermore, instead of a plated bar located in the center of the cutout between adjacent package outlines, the plated bar is located eccentrically within the cutout. Specifically, the plating strips are placed close to package outlines where they are not connected, and away from package outlines that have terminals to which the plating strips are connected.

Thus, for example in FIG. 5 , plated strip 116 located between package enclosures 102 and 102a is coupled to terminals within package enclosure 102 but not to terminals in package enclosure 102a. Plated strips between package outlines 102 and 102a are placed close to package outline 102a and away from package outline 102 . Similarly, plated strips 116 located between package outlines 102 and 102b are coupled to terminals within package outline 102 but not to terminals in package outline 102b. Plated strips between package outlines 102 and 102b are placed close to package outline 102b and away from package outline 102 . Although not shown, the plated strips coupled to the terminals within the package enclosure 102c may be located between the package enclosures 102 and 102c, proximate to the package enclosure 102, and the plated strips coupled to the terminals within the package enclosure 102d may be It is located between the package outline 102 and 102d, close to the package outline 102 .

Plated strips 116 are spaced a sufficient distance from their coupled package outlines to ensure that the package outlines are severed from their attached plated leads 118 during the dicing process. This distance can vary according to engineering tolerances and other factors. However, in an embodiment, the plated leads 118 may deviate between 125 μm and 50 μm (and more specifically about 100 μm) from the package outline to which they are coupled. It should be noted that in alternative embodiments, the plated bars may be offset by more or less than the amount described above. It should be understood that the horizontal plating bars 116 coupled to the package outline 102 may be spaced from the package outline 102 by the same amount or a different amount than the vertical plating bars 116 coupled to the package outline.

Referring now to FIG. 6 , there is shown package outline 102 that has been cut (by a method explained later) along dashed line 120 . In this example, there is no incorrect offset during cutting of the package outline, and the cut is made correctly at the perimeter of the package outline. However, as shown in the background section, due to engineering tolerances, the dicing device may shift during dicing so as not to cut precisely along the perimeter of the package outline. For example, in FIG. 7 the cut is offset upwards by an amount Δ ₁ and to the left (relative to the view shown in FIG. 7 ) by an amount Δ ₂ . Because the plated strips coupled to the electrical terminals within the package outline deviate from the package outline 102 by more than the tolerance of the cutting system, the horizontal plated strip above the package (not shown) remains on the cut line even though the cut is offset upwards. outside. The same is true if the cut is offset to the right of the package outline 102 shown in FIG. 7 .

Since the cut is offset to the left by Δ ₂ , the plating strip 116 shown in FIG. 7 to the left of and close to the package outline 102 is included in the cut. However, because the illustrated plating strips 116 are not coupled to any electrical terminals in the illustrated package enclosure 102 , no electrical shorting of the electrical terminals occurs in the illustrated package enclosure 102 . The portion of plated strip 116 shown may remain harmlessly within the semiconductor package to be formed using package outline 102 . The same is true if it is shifted downward from that shown in FIG. 7 . Additionally, cuts along the left edge of package outline 102 will cut through and electrically isolate electrical terminals in any adjacent package outlines to the left of package outline 102 as shown.

Having the plated lines spaced from the package outlines to which they are coupled provides the advantage that the cutout width k between adjacent package outlines can have a thinner width than is known in the prior art. Firstly, the width of the cutting device need not be greater than the width of the plated bar, since the plated bar does not have to be removed. Second, even if the path of the cutting device deviates from a straight line due to engineering tolerances, the cut will still separate the electrical terminal from the plated bar to isolate the electrical terminal because the distance separating the plated bar from the coupled package outline is far out of tolerance.

Thereby, the kerf width between adjacent package outlines can be reduced because the width of the cutting device can be made smaller and the space required for previous engineering tolerances can be omitted. In an embodiment, this allows for a kerf width of about 100 μm to 225 μm, or alternatively, 150 μm to 200 μm, and more specifically about 175 μm. It should be understood that in alternative embodiments, the slit width may be wider or smaller than this. In an embodiment where the kerf width is 175 μm, a plated strip may be located between the first and second package outlines, 25 μm from the first package outline, wherein the plated strip is coupled to a terminal in the second package outline. It should be understood that in the above example, in alternative embodiments, the plated bars could be closer or farther apart than 25 μm. In an embodiment, a plated wire may be located within a first package outline, with a plated bar coupled to a terminal in a second package outline.

The size of the substrate panel is typically selected by the semiconductor package manufacturer, and is generally not selected for a particular number of package outlines. Set the size, then provide as many package outlines as will fit on that size. If the density of package outlines is to be maximized on a substrate panel of a given size, it is rarely appropriate to fit an integer number of package outlines on a substrate panel. Instead, maximizing density yields a given integer number of package outlines, and a fraction of package outlines at the side and bottom edges. For example, a substrate panel may fit 10 package outlines over the entire length of the panel, leaving a fraction of the package outlines. Obviously, fractional semiconductor packages cannot be manufactured. Thus, conventionally, in this example, 10 such packages would be formed on the substrate panel, and the 10 packages distributed over the entire length of the panel (ie, increasing the boundaries between packages).

However, by reducing the width of the boundaries between adjacent package outlines according to the invention, a panel with 10 such boundaries can reclaim enough space to complete 11 package outlines, thereby allowing an additional column of semiconductor packages. Adding even a single row and/or column of semiconductor packages within a panel of a given size can result in a huge increase in semiconductor package yield.

Although the plating strip 116 is shown offset upward and to the right relative to the cutout centerline between the package outlines 102 on the panel 100 in FIGS. For example, Figure 8 shows a plated strip offset downward and to the left relative to the centerline of the incision. Furthermore, the plated strips according to the present invention need not consist only of straight lines on the panel 100 . A single plated line 116 and horizontal and vertical components placed as described above are also contemplated.

As used herein and explained in more detail below, the term "cut" may refer to separating the package outline 102 from the panel, or the term "cut" may otherwise refer to cutting through the plating strip without cutting through the substrate. In an embodiment, the plating strip 116 may remain intact for the remainder of the semiconductor package after the plating process. When packaging the panels as described below, the panels may be singulated into individual semiconductor packages. In such an embodiment, the plated strips may be cut when the package is detached. Package separation and dicing of plated strips can be performed by a variety of dicing methods used to separate semiconductor packages.

Sawing is generally less expensive, takes less time, requires less equipment than other cutting methods, and can be used to separate semiconductor packages. However, it should be understood that in alternative embodiments, panel 100 may be separated by various cutting methods, such as waterjet cutting, laser cutting, water guided laser cutting, dry media cutting, and diamond coated wire. Water can also be used with laser cutting to help replenish or focus its effects. Although semiconductor packages are shown as square or rectangular, in alternative embodiments they may additionally or instead have irregular or curvilinear shapes. A further description of cutting a semiconductor package from a panel and the resulting shape is disclosed in Published U.S. Application No. 2004/0259291 entitled "Method For Efficiently Producing Removable Peripheral Cards", assigned to the owner of the present invention and This application is hereby incorporated by reference in its entirety.

In an embodiment, after the plating process, the plating strip 116 may be cut without cutting through the substrate panel 100 . A router may be used to cut through the plated strip 116 without cutting through the substrate panel, as is known in the art.

The substrate panel 100 including plated bars, leads and electrical terminals as described above may be formed into a plurality of semiconductor packages 130 , one of which is shown in FIG. 9 . After plating the conductive pattern on the substrate panel 100, one or more passive devices 132 and semiconductor die 134 may be mounted on the substrate panel. Although not critical to the invention, semiconductor die 134 may be a flash memory chip (NOR/NAND), SRAM or DDT, and/or a controller chip such as an ASIC. Other silicon chips can be considered.

One or more die 134 may be electrically connected to substrate panel 100 by wire bonds 136 soldered at plated pads 110 in a known wire bonding process. Thereafter, the substrate and die may be packaged in a molding compound in known packaging processes to form a complete semiconductor die package 130 . The molding compound can be applied according to various techniques, including by transfer molding or injection molding techniques, to package the package. After being packaged, each package outline 102 may be detached from the panel into individual semiconductor packages 130 . If the plated wires have not already been cut, cut them during the process of detaching the package from the panel.

FIG. 10 is a rear view of a flash memory device 140 in which semiconductor package 130 may be used. The flash memory device can be SD card, Compact Flash, Smart Media, Mini SD card, MMC, xD card, Transflash or memory stick. Other arrangements are conceivable.

The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiment described was chosen in order to best explain the principles of the invention and its practical application, to enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. invention. It is intended that the scope of the invention be defined by the appended claims.

Claims (18)

1. A method of minimizing a kerf width in a substrate panel comprising a plurality of package outlines defining a location for forming a semiconductor package, the method comprising the steps of: (a) forming a plated bar on the substrate panel between first and second adjacent package outlines, said step (a) comprising forming a plated bar closer to the first package outline than the second package outline; (b) electrically coupling the plated bars to electrical terminals in the second package outline without electrically coupling the plated bars to electrical terminals in the first package outline, and the first package outline and the second package outline each of the package outlines includes electrical terminals from up to two plated bars; and (c) cutting the electrical coupling between the electrical terminal in the second package outline and the plated strip, said step (c) having a tolerance for cutting away from the intended cut line, said step (a) plating The strip is formed close enough to the first package to prevent electrical shorting of two or more electrical terminals on the second package outline by the plated strip due to cutting tolerances. 2. The method of claim 1, wherein said step (a) of forming a plated strip on the substrate panel between first and second adjacent package outlines comprises the step of forming a distance between first and second A plated strip whose centerline between two adjacent package outlines exceeds 50 μm. 3. The method of claim 1, wherein said step (a) of forming a plated strip on the substrate panel between first and second adjacent package outlines comprises the step of forming a Plated strips with a profile of 25 μm or less. 4. The method of claim 3, wherein the kerf width between the first and second package outlines is between 100 [mu]m and 225 [mu]m. 5. The method of claim 1, wherein the kerf width between the first and second package outlines is between 100 μm and 225 μm. 6. The method of claim 1, wherein the kerf width between the first and second package outlines is between 150 μm and 200 μm. 7. The method of claim 1, wherein said step (b) of electrically coupling the plating strip to electrical terminals in the second package outline comprises the step of: connecting the plating strip and one or more contact fingers , pads and through-holes to add plated leads. 8. The method of claim 1, wherein step (c) includes cutting through the plated bar and the substrate beneath the plated bar. 9. The method of claim 1, wherein step (c) includes cutting through the plated strip. 10. A substrate panel for manufacturing a semiconductor package, the substrate panel comprising a plurality of package outlines defining a location for forming a semiconductor package, the substrate panel comprising: a first package outline of the plurality of package outlines, the first package outline including electrical terminals on a surface, a first edge, and a second edge adjacent to the first edge; a second package outline of the plurality of package outlines, the second package outline including electrical terminals and adjacent to the first edge of the first package outline; a third package outline of the plurality of package outlines, the third package outline including electrical terminals and adjacent to a second edge of the first package outline; a first plating strip between the first and second packaging outlines, the first plating strip being electrically coupled to electrical terminals in the first packaging outline and not electrically coupled to electrical terminals in the second packaging outline, The first plated strip is located between the first and second package outlines closer to the second package outline; and a second plating strip between the first and third packaging outlines, the second plating strip being electrically coupled to electrical terminals in the first packaging outline and not electrically coupled to electrical terminals in the third packaging outline, The second plating strip is located between the first and third package outlines and is closer to the third package outline. 11. The substrate panel as claimed in claim 10 , wherein the first plating strip is sufficiently close to the second package to prevent electric current passing through the first plating strip due to the cutting device deviating from the intended cutting line during the process of cutting the first plating strip. One or more electrical terminals of the first package outline are shorted. 12. The substrate panel of claim 10, wherein the first plating strip is separated from the first edge by about the same distance as the second plating strip is separated from the second edge. 13. The substrate panel of claim 10, wherein the distance separating the first plating strip from the first edge is different from the distance separating the second plating strip from the second edge. 14. The substrate panel of claim 10, wherein the first plated strip is more than 50 μm from a centerline between first and second adjacent package outlines. 15. The substrate panel of claim 10, wherein the first plated bar is 25 μm or less from the first package outline. 16. The substrate panel of claim 15, wherein the kerf width between the first and second encapsulation outlines is between 100 μm and 225 μm. 17. The substrate panel of claim 10, wherein a kerf width between the first and second encapsulation outlines is between 100 μm and 225 μm. 18. The substrate panel of claim 10, wherein the electrical terminals are plated with one of: gold, nickel, or a gold-nickel alloy.

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