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CN101728261A - 制造低k介电膜的方法及使用低k介电膜的气隙的形成 - Google Patents

制造低k介电膜的方法及使用低k介电膜的气隙的形成 Download PDF

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CN101728261A
CN101728261A CN200910180452A CN200910180452A CN101728261A CN 101728261 A CN101728261 A CN 101728261A CN 200910180452 A CN200910180452 A CN 200910180452A CN 200910180452 A CN200910180452 A CN 200910180452A CN 101728261 A CN101728261 A CN 101728261A
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dielectric film
substrate
deposition
plasma
icp
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梁宰瑛
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DB HiTek Co Ltd
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Dongbu Electronics Co Ltd
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Abstract

本发明披露了一种制造介电膜的方法以及一种使用制造的低k介电膜形成气隙的方法。制造低k介电膜的方法包括：将TMS和3、3-二甲基-1-丁烯导入到等离子体沉积反应器中，利用反应器中产生的等离子体来聚合TMS和3、3-二甲基-1-丁烯，从而在置于反应器中的衬底上沉积绝缘膜，以及使沉积的绝缘膜同时遭受热处理和ICP工艺。

Description

制造低k介电膜的方法及使用低k介电膜的气隙的形成
本申请要求于2008年10月15日提交的韩国专利申请第10-2008-0101130号的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体器件，更具体地，涉及一种制造具有不大于2.4的低介电常数(对半导体器件有用)的介电绝缘膜的方法，以及使用所制造的介电绝缘膜形成气隙(air-gap)的方法，其中，制造介电绝缘膜的方法包括：使用配置有双起泡器(bubbler)的等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)装置并通过执行电感耦合等离子体快速热退火(inductivelycoupled plasma-rapid thermal annealing，ICP-RTA)工艺沉积等离子体聚合SiCOH-CHx膜(plasma polymerized SiCOH-CHx film)。
背景技术
通常，具有CPU、存储器和系统LSI的大规模集成(large-scaleintegration，LSI)装置采用碳基氧化硅膜作为层间介电膜，以降低导致信号延迟的互联电容(interconnection capacity)。
具有不同成分的多种碳化硅膜是众所周知的。这些薄膜中的一种可以是包含硅Si、碳C和氢H的碳化硅膜。这种薄膜具有相对高的吸水性和/或吸氧性，其缺点在于：在暴露到空气中之后，薄膜应力或介电性能通常发生改变。碳化硅膜表现出高的漏电流和差的电隔离(electric isolation)。
为解决以上问题，已经开发了通过使用惰性等离子气体(inertplasma gas)处理薄膜的表面以防止水分或氧气穿过薄膜表面的技术。然而，尽管这些途径改善了薄膜的表面的质量，但并未提高碳氢化硅(SiCH)膜的内部特征。结果，薄膜仍表现出高的漏电流和差的电隔离。碳化硅膜的介电常数约为4.5至5。
具有不同成分的碳化硅膜的实例可以包括包含Si、C、N和H的碳化硅膜、包含Si、C、O和H的碳化硅膜等。
相比于上述SiCH膜，碳化硅膜表现出相对低的漏电流以及优良的电隔离。特别地，根据氧相对于其它成分的比例，SiOCH膜的介电常数可以约为4.2。
由于应降低层间介电(ILD)材料的介电常数以便提高半导体集成电路的性能，因此仍需要介电常数不大于3的薄膜。
发明内容
因此，本发明旨在解决上述有关传统技术的问题，本发明的一个目的在于提供一种制造具有低介电常数的绝缘膜(在下文中，称为“低k介电膜(a low-k dielectric film)”)的方法以及利用所制造的低k介电膜形成气隙(air-gap)的方法。
为达到以上目的，根据本发明的示例性实施例，提供了一种制造介电膜的方法，包括：将三甲基硅烷(trimethylsilane，TMS)和3、3-二甲基-1-丁烯(3，3-dimethyl-1-butene)导入到等离子体沉积反应器中；利用反应器中产生的等离子体来聚合TMS和3、3-二甲基-1-丁烯以便在置于反应器中的衬底上沉积绝缘膜；以及使沉积的绝缘膜同时遭受热处理和ICP工艺。
为达到以上目的，根据本发明的示例性实施例，还提供了一种利用制造的低k介电膜来形成气隙的方法，包括：制备图样化的衬底；在图样化的衬底的表面上沉积第一绝缘膜；利用CVD工艺遍及沉积有第一绝缘膜的衬底的表面来沉积十氢化萘层，以便用十氢化萘层填充图样化的衬底的间隙；使处理过的衬底遭受化学机械抛光(chemical mechanical polishing，CMP)工艺，以使形成在衬底上的十氢化萘层和第一绝缘膜被顺序平坦化；聚合TMS和3、3-二甲基-1-丁烯以便用聚合的TMS和3、3-二甲基-1-丁烯在平坦的衬底上沉积第二绝缘膜；以及使沉积的第二绝缘膜同时遭受热处理和ICP工艺，以便使填充在衬底间隙中的十氢化萘层通过第二绝缘层以气体形式释放出来(out-gassing)，从而形成气隙。
可以理解的是，本发明的上述总体描述和以下的具体描述都是示例性的和说明性的，并且旨在提供对所要求的本发明的进一步解释。
附图说明
附图被包括用来提供对本发明的进一步理解，并结合于此而构成本申请的一部分。本发明的示例性实施例连同描述都用来解释本发明的原理。在附图中：
图1是示出了根据本发明的示例性实施例的制造低k介电膜的方法的流程图；
图2A是示出了用于制造根据本发明的示例性实施例的低k介电膜的PECVD装置的示意图；
图2B是示出了用于制造根据本发明的示例性实施例的低k介电膜的ICP-RTA装置的示意图；
图3A描述了作为图1中所示的前驱体的TMS的结构；
图3B描述了作为图1中所示的前驱体的3、3-二甲基-1-丁烯的结构；
图3C描述了聚合TMS和3、3-二甲基-1-丁烯的结构；
图4示出了通过图1中所示的方法制造的介电膜的介电常数；
图5示出了在ICP-RTA处理之前和之后的介电膜的漏电流密度；
图6是示出了在ICP-RTA处理之前和之后的介电膜的化学结构分析结果的曲线图；
图7示出了在ICP-RTA处理之后的介电膜的硬度和弹性模量；以及
图8A至8E是示出了使用由图1中所示的方法制造的介电膜形成气隙的各个过程的横截面图。
具体实施方式
在下文中，本发明的技术结构和特征将通过参照优选的实施例连同附图的详细描述变的显而易见。将通过本发明的优选的实施例给出以下详细描述。
图1是示出了根据本发明的示例性实施例的制造低k介电膜的方法的流程图，图2A是示出了用于制造根据本发明的示例性实施例的低k介电膜的PECVD装置的示意图；图2B是示出了用于制造根据本发明的示例性实施例的低k介电膜的ICP-RTA器件的示意图。
参照图1和图2A，作为前驱体溶液的TMS储蓄在第一起泡器(bubbler)210中，而3、3-二甲基-1-丁烯储蓄在第二起泡器215中。这样的第一起泡器210和第二起泡器215的组合被称为双起泡器。
第一传输部分220储蓄诸如Ar的第一载气(carrier gas)，而第二传输部分225储蓄诸如N2O的第二载气(carrier gas)。
加热并蒸发前驱体溶液，即，TMS和3、3-二甲基-1-丁烯。使用Ar和N2O作为载气，分别将蒸发的TMS和3、3-二甲基-1-丁烯导入到反应器230中以用于等离子体沉积(步骤S110)。
导入的TMS和3、3-二甲基-1-丁烯通过反应器230的喷头(showerhead)235被注入到在反应器内的晶片240(在下文中，称为“衬底”)中。然后，利用反应器230中产生的等离子体，由注入的TMS和3、3-二甲基-1-丁烯来沉积衬底240(步骤S120)。
在沉积过程中，衬底240的温度可以从300℃到400℃变化，并使用由电源245提供的RF功率以及密度为0.1W/cm2至1.5W/cm2的等离子体，以便使TMS和3、3-二甲基-1-丁烯聚合。同样地，沉积在衬底240上的所得绝缘膜可以具有SiOCH-CHx的结构(其中x是自然数)以及0.4至0.5μm的沉积厚度。
图3A描述了作为前驱体的TMS的结构，图3B描述了作为另一种前驱体的3、3-二甲基-1-丁烯的结构，图3C描述了聚合TMS和3、3-二甲基-1-丁烯的结构。
导入到反应器230的前驱体TMS和3、3-二甲基-1-丁烯可以通过等离子体被活化或裂解为活性组分(reactive species)，从而凝结在衬底240上。使用TMS和3、3-二甲基-1-丁烯作为前驱体可以增加CHx基团的数量，从而将介电常数降低至小于2.4。
然后，如图2B所示，通过使用ICP-RTA装置使具有SiOCH-CHx结构的沉积的绝缘膜遭受ICP-RTA(步骤130)。
卤素灯250可以产生热并以350至450℃执行热处理，其中，卤素灯250发射波长为2至5μm的光并被设置在衬底240的周围，而衬底240沉积有具有SiOCH-CHx结构的绝缘膜248。同时，利用RF功率(RF power)产生N2O等离子体以使得具有SiOCH-CHx结构的绝缘膜遭受等离子体工艺，其中，通过向衬底240和6匝Cu线圈245施加RF电源265来提供RF功率。施加到Cu线圈的RF功率的频率可以从13变化至14MHz，而施加至等离子体导板260的RF功率的频率可以从100变化至150KHz。
具有SiOCH-CHx结构的绝缘膜248同时遭受热处理和等离子体处理。热处理可以分离出绝缘膜248(具有SiOCH-CHx结构)中与Si结合的CHy，其中，y可以等于或小于x。
包含在N2O等离子体中的氧被置于空位中以替代由热处理分离出的CHy，从而提高了绝缘膜248的强度。
图4示出了由图1中所示的方法制造的介电膜的介电常数。参照图4，当聚合TMS和3、3-二甲基-1-丁烯所需要的等离子体密度增加时，介电常数可以降低至2.15。
图5示出了在ICP-RTA处理之前和之后的介电膜的漏电流密度(f1和f2)。参照图5，通过k为2.15的介电膜的漏电流特征可以看出：在ICP-RTA处理之后很好地改善了击穿电压特性。
图6是示出了在ICP-RTA处理之前和之后的介电膜的化学结构的分析结果的曲线图(g1和g2)。参照图6，通过使用红外光谱分析介电膜的化学结构(infrared spectroscopy)的结果表明在相同的频率下化学结构g1和g2都被展宽了。因此，可以看出在等离子体沉积绝缘膜(plasma deposited insulation film)的ICP-RTA处理之前和之后，介电膜的键合结构(bonding structure)基本类似。
图7示出了在ICP-RTA处理之后的介电膜的硬度和弹性模量。参照图7，在ICP-RTA处理之后的介电膜的硬度和弹性模量分别是1.25GPa和10GPa。
如图4和7所示，根据本发明的示例性实施例制造的等离子体聚合介电膜(plasma polymerized dielectric film)可以在诸如介电性能、热稳定性、不变的化学键合结构、强度(硬度)和弹性模量的特性上有所改善。
利用线型有机和无机前驱体材料可以提供低k介电膜，而利用ICP-RTA装置的后处理(post-treatment)可以改善等离子体聚合介电膜(plasma polymerized dielectric film)的介电常数和机械强度。
图8A至8E是示出了利用根据图1中所示的方法制造的介电膜来形成气隙(air-gaps)的各个过程的截面图。
如图8A所示，在图样化的晶片810(即，衬底)上沉积厚度为5至10nm的非掺杂硅酸盐玻璃(undoped silicate glass，USG)层820。这里，图样化的衬底810可以是应用到衬底的金属图样、沟槽图样或接触孔图样。USG层820可以形成在图样衬底810中的间隙815的内表面以及衬底的表面上。
然后，如图8B所示，通过使用化学气相沉积CVD，遍及具有USG层820的衬底810沉积等离子体聚合十氢化萘(plasmapolymerized decahydronaphthalene(DHN))层830。在这种情况下，等离子体聚合DHN层830可以填充在图样化的衬底的间隙815中也可以形成在USG层820上方。
初始沉积状态的等离子体聚合DHN层830是热不稳定的，并且具有小的分子尺寸，从而表现出优良的间隙填充能力(gap-fillingcapacity)。
如图8C所示，可以执行CMP工艺以顺序平坦化形成在衬底810上的DHN层830和USG层820。例如，DHN层830和USG层820被顺序平坦化并被去除直到暴露衬底810。
如图8D所示，根据图1中所示的过程S110和S120，在平坦的衬底810上沉积低k(即，2.7≤k≤3)介电膜840。
然后，沉积的介电膜840遭受350至450℃的RTA热处理并同时遭受ICP工艺。
通过热处理，沉积的介电膜840可以变为具有多孔结构845(简称为“多孔膜”)的薄膜。热处理使填充在衬底的间隙815中的DHN层830通过多孔膜845以气体形式释放出来，从而在向外释放气体的空间形成了气隙850。这种气隙850可以大幅减小导线之间的寄生电容，从而有效地降低了对驱动器件中RC延迟和/或信号失真的影响。
为改善沉积的多孔膜845的隔离性能并从多孔膜845固定和/或去除残留物，可以持续5至60秒来执行使用He和N2O的ICP工艺，以在多孔膜845的表面上方形成厚度为5至10nm的增强层(improved layer)847。
因此，通过ICP-PECVD形成的等离子体聚合膜可以用作牺牲层以通过热处理形成气隙，其中，等离子体聚合膜是热不稳定的，即在低于250℃时完全分解。由于在这里使用的等离子体聚合膜仅由有机材料组成，因此可以将具有大量热不稳定的CH2基团的DHN用作前驱体以通过执行RTA-IPC处理形成多孔膜845。从而，如图8E所示，可以形成共形气隙(conformal air-gap)850，同时降低多孔膜845的介电常数。
从以上描述显而易见的是，根据本发明的优选实施例制造低k介电膜的方法可以通过使用TMS和3、3-二甲基-1-丁烯作为前驱体来提供具有低介电常数的绝缘膜，并且还可以通过使用ICP-RTA装置的后处理来有效地改善绝缘膜的介电常数和机械性能。
此外，根据本发明的优选实施例的使用上述制造的低k介电膜来形成气隙的方法可以利用具有大量热不稳定的CH2基团的DHN作为前驱体，通过执行RTA-IPC处理来制造绝缘膜，并且可以利用制造的绝缘膜从而形成共形气隙，同时有效地降低绝缘膜的介电常数。
本发明不局限于上述示例性的实施例和附图，但在不脱离本发明的精神和范围内可以涵盖其替代、修改和/或变形，这对于本领域的技术人员而言是显而易见的。因此，本发明不限制于以上描述所述的内容，而是解释为在所附的权利要求所界定的本发明的范围内。

Claims (10)

1.一种制造介电膜的方法，包括：
将三甲基硅烷(TMS)和3、3-二甲基-1-丁烯导入到等离子体沉积反应器中；
利用在所述反应器中产生的等离子体来聚合TMS和3、3-二甲基-1-丁烯，以便在置于所述反应器中的衬底上沉积绝缘膜；以及
使所述沉积的绝缘膜同时遭受热处理和电感耦合等离子体(ICP)工艺。
2.根据权利要求1所述的方法，其中，通过使用等离子体聚合TMS和3、3-二甲基-1-丁烯来执行所述绝缘膜的沉积。
3.根据权利要求1所述的方法，其中，通过使用电感耦合等离子体快速热退火(ICP-RTA)装置同时执行所述热处理和所述ICP工艺。
4.根据权利要求1所述的方法，其中，所述同时进行的热处理和ICP工艺包括：通过利用设置在所述衬底周围的卤素灯来产生热，并以350至450℃加热所述沉积的绝缘膜以完成所述热处理，其中，所述衬底沉积有所述绝缘膜，所述卤素发出波长为2至5μm的光。
5.根据权利要求4所述的方法，其中，所述同时进行的热处理和ICP工艺包括：对所述沉积的绝缘膜的热处理，同时，在所述反应器中产生N2O等离子体，从而用所述产生的等离子体处理所述沉积的绝缘膜。
6.根据权利要求1所述的方法，其中，由聚合TMS和3、3-二甲基-1-丁烯得到的所述绝缘膜具有SiOCH-CHx基本结构，其中x为自然数。
7.一种形成气隙的方法，包括：
制备图样化的衬底；
在所述图样化的衬底的表面上沉积第一绝缘膜；
通过CVD工艺遍及沉积有所述第一绝缘膜的所述衬底的表面来沉积十氢化萘(DHN)，以便用所述DHN层来填充所述图样化衬底的间隙；
使所述处理的衬底遭受化学机械抛光(CMP)工艺，以使得在所述衬底上形成的所述DHN层和所述第一绝缘膜被顺序平坦化；
聚合TMS和3、3-二甲基-1-丁烯以在所述平坦的衬底上沉积第二绝缘膜；以及
使所述沉积的第二绝缘膜同时遭受热处理和ICP工艺，以使填充在所述衬底的所述间隙中的所述DHN层通过所述第二绝缘层以气体形式释放出来，从而形成气隙。
8.根据权利要求7所述的方法，其中，所述沉积所述第一绝缘膜包括在所述衬底的所述表面上沉积非掺杂硅酸盐玻璃(USG)层。
9.根据权利要求7所述的方法，其中，所述顺序平坦化所述DHN层和所述第一绝缘膜包括：顺序平坦化所述DHN层和所述第一绝缘膜直到暴露所述衬底，然后去除所述DHN层和所述第一绝缘膜两者。
10.根据权利要求7所述的方法，其中，所述气隙的所述形成包括：350至450℃快速热退火(RTA)热处理和同时进行的ICP工艺，其中所述第二绝缘膜的所述表面遭受使用He和N2O气体的所述ICP工艺。
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