CN101719497B - New type integrated circuit for resisting full-scale irradiation of NMOS component - Google Patents

Abstract

The invention discloses an integrated circuit capable of resisting total dose irradiation of NMOS devices, which belongs to the field of electronic technology. The anti-NMOS device total dose radiation integrated circuit of the present invention includes NMOS devices, and may also include PMOS devices, and the devices are separated by trenches on the substrate, and the trenches are filled with trench-filling materials, which are characterized in that, In a trench adjacent to the NMOS device, a sacrificial material layer is embedded in the trench filling material, and the sacrificial material is silicon doped with elements of the third main group. The invention can be used in industries related to total dose irradiation, such as aerospace, military affairs, nuclear power and high energy physics.

Description

Integrated circuits resistant to total dose irradiation of NMOS devices

technical field

The invention relates to an integrated circuit, in particular to an integrated circuit capable of resisting total dose irradiation of NMOS devices, and belongs to the field of electronic technology.

Background technique

Integrated circuit technology is being more and more widely used in industries related to total dose radiation, such as aerospace, military, nuclear power and high-energy physics. Moreover, with the continuous improvement of the integration level of integrated circuits, the size of semiconductor devices is decreasing day by day. Shallow trench isolation technology is becoming the mainstream technology for electrical isolation between devices in integrated circuits due to its excellent device isolation performance. However, due to the damage of the silicon dioxide oxide layer in the device by the total dose of irradiated particles, a large amount of fixed positive charges will be generated in the oxide layer of the shallow trench isolation structure. In NMOS devices, the existence of a large number of fixed positive charges will cause the substrate inversion near the shallow trench isolation oxide layer, and form a parasitic tube leakage under a certain source-drain bias. The distance from the substrate is related to the concentration of these positive charges, that is, the stronger the positive charge of the shallow trench isolation structure material after total dose irradiation, the closer it is to the silicon substrate, and the greater the leakage. Before the device supervisor is turned on, the supervisor is in the off state, but at this time the parasitic tube has been turned on, resulting in a large off-state leakage current. This off-state leakage current will greatly increase the power consumption of the integrated circuit, and have a greater negative impact on the reliability of the integrated circuit, which has become a total dose radiation reliability issue that needs to be solved urgently at this stage.

Therefore, if it is possible to propose a method that can reduce the positive charge of the shallow trench isolation material after total dose irradiation and increase the distance between the positive charge and the silicon substrate without changing the mainstream preparation process of the shallow trench isolation technology, In order to suppress these positive charges, thereby reducing the total dose of NMOS devices after irradiation, the isolation technology of CMOS integrated circuits and device off-state leakage currents will be of great significance to the radiation resistance of the entire integrated circuit.

Contents of the invention

The object of the present invention is to provide an anti-total dose irradiation integrated circuit which can reduce the off-state leakage current of NMOS devices after total dose irradiation.

The present invention is based on the existing shallow-trench isolation technology (shallow-trench isolation: STI) for CMOS integrated circuits, aiming at the characteristic that positive charges in silicon dioxide can induce negative charges in silicon materials, in conventional shallow-trench isolation structures A layer of sacrificial material is added in the shallow trench isolation structure, and the electric field of a large number of fixed positive charges in the silicon dioxide in the shallow trench isolation structure is limited to this layer of sacrificial material layer, so as to weaken the inversion effect on the bulk silicon substrate, thereby reducing The parasitic transistor current after total dose irradiation achieves the purpose of reducing the off-state leakage current of NMOS devices after total dose irradiation.

Specifically, in order to achieve the above technical purpose, the present invention adopts the following technical solutions:

An integrated circuit capable of resisting total dose radiation of NMOS devices, the integrated circuit includes NMOS devices, and may also include PMOS devices, the devices are separated by trenches on a substrate, and the trenches are filled with trench filling materials , characterized in that, in a trench adjacent to the NMOS device, a sacrificial material layer is embedded in the trench filling material, and the sacrificial material is silicon doped with elements of the third main group. That is to say, the sacrificial material layer is provided in the two trenches on both sides of each NMOS device, regardless of whether the NMOS device is adjacent to the NMOS device or the PMOS device, as shown in FIG. 1 b .

The layer of sacrificial material is sandwiched between two parts of the trench fill material separated, a first part (lower part) of which is located between the substrate and the layer of sacrificial material and a second part (upper part) is covered by the The sacrificial material layer is enclosed on three sides. The above-mentioned three-layer structure is generally obtained by depositing each layer in sequence, that is, depositing the first part, the sacrificial material and the second part in sequence. Therefore, the cross-sectional shape of the first part and the sacrificial material layer is consistent (corresponding) to the profile of the trench, that is, because the cross-section of the trench is generally an inverted trapezoid (the upper base is longer than the lower base) Trapezoid), therefore, the cross sections of the first part and the sacrificial material layer are both U-shaped.

The third main group element includes one or more of boron, aluminum, gallium, indium and thallium. The doping concentration of the sacrificial layer material is in the range of 5×10 ¹⁶ to 1×10 ¹⁸ /cm ³ ; the thickness is preferably in the range of 10 nanometers and 80 nanometers.

The trench filling material may be conventionally used silicon dioxide, and the substrate material may be conventionally used silicon.

Figures 1a and b respectively show the interface structure between the trench and the substrate in the conventional shallow trench isolation technology and the present invention. Fig. 2 shows the comparison of the inversion carrier concentration produced in the substrate after the total dose irradiation of the conventional shallow trench isolation process structure and the anti-total dose irradiation process structure of the present invention.

It can be seen from Figure 1 and Figure 2 that in the conventional shallow trench isolation process structure, due to the existence of trench filling materials, a large amount of fixed positive charges generated in the trench by total dose irradiation will be induced in the silicon substrate. A large number of reverse carriers, that is, a large number of electrons, are mirrored by the bio-image, and these electrons can be turned on when the source and drain are biased, resulting in a large leakage current when the NMOS transistor is in the off state. The anti-total dose irradiation process structure of the present invention aims at the characteristics that positive charges in silicon dioxide can induce negative charges in silicon materials, and a sacrificial layer of silicon material is added to the conventional shallow trench isolation structure, and the shallow trench isolation structure The electric field of a large number of fixed positive charges in silicon dioxide is limited on this layer of sacrificial layer, and the existence of a large number of fixed negative charges generated by positive charges in silicon dioxide in the sacrificial layer of silicon material greatly weakens the resistance of silicon dioxide in the shallow trench isolation structure. The inverse effect on the bulk silicon substrate, and increases the distance between a large number of fixed positive charges in the shallow trench isolation structure and the substrate, and a thin layer of silicon dioxide material that is in contact with the substrate (ie the first part above) ) Because it is very thin (for example, 10 nanometers to 20 nanometers), the amount of fixed positive charges generated inside is very small, and the impact on the substrate can be ignored. This structural design can suppress or even counteract the image induction effect of fixed positive charges in the trench filling material on the carriers in the silicon substrate, suppress the carrier inversion of the silicon substrate, and make the conduction of the parasitic transistor. The flow rate is greatly reduced or even reduced to zero, thereby greatly reducing the off-state leakage current of the NMOS device, and greatly improving the radiation resistance performance of the integrated circuit.

In addition, another feature of the anti-total dose irradiation process structure of the present invention is that the P-type doped silicon process material used is fully compatible with the traditional CMOS process, and retains the traditional shallow trench isolation The process structure has all the technical advantages in the isolation of integrated circuits, and the manufacturing process steps are very simple.

Compared with the prior art, the isolation technology proposed by the present invention can greatly reduce the off-state leakage current after the total dose of the integrated circuit NMOS device is irradiated, and can greatly enhance the anti-total dose radiation performance of the integrated circuit, which is helpful for reducing the total dose The power consumption of integrated circuits under irradiation and the enhancement of reliability of integrated circuits are of great significance. In the application of integrated circuit anti-total dose radiation hardening technology, it has obvious advantages and broad application prospects.

Description of drawings

Fig. 1 shows the interface structure difference between the conventional shallow trench isolation technology and the integrated circuit of the present invention between the trench and the substrate, Fig. 1a represents the conventional technology, and Fig. 1b represents the technology of the present invention;

Fig. 2 shows the comparison of the inversion carrier concentration in the substrate after the conventional shallow trench isolation process structure and the anti-total dose irradiation process structure of the present invention are subjected to total dose irradiation;

Figures 3-8 show various steps in the fabrication of integrated circuits in the embodiment.

Detailed ways

The present invention will be further described below through a specific preparation example in conjunction with the accompanying drawings.

In this embodiment, the integrated circuit prepared according to the total dose irradiation of NMOS devices according to the present invention mainly includes the following steps:

1) Formation of silicon dioxide and silicon nitride. As shown in Figure 3, a layer of silicon dioxide with a thickness of about 100 angstroms to 200 angstroms is grown by thermal oxidation on the silicon substrate 1 as a stress buffer layer 2 between the silicon nitride and the silicon substrate, and then used A layer of silicon nitride with a thickness of 1000 angstrom to 1500 angstrom is deposited as the barrier layer 3 by a low pressure chemical vapor deposition (LPCVD) method.

2) Trench lithography and etching. As shown in Figure 4, after the pattern shown is defined by photolithography, reactive ion etching (RIE) is used to etch trapezoidal trenches 4 between MOS devices, and the etching gas can be C1 ₂ , HBr , and O ₂ etc., the groove width is about 100 to 250 nanometers, the groove depth is about 300 nanometers to 500 nanometers, and the inclination angle of the trapezoidal side of the trapezoidal groove is about 75° to 89°.

3) Deposit silicon dioxide material for the first time. As shown in FIG. 5 , a first silicon dioxide layer 5 is deposited into the trench 4 etched in step 2 by using a high-density plasma CVD (HDPCVD) method. The ratio of etching and deposition, the so-called Etch/Depo ratio, is usually kept between 0.14 and 0.33. The thickness of the deposition is approximately 10 nm to 20 nm.

4) Deposit the sacrificial layer material. As shown in Figure 6, use the high-density plasma CVD (HDPCVD) method to deposit the p-type silicon layer 6 of the sacrificial layer material in the trench 4 etched in step 2. The p-type silicon layer is made of boron, aluminum, gallium , indium or thallium and other elements of the third main group, and the doping concentration is in the range of 5×10 ¹⁶ -1×10 ¹⁸ /cm ³ . The ratio of etching and deposition, the so-called Etch/Depo ratio, is usually kept between 0.14 and 0.33. The thickness of the deposition is approximately 10 nm to 80 nm.

5) Deposit silicon dioxide material for the second time. As shown in FIG. 7 , a second silicon dioxide layer 7 is deposited into the trench 4 etched in step 2 by high density plasma CVD (HDPCVD). The ratio of etching and deposition, the so-called Etch/Depo ratio, is usually kept between 0.14 and 0.33.

6) All materials deposited above the barrier layer 3 and the stress buffer layer are removed. As shown in FIG. 8, chemical mechanical polishing (CMP), concentrated phosphoric acid boiling, rinsing and other methods are used to remove various deposition materials and stress buffer layer materials to obtain the final isolation structure.

Claims (4)

1. the integrated circuit of a resisting NMOS element total dose radiation, said integrated circuit comprises nmos device, also can comprise the PMOS device; Pass through the trench isolations on the substrate between the said device; Be filled with trench fill material in the groove, it is characterized in that, with said nmos device adjacent grooves in; Embed a sacrificial material layer in the said trench fill material, said expendable material is the silicon of the 3rd major element of having mixed; The doping content of said expendable material is 5 * 10 ¹⁶To 1 * 10 ¹⁸/ cm ³Scope in, in the scope of 80 nanometers, and the distance of said sacrificial material layer and substrate is 10 nanometer to 20 nanometers to the thickness of said sacrificial material layer in 10 nanometers.

2. the integrated circuit of resisting NMOS element total dose radiation as claimed in claim 1 is characterized in that, said the 3rd major element comprises one or more in boron, aluminium, gallium, indium and the thallium.

3. like the integrated circuit of any described resisting NMOS element total dose radiation of claim 1-2, it is characterized in that said trench fill material is a silicon dioxide.

4. like the integrated circuit of any described resisting NMOS element total dose radiation of claim 1-2, it is characterized in that said backing material is a silicon.

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