CN1017007B - Electronic computer system with expansion card - Google Patents

Abstract

A PC system is composed of a main circuit; the main circuit is provided with a centre processor and a plurality of expansion slots; each expansion slot is suitable to accept a printing circuit card. The main circuit also comprises a memory, a thirty two bit, a relative control signal address bus and an input/ output circuit. The slots are coupled with the thirty two bit address bus; the bus is actually a NuBus. The slots comprise a special route identifying device which sends identifying signals to the slots of the PC system.

Description

Electronic computer system with expansion card

The present invention generally speaking relates to the electronic computer system that has some expansion slots on the motherboard (main circuit board), more particularly, relate to the personal electric computing machine that this class card slots and printed circuit board plug-in are housed, circuit board plug-in is suitable to be inserted this class and is connected in the card slots on the bus, and the part address storage space in the robot calculator is promptly specially left this card slots for and used.

Electronic computer system with expansion slot is a known technology.For example, Apple II e is the known personal electric computing machine with expansion slot, and this robot calculator is provided with and specially leaves the storage space that this card slots is used for.But when visiting the storer of plug-in unit in the sort of robot calculator is not from providing the address to start with, but choose a certain particular pin (together with the address) in the card slots earlier, this particular pin is told the package card in the card slots, and the address that microprocessor will be visited is somewhere in the storer of peripheral plug-in unit special use.In addition, these systems leave the storage space less (for example 16 bytes or 256 bytes) that all plug-in units are used for.In other words, address itself is not independent use usually, and when the address space of indicating plug-in unit is just accessed.There is the reference of the general performance of various relevant these electron-like computer systems can supply those skilled in the art that scholar's reference.For example " Apple II e reference manual ", Apple robot calculator (1981); " from the chip to the system: microprocessor is crossed the threshold ", Rodnay, Zaks, Sybex company limited, 1981; " microelectronic computer is crossed the threshold " of people such as Adam Osborne work, 1975; " introduction of Apple II circuit ", Winstur Gayler work Howard W.Sauis company limited publishes (1983).

The present invention more particularly, relates to the electronic computer system that the system bus of NuBus technical manual is followed in employing in fact.The NuBus technical manual has stipulated to have usually the relevant agreement (for example logic, electric and physical criterion) and the universal standard of synchronous (10 megahertz) many host buses of multipath conversion of rational arbitration function.NuBus originates from Massachusetts Institute Technology, later on through revision, is published at present in some publication of Texas, USA Instr Ltd. (comprising publication 2242825-0001 of Texas Instr Ltd. and 2537171-0001).A council of IEEE (IEEE) has proposed the technical manual of some system buss as ieee standard recently, this system bus comes down to the NuBus bus, although this technical manual is to revise out from the technical manual of Texas Instr Ltd. issue.The bus that IEEE proposed is named as IEEE 1196 buses.The application's book has been enclosed the copy (2.0 version) of IEEE 1196 bussing technique preliminary specifications, only for being familiar with those skilled in the art's reference.IEEE 1196 buses come down to original described NuBus bus in the publication of Texas Instr Ltd..

In the NuBus system, there is one can be coupled to and to produce 2 ³²The CPU(CPU (central processing unit) of individual different addresses) 32 bit address buses, thereby actual memory address space has 4 GB.Adopt the robot calculator of NuBus architecture, its the simplest form substantially be that a main circuit board with some card slots is arranged, have microprocessor, storer with other usually the plug-in unit (being called module sometimes) of the circuit relevant with microelectronic computer promptly insert in this card slots.In fact, each plug-in unit itself can be also to be connected to the associated microelectronic computer of other plug-in unit in the card slots on the NuBus by NuBus and other.For example, a NuBus system can comprise such plug-in unit, and this plug-in unit has a CPU(CPU (central processing unit)) microprocessor, a Memory Management Unit, some get the plug-in unit of the storer of random-access memory (ram) and ROM (read-only memory) (ROM) form; Also have bus on the plug-in unit, this bus makes the microprocessor on the plug-in unit can read ROM and the RAM sense data from plug-in unit on the plug-in unit and write data toward this RAM.In addition, input and output (I/O) circuit also can be housed on the plug-in unit, and this circuit can be got in touch plug-in unit by the remainder (comprising peripherals and other peripherals such as disc driver, printer, display device) of each terminal and system on the plug-in unit.Plug-in unit generally has one some electric terminals that are the pin form are housed, in order to card slots in supporting terminal form and be electrically connected.This plug-in unit is owing to have a microprocessor, thereby can make NuBus take to some business by handling some signal, and receives information by the NuBus on the main circuit board.Therefore this plug-in unit can write the storer (business) that is positioned on other plug-in unit with information by NuBus, and reads this information (another business) by NuBus.

In this NuBus system, each card slots all has special-purpose storer.In this NuBus system, card slots can reach 16, and they are configured in 1/16 storage space on whole 4 GB NuBus address space tops.The 16 storage space in this top is 256 megabyte storage spaces, this storage space is divided into 16 districts that are made up of 16 megabyte, 16 districts then are mapped in each groove of 16 possible NuBus plug-in units according to the card slots identifier, this identifier just produces particular number in each card slots, make plug-in unit in this card slots can " read " groove number that this specific identifier is determined the card slots that this plug-in unit inserted.These generally can be referring to the 30th page to 32 pages of IEEE 1196 bussing technique preliminary specifications.Like this, " the card slots space " of each plug-in unit is 16 megabyte.In common NuBus system, plug-in unit on can make (the plug-in unit place) groove specific number (the using hexadecimal representation) device consistent [when the highest effective hexadecimal digit (MSHD) of this address during] for $F with time the highest effective hexadecimal digit (inferior MSHD) of address on appearing at the NuBus bus, be for " card slots space " special use of this plug-in unit.Therefore, when this device is identified and to be identified then whether groove number (identifier of groove) is consistent with inferior MSHD by MSHD Deng Yu $F; If consistent, this device is just permitted this plug-in unit and is accepted the interview.Certainly, card slots is actual carries out with scale-of-two when comparing, but for ease of for the purpose of the explanation, comparison procedure is regarded as by hexadecimal then more easy.

This NuBus system has great dirigibility, because most of memory address space is not special-purpose.In addition, the special-purpose space of very big (16 megabyte) of it seems of each groove (slot space) has sizable memory data output (" data " speech comprises computer programs) here.But dirigibility too conference encourages incompatibility between the plug-in unit can be used on the same mother board.In other words, this dirigibility make we may design a kind of for most of address space left space special use in the NuBus system plug-in unit, this plug-in unit can use a part of same memory space with the plug-in unit contention of another exploitation.Certainly, overlapping for preventing storage space, can adopt switch and leap connection cable to wait configuration-system.But this solution is trouble in many aspects, comprising the tendency that the beginner is feared that they had.Concerning the beginner, they prefer the sort of as long as plug-in unit is inserted the electronic computer system that can need not to worry about in the card slots.

The method that the present invention addresses these problems is that 1/16 of whole memory address space is automatically assigned in each card slots in the NuBus system.Therefore an object of the present invention is to provide a kind of like this system, this system oneself disposes oneself, and still has certain dirigibility, but its dirigibility is unlikely so make troubles to the user.Another object of the present invention provides a kind of such main circuit board (motherboard), and this main circuit board has some card slots that more storage space thereby the automatic computing power of raising robot calculator are provided for each plug-in unit.Another object of the present invention provides this printed circuit board plug-in of a kind of like this edge receptacle (module) can dispose their storage space automatically, and increases to some extent for the storage space of each plug-in unit special use.

The present invention relates to a kind of some electronic computer systems that are coupled to the expansion slot of a NuBus bus that have, storer on the wherein each plug-in unit (module) is suitable for each expansion slot and the storage space of reservation increases to some extent, wherein the reservation to the storer that increased realizes by adopting the specific identification line unit, and this specific identification line unit provides the particular number of this card slots of identification number for any plug-in unit in this card slots by signal specific.The invention provides a kind of plug-in unit with decoding device in addition, this decoding device is to be coupled for the signal specific that receives this specific identification line unit and provided.Decoding device upward the address of appearance is compared particular number and the NuBus that signal specific provided.Result relatively keeps the storage space of 256 megabyte to this plug-in unit special use in a certain card slots, and wherein the scope of storage space is $ X0000000 to $ XFFF FFFF, and card slots number is X.

Decoding device compares the highest effective hexadecimal digit that goes out current address on this specific number and the NuBus bus, whether equals the highest effective hexadecimal digit in the address to determine specific number with hexadecimal representation.If the result that decoding device is identified is equal, then it is just according to any storer on the address start plug-in unit that occurs on the NuBus bus.Yes carries out with scale-of-two for comparison procedure, but for ease of for the purpose of the explanation, comparison procedure regard as by sexadecimal carry out then more easy.

Fig. 1 is in the block scheme of general electronic computer system of a most preferred embodiment of the present invention, wherein has 6 card slots to be coupled on the NuBus bus 10.

Fig. 2 is the actual address storage space figure of one embodiment of the invention.

Fig. 3 is an actual address storage space figure, shows the memory allocation situation of a most preferred embodiment of the present invention.

Fig. 4 shows a printed circuit board plug-in of the present invention, in order to use with motherboard of the present invention.

Fig. 5 is the block scheme of the NuBus interface that a microprocessor on the main circuit board joins of coexisting.

Fig. 6 is the block scheme with the various NuBus clocks of NuBus bus adapted.

Fig. 7 has shown the phase relation of various NuBus clocks.

Fig. 8 is the block scheme of the interface between each NuBus plug-in unit in motherboard processor (CPU 1) and the NuBus card slots.

Fig. 9 is a block scheme of receiving the NuBus of motherboard processor bus interface.

Figure 10 shows the distribution condition of a certain address storage space on the plug-in unit in the NuBus card slots, and wherein this plug-in unit addresses the ROM part that visits storer 2 by the top to card slots 0 little space.

Figure 11 is the skeleton view of electronic computer system main circuit board of the present invention (motherboard).

Figure 12 is the synoptic diagram that is used for the decoding device example on the plug-in unit of the present invention.

Figure 13 is the block scheme of electronic computer system of the present invention.

Figure 14 is the synoptic diagram of the printed circuit board plug-in of preparation and main circuit board adapted of the present invention.

For fullying understand content of the present invention, introduce in the following explanation and showed multiple detail of the present invention, such as circuit, block scheme, storage unit and logical value or the like.But be familiar with the present invention, in other cases,,, no longer describe in detail here some known element and subsystem for fear of short the present invention's indigestion that becomes that so makes.

Fig. 1 is the general construction synoptic diagram of electronic computer system of the present invention.There is a CPU (central processing unit) 1(CPU 1 in this system), CPU 1 is a microprocessor normally, and it is coupled to storer 2, so that allow the CPU 1 can be from storer 2 reading of data, and with in the writing data into memory 2.CPU 1 is coupled to storer 2, provides the address of storage unit via processor bus 5, and 5 of processor bus play address bus, and the address is offered storer 2 from CPU 1.On storer 2 is provided to processor bus 6 as BDB Bi-directional Data Bus with data (programmed instruction that comprises robot calculator) from the storage unit of being visited.CPU 1 can write toward storer 2 like this: provide an address according to the access signal on the processor bus 5 on the processor bus 5 of the storage unit in reference-to storage 2 earlier, provide data to write on storer 2 on the processor bus 6 storer 2 then.As everyone knows, can take away by processor bus 5 from these signals of some signal of CPU 1) represent that CPU 1 is writing on storer 2, or reading from storer 2.Processor bus 5 is 32 buses, thereby has 32 address lines that address signal is provided.It is the control signal reading or write at (toward storer) at (from storer) [for example R/W(read/write) signal and chip select signal] and other relevant control signal that processor bus 5 also has some CPU of showing 1, the control signal and the timing signal (for example column address gating signal and rwo address strobe signals) that comprise the special microprocessor of present use, these all are known in the prior art, thereby no longer describe in detail here.Processor bus 6 has one 32 bit data bus (thereby having 32 data circuits that data-signal is provided) and some employed relevant controlling signals that generally comprises the special microprocessor of data bus at present, and this is well known in the prior art (for example writing enabling signal etc.).CPU 1 of the present invention has a generating device of the address, in order to produce 2 ³²Individually 0,000 0000 represent hexadecimal notation to unit FFFF FFFF(symbol from the unit) different addresses; This generating device of the address generally is to be coupled on the processor bus 5, and is the part of CPU 1, for example 68020 microprocessor (Motorola) and 80386 microprocessor (Intel).

Electronic computer system also comprises the input and output circuit, this circuit, as of the prior art known, be to receive data and the interface of data is provided for each peripherals from each peripherals as robot calculator.The details of this circuit is well-known.I/O (I/O) circuit 7 is coupled on CPU 1 and the storer 2 via interconnect bus 13 and processor bus 6 and processor bus 3.I/O circuit 7 can in order to visit such as disc driver, printer, modulator-demodular unit, video display peripherals and with other peripherals of electronic computer system adapted.As shown in Figure 1, disc driver 8 is to be coupled on the I/O circuit 7 with the interconnect bus shown between I/O circuit 7 and the disc driver 8.I/O circuit 7 is coupled on the storer 2 by processor bus 6, data is provided and receives data from storer 2 with from CPU 1 to storer 2; Each peripherals that bus 3 can visit CPU 1 to be connected to I/O circuit 7, and make the I/O circuit 7 can reference-to storage 2.I/O circuit 7 also is coupled to CPU upward so that receive data and control signal from CPU 1.Like this, peripherals (for example disc driver 8) just can with CPU 1 and storer 2 swap datas (comprising program), also can with any plug-in unit and the coupling NuBus 10 card slots (card slots 29 that for example in electronic computer system shown in Figure 1, has Te Dinghao $9) swap data.

In general business, CPU 1 provides an address on bus 5.The storer 2 that is coupled on the bus 5 receives this signal, provides a value according to the unit of visiting by the address that is provided on the bus 5 on bus 6 then.Data from storer 2 are to offer CPU 1 on processor bus 6.Storer 2 generally comprises RAM, also can comprise the ROM(ROM (read-only memory)).Processor bus 6 is to be coupled on the NuBus 10 by interface 9 and interconnect bus 11 and 12.

Electronic computer system shown in Fig. 1 has six " expansion " card slots, in order to receive printed circuit board plug-in and to be electrically connected respectively with circuit on the plug-in unit (for example plug-in unit 50a among the plug-in unit among Fig. 4 50 and Figure 14).This system is equipped with card slots 29,30,31,32,33 and 34, and each all is coupled on another system bus-NuBus 10 on the motherboard.Therefore, card slots 29 is coupled on the NuBus 10 via interconnect bus 19.Each card slots has supporting terminal, and each terminal is coupled on the signal specific circuit of NuBus bus 10 by interconnect bus; Like this, each card slots 29,30,31,32,33 and 34 has the terminal of assembly cover, and these terminals and NuBus bus 10 are electrically connected.A plug-in unit of the present invention has terminal 51, in order to card slots in corresponding supporting terminal be electrically connected, thereby make each element on the plug-in unit can receive all signals of NuBus bus 10.

Plug-in unit in 29,30,31,32,33 or 34 one of them card slots can be got in touch via NuBus interface 9 and storer 2, and 1 of CPU can get in touch via NuBus interface 9 and any storer on the plug-in unit, and these are about to speak of below.For example, NuBus interface 9 is that the storer on the plug-in unit and is provided to this address on the NuBus 10 by interconnect bus 11 from CPU 1 receiver address on bus 25 in a certain card slots; Interface 9 is by 25 in order to the processor bus 5(between any CPU that (can make its control NuBus bus read or be written on this storer from the storer on the plug-in unit) on heat CPU 1 of portion and the plug-in unit) and 6, and make this double bus co-ordination.Equally, interface 9 CPU(that is storer 2 from a certain plug-in unit " the NuBus device) by NuBus 10 and interconnect bus 11 receiver addresses; With each processor bus synchronous, and judgement (the generation address) NuBus device can (by address signal is delivered on the processor address bus 5 via bus 25) be controlled after all processor bus, and interface 9 offers address signal the bus 25 that is connected on the storer 2.Storer 2 responses are from the data of accessed unit, and these data are placed on the bus 6 that is coupled to interface 9, via NuBus 10 these data are offered the NuBus device by interface 9.

Electronic computer system shown in Fig. 1 is utilized the expansion bus of NuBus bus as an electronic computer system on the main circuit board, and wherein CPU 1 processor bus on this main circuit board not necessarily must be the NuBus bus.Therefore all card slots that are coupled on the NuBus 10 have the ability of expanding system, and system can be set up, for example, and annex memory or addition processing machine transplanting of rice part.But also can being applied to, the present invention do not have the NuBus of CPU and storer architecture on the main circuit board.This system is about to speak of as shown in figure 13 below.

Figure 13 has shown that the present invention adopts the electronic computer system of NuBus bus 120 on main circuit board, and this main circuit board has some card slots, and each all is coupled on the NuBus bus 120.The main circuit board of this system (as shown in figure 13) can be installed NuBus bus 120 and 15 called after groove 130, groove 131 respectively ... card slots to groove 144.Each card slots is coupled on the NuBus bus 120 by interconnect bus; Therefore, groove 130 is coupled on the NuBus bus 120 by interconnect bus 150, and this interconnect bus generally includes all circuits of NuBus bus 120, comprises four circuits as the specific identification line unit in addition.These four circuits generally are loaded with binary value, and these binary values can be specified any number of from 0 to 15 together.Each card slots receives a certain specific identification line unit, different (specific) number is provided for each card slots by this device.In other words, the specific identification line unit of installing as the part of interconnect bus 150 is loaded with and equals 0 signal specific.Groove 144(Cao $E) has the specific identification line unit of installing as the part of interconnect bus 164, the value (signal specific) of Deng Yu $E is provided by interconnect bus 164.Should be noted that there be not the 16 card slots here, because the employing of NuBus standard is to be distributed in groove 0 to 15 little card slots space (respectively being 16 megabyte) uppermost 256 megabyte (shown in the district among Fig. 2 40).This can see clearlyer from Fig. 2, and Fig. 2 has shown the actual address storage space that resembles the sort of system shown in Figure 13.Each card slots of $0 to $E all has " the super space of 256 megabyte.Therefore, for example, groove 0 has the super space of-256 megabyte, and storage unit $ 0,000 0000 to $ 0FFF FFFF is this super space and keeps special-purpose.This space is total representing with numbering 41 in Fig. 2.In this system shown in Figure 13 and Fig. 2 a Cha Jiancao $0 is arranged, this groove has the storage space of a special use; But because many microprocessor are in 41(Cao $0 super space, district) in have storer more favourable, for simplicity, use usually and can not establish Cao $0 when of the present invention, do not stay special-purpose storage space 41 for any particular plug-in groove yet.Therefore, any plug-in unit in all the other each grooves (being Cao $1 to $E) can adopt the storer in the district 41.The number of card slots can be to be less than any number of 15 when certainly, enforcement was of the present invention.NuBus standard-required, each card slots of Ying Wei $0 to $E are reserved the space of 16 megabyte in master serial number is 40 256 megabyte districts; This district's scope is to unit $ FFFF FFFF from unit $ F000 0000.Adopt identification signal, for example four specific identification circuits when being assigned on each plug-in unit with all " little space " in the district 40.Each little space in the district 40 also is called " package space " in the NuBus standard.The address reference of getting $ FSiXX XXXX form belongs to the address space in the card slots space of plug-in unit among the groove Si.Referring to IEEE 1196 technical manuals (2.0 version) the 30-31 page or leaf of enclosing with this instructions.

Fig. 2 is the synoptic diagram of total actual address storage space of system shown in Figure 13.The main circuit board that NuBus 120 is housed is not provided with CPU or storer.System clock 170 on the main circuit board provides NuBus clock signal, and is coupled on the NuBus 120 via circuit 175.The power circuit of NuBus signal does not show among the figure, but self-evident.In addition, be understood that the main circuit board of the system shown in Figure 13 should comprise that other is not placed in the NuBus assembly on the plug-in unit, for example overtime circuit of NuBus etc.

Electronic computer system shown in Figure 13 generally comprises two printed circuit board plug-ins, and one of them plug-in unit inserts in the card slots, and another plug-in unit (second plug-in unit) inserts in another card slots.For the purpose of illustrating, suppose that first plug-in unit Cha Rucao $0(is a groove 130) in, second plug-in unit Cha Rucao $1(is groove 131) in.Fig. 4 and Figure 14 have shown the synoptic diagram that plug-in unit is total.These plug-in units comprise a printed circuit board plug-in 50 or 50a and plurality of terminals 51, and these terminals all are coupled on the various assemblies and signal line on plug-in unit 50 or the plug-in unit 50a.All terminals 51 are to stretch on printed circuit board (PCB) on the part of a jack in all card slots, this insert hole contain some supporting terminals in order to plug-in unit on respective terminal be electrically connected.The NuBus standard code physical criterion of interconnection line.The supporting terminal of in the card slots each all is coupled on the various circuits and element on the main circuit board; For example, a plurality of supporting terminal electrical couplings in the card slots is to NuBus bus signals circuit.These supporting terminals make each element on the plug-in unit can receive the various signals that appear on the NuBus bus 120, and a plug-in unit in the card slots can be got in touch via interconnect bus (for example interconnect bus 150 and 151) and the plug-in unit in another card slots by NuBus.

This example relates to Figure 13.First plug-in unit 50(hypothesis is in Cao $0) for example CPU shown in Fig. 4 61 of a CPU(arranged) and a storer (for example, RAM62 and the ROM62 that is coupled by the card bus that is configured on first card slots 50).CPU 61 and storer 62 are coupled on the system bus NuBus 120 by the terminal on the plug-in unit 50 51.The second plug-in unit 50a(among the Cao $1 sees Figure 14) comprise for example random access memory of storer 62(shown in Figure 14) but do not comprise CPU.This plug-in unit is called the subordinate plug-in unit, and it can not start to control to make to bus 120 and use.Second plug-in unit generally has a card bus 65, the same signal that this bus is included in most of on the NuBus 120 (if not all) can find.[this is called AD(31 in the IEEE1196 technical manual in 2.0 versions to the address of some NuBus 120 (and data) circuit ... 0), because these addresses and data are can multipath conversion on each identical circuit] be to be added on the decoding device 60.Bus 66 shown in Fig. 4 is loaded with whole addresses and data-signal, control signal and the electric power signal of NuBus usually.In this manual, 32 of NuBus address lines (also being as 32 data circuits on the NuBus) are though be NuBus signal AD(31 ... 0), also called after A31 to A0.In fact, the decoding device 60 of plug-in unit 50a makes that storer 62 on the second plug-in unit 50a can be on NuBus 120 when being in the address space of the second plug-in unit special use such as the address (this private address space is the address from unit $ 10000000 to unit $ 1FFF FFFF in the case) receives visit.When these addresses are in this special-purpose storage space the time, the chip of the storer 62 on the decoding device 60 drive plug 50a selects (CS) circuit (these circuits all are coupled on the circuit 64 from decoding device 60) thereby various RAM chips on this plug-in unit and rom chip show that they accept the interview, thus the storer 62 on the plug-in unit 50a among the visit Cha Jiancao $1.Like this, work as decoding device, select pin by means of chip, when storage chip was worked, the storer on the second plug-in unit 50a can be from receiver address on the system bus.

Like this, among the Cha Jiancao $0 this CPU of CPU(on first plug-in unit 50 have a generating device of the address in order to produce that reference-to storage uses 2 ³²Individual different address) all terminals by plug-in unit in the groove provide an address to NuBus 120.Some part of this address appears on the decoding device 60 on the second plug-in unit 50a.If this address be at $ 1,000 0000 to the scope of $ 1FFF FFFFF, then the storer on second plug-in unit can respond, and during suitable time-count cycle data is being provided on the NuBus 120.

Decoding device 60 on second plug-in unit among the Cao $1 of Figure 13 compares the specific number (this number is $1) of Cao $1 with the highest effective hexadecimal digit in address that appears on the system bus (NuBus 120), to determine when to equal with the specific number of hexadecimal representation the highest effective hexadecimal digit of address.When the sort of situation took place, decoding device made second memory to be visited that data are provided on the system bus.Therefore the super space of 256 megabyte " be to leave the second card slots special use among the Cao $1 for.Be about to below speak of, decoding device also plays the desired preservation 16 megabyte storage spaces of NuBus systems technology standard.

Be understood that that Cao $1 of Figure 13 is coupled to this groove provides on the specific identification line unit of signal specific, this signal is discerned certain specific number of this groove.Other groove each and every one also is (for example, groove 144 has the Te Dingxinhao $E of the specific number that is this groove) like this among Figure 13.In general, a specific identification line unit is made up of four leads that are loaded with binary value.Concerning Cao $1, have only one can be loaded with binary value 1 in four circuits, all other circuits then are loaded with binary value 0, and wherein 1 is minimum effective binary digit.Like this, the specific identification line unit provides signal specific 1 can for Cao $1, discerns this groove thus and whether has Te Dinghao $1.Self-evident, also can adopt other to discern the method for specific number, an identifier that can produce the specific number of this groove by mathematical conversion for example is provided.Not so also can provide a lead as the specific identification line unit with multilevel logic.

Referring now to Fig. 1,3,11 and 12, introduces a most preferred embodiment of the present invention that adopts six (6) individual card slots.Figure 11 is that main circuit board 14(also is called motherboard) skeleton view, this main circuit board has a CPU 1, comprises the storer 2 of ROM (read-only memory) (ROM), I/O circuit 36 and is numbered six card slots of 29 to 34.Motherboard 14 also has a coupling arrangement, in order to be connected on the keyboard, as shown in Figure 11.As for any other personal electric computer system, motherboard 14 also can be equipped with various other circuits, for example power supply, latch and circuits such as impact damper, driver also can be installed the general element relevant with the personal electric computer system known in video line, clock line and other prior art.Each card slots 29,30,31,32,33 and 34 have with the plug-in unit that inserts in the card slots on all terminals 51 some supporting terminals that are electrically connected are arranged.Each card slots 29-34 according to the NuBus standard, receives all NuBus signals in NuBus 10 basically, as shown in fig. 1.Each card slots receives the NuBus signal by interconnect bus 19,20,21,22,23 and 24 as shown in fig. 1.These pair of connecting wires card slots all are general (identical), and the specific identification line unit of each card slots being discerned the specific number that each groove has then makes an exception.

In this specific embodiments, four leads (circuit) that are loaded with binary value give card slots 29 1 Te Dinghao $9, and are as shown in the table.Though these four leads be owing to can provide on the spot near Cha Jiancao $9, thereby in fact need not to occur on the circuit of whole length in NuBus 10, but the part of interconnect bus 19. Concerning card slots 30,31,32,33 and 34 also is like this.Ground regional address shown in the table 1 certainly, is the specific number of each card slots.

Table 1

The NuBus card slots of Fig. 1 system number

Among Fig. 1

Card slots number ground regional address GA3 GA2 GA1 GA0 binary value

29 $9 ground connection open circuit open circuit ground connection 1001

30 $A ground connection open circuit ground connection open circuit 1010

31 $B ground connection open circuit ground connection ground connection 1011

32 $C ground connection ground connection open circuit open circuit 1100

33 $D ground connection ground connection open circuit ground connection 1101

34 $E ground connection ground connection ground connection open circuit 1110

(binary value is according to transducer the NuBus signal to be carried out the shown value of logical conversion)

Each circuit in the specific identification line unit of each card slots is to be coupled to attempt each circuit is drawn high on the circuit of power supply signal+5 volt.This circuit according to the NuBus standard, can comprise a loading resistor usually on each specific identification circuit, this resistor can number draw high open circuit substantially+and 5 volts, side by side signal can remain on earth potential haply.Circuit shown in Figure 12 (following being about to spoken of) supposes that open circuit signaling (before they are added to decoding device 60) draws high+5 volts mains voltage level haply, and NuBus signal GA3 ... GA0 signal and address (A31 ... A0) signal) carry out logical conversion by transducer.In addition, the NuBus signal on the NuBus bus 10 should (by the transducer on each plug-in unit) carry out logical conversion before the circuit that is added on the NuBus plug-in unit (for example plug-in unit 50 and plug-in unit 50a); Equally, also should (by a transducer) carry out logical conversion from the signal that is added on each plug-in unit on the NuBus bus 10.In general, these transducers are included on each plug-in unit in the employed input and output impact damper.At the interface 9 as the interface between NuBus bus 10 and the motherboard circuit (being CPU 1, storer 2, I/D circuit 7, various bus 5,6,25 etc.), the signal of turnover NuBus bus 10 is in addition conversion all.Therefore, for example, the GA3 NuBus signal (GND) that is added to each card slots is transformed into logical one on plug-in unit, be added to the circuit in the decoding device 60 shown in Figure 12 then.These conversion processes are that the present technique field is known.Certainly, as if CPU 1 and about circuit and bus (for example bus 5,6,25) employing NuBus system, standard and signal, then just need not to carry out conversion at interface 9.

As can be seen, the specific number of groove 30 is with Wei $A from present embodiment (shown in Fig. 1,11 and 3); The specific number of groove 31 is with Wei $B; The specific number of groove 32 in electronic computer system is with Wei $C; The specific number of groove 33 is with Wei $D, and the specific number of groove 34 is then with Wei $E.In the NuBus of IEEE technical manual draft (being called IEEENuBus 1196 bussing technique standards), the specific identification line unit is called as the card slots recognition device, and with symbol " ID(3 ... 0) " expression, this symbology ground regional address GA3, GA2, GA1 and GA0.As pointed in the 6th page of this IEEE technical manual, these four circuits are not as bus, but compile with binary code, with the position of indication plug unit in robot calculator in each position.

According to the present invention, the electronic computer system shown in Fig. 1 draws the actual address storage space shown in Fig. 3, wherein six card slots each and every one all it has " the super space " of containing 256 megabyte dedicated memory space.Therefore, for example, Cao $9 has from the special-purpose super space of $ 9,000 0000 beginnings in unit up to unit $ 9FFF FFFF end.In addition, Cao $9 also can have a little space (" card slots space ") and kept by the NuBus technical manual; According to this technical manual, Cao $9 can have the special-purpose little space for its reservation, begins to finish to unit $ F9FF FFFF from unit $ F900 0000.As can see from Figure 3, the little space of using for various card slots is contained in 256 megabyte districts 42.There is the NuBus memory address space 43 of a non-special use there, and other expansion slots that can be added in the system that designs by the present invention can be used non-special-purpose NuBus memory address space.The nethermost 256 megabyte storage spaces of called after 45 are local address spaces of CPU 1, give its specific number specific number $0, on it is plug-in unit among the Zai $0.CPU 1 can design to such an extent that make it " occupy " other card slots, in other words, can give its Te Dinghao $1,2 and 3, thereby the same with the specific embodiments shown in Fig. 3, and whole district 44 all leaves its special use for; In fact, motherboard has become 4 card slots ($0,1,2 and 3) in a plug-in unit.If the deviser wants super space Cha Jiancao $0 separated to come for CPU 1 fully to use (promptly preventing NuBus visit this super Kong Jian $0), then NuBus interface 9 should be designed to such an extent that be enough to prevent this visit but allow by means of repetition some in super Kong Jian $1 Huo $2 Huo $3 and call the data of visiting in super spaces.Therefore the NuBus address on super Kong Jian $0 NuBus 10 can be decoded on the corresponding same unit in the super space 51 (being $ 0XXX XXXX to $ 1XXX XXXX).In this case, (in real actual Cha Jiancao $9 to $E) NuBus plug-in unit can design to such an extent that comprise that the super Kong Jian $1,2 or 3 of the another name of the data that are stored in super Kong Jian $0 visits the super space of Cha Jiancao $0 by visiting those.Address space ($ 0,000 0000 to $ 1,000 0000) also is to work on plug-in unit fully and do not have the local address storage space of some plug-in units of NuBus business; In other words, resemble a plug-in unit with a CPU shown in Figure 4, if this CPU does not cause the NuBus business, can be with regard to the local RAM on its plug-in unit in this same address space 45 of accessing.This layout of using for pure local service on the plug-in unit is to carry out with the address decoder on the plug-in unit, and this is a known technology in the art.

This specific embodiments shown in Fig. 1 also is that I/O circuit and ROM (read-only memory) (ROM) (this is the part of the storer 2 shown in Fig. 3) leave special-purpose storage space in addition.Particularly from $ 4,000 0000 to unit $ 4FFF FFFF, all leave address storage space special use for.In addition, the memory address space of leaving I/O operation and circuit special use for is to unit $ 5FFF FFFF from unit $ 5,000 0000.One embodiment of the present of invention shown in Figure 3, I/O wherein and ROM storage space are to be positioned at $ 4,000 0000 to $ 5FFF FFFF.Like this, by means of CPU 1 or second CPU 61, by visiting the information that those just can visit ROM or I/O from all storage unit of $ 4,000 0000 to $ 5FFF FFFF.Figure 10 is an alternative embodiment of the invention, and wherein motherboard I/O and ROM are to be placed in $ F000 0000 to $ FOFF FFFF with respect to the storage space of NuBus plug-in unit.In this embodiment, can be by the storage space of the motherboard I/O information of (in the NuBus card slots) NuBus plug-in unit visit and (on the motherboard) system ROM, when still addressable district $ 4,000 0000 to the $ 5FFF FFFF of CPU 1, be to be restricted to 16 megabyte; But can also make the system that enough use for ROM and I/O in many wherein these spaces that are confined to 16 megabyte.Therefore, concerning a NuBus plug-in unit, thereby it can impel visit to this ROM to visit ROM as the part of the storer on the motherboard 2 by the address that $ F000 0000 to $ FOFF FFFF scope is provided on the NuBus bus.This is to carry out in known mode with interface 9, and promptly interface 9 will be from the NuBus bus at the address decoder in FF000 0000 to FFFF district ROM and I/O district (4,000 0000 to the 5FFF FFFF) to motherboard.CPU 1 not necessarily leave no choice but similarly be tied can not, therefore can seek motherboard ROM or I/O storer by the district of visit $ 4,000 0000 to $ 5FFF FFFF scopes; In other words, CPU 1a can have other be not NuBus plug-in unit (these plug-in units are being restricted) employed (as the part of storer 2) ROM or I/O storer aspect the visit of main system ROM on the motherboard and I/O.This embodiment of the present invention (as shown in figure 10) meets the regulation that the NuBus standard-required is placed in structure ROM 16 megabyte (card slots) top of space; For example, the ROM space of Cao $0 is the top that is placed in space $ F000 0000 to $ FOFF FFFF.

Referring now to Fig. 4,12 and 14, introduces plug-in unit of the present invention.Fig. 4 has shown a plug-in unit of the present invention, and this plug-in unit inserts in the electronic computer system of the present invention it by one of them card slots (for example groove 29) that is inserted into all card slots of system.This plug-in unit has a printed circuit board (PCB) 50, disposes the electric installation that is various circuit forms on the circuit board, for example card slots bus 65 and interconnect bus 67,68 and 69 etc.Equally, Figure 14 has shown a plug-in unit 50a of the present invention, it is the same with the plug-in unit shown in Fig. 4 basically, just it does not have the common CPU 61 that can make 50 pairs of NuBus buses 10 of plug-in unit start to control making usefulness, and the plug-in unit 50a shown in Figure 14 can only be a subordinate plug-in unit usually, and can not control NuBus bus 10, can not cause the NuBus business.Plug-in unit 50 and 50a have plurality of terminals 51, and each the supporting terminal in these terminals and each card slots is electrically connected, thereby the various elements on each plug-in unit are coupled to the various signals that appear on the main circuit board 14.All (turnover NuBus's) NuBus signals are all cushioned and conversion by all impact dampers 59 on the plug-in unit.Therefore, for example, interconnect bus 63 is connected to decoding device 60 with the address lines A31 to A24 of NuBus 10.Bus 63 also comprises power supply and specific identification line unit, and this has four bars circuit GA3, GA2, GA1 and GA0 in the present embodiment, and they all are coupled to terminal 52,53,54 and 55 respectively.That is, signal GA3 is added on the terminal 52 by a supporting terminal that is arranged in the card slots that receives plug-in unit 50.Equally, signal GA2 is added on the terminal 53; Signal GA1 is added on the terminal 54; GA0 then is added on the terminal 55.These terminals 52,53,54 and 55 all are coupled to these four signals (after changing) are added on the wire installation on the input end 82 of decoding device 60, as shown in figure 12.

The signal that occurs in all card slots of this specific embodiments is some NuBus signals, and they are listed in the following table 2.Certainly, NuBus 10 comprises one 32 bit address buses, this address bus is read cycle period at first address of wanting the storage unit of visiting is provided, and second effect of reading super data bus of cycle period, and receives the data that are stored in this storage unit.During writing toward storer, NuBus 10 carries the element address that preparation writes in first cycle period on its 32 bit address bus, and in second cycle period, NuBus 10 provides the data of preparing to be written in the unit of being visited in first circulation.NuBus 10 comes down to an IEEE1196 bus.All plug-in units receive and use the major part of these signals usually, although they use these signals to depend on indivedual needs of plug-in unit and designer's target.

Table 2

NuBus card slots signal instruction

Signal instruction

+ 5 volts of card slots power supplys.5 volts

+ 12 volts of card slots power supplys.12 volts

-12 volts of card slots power supplys.-12 volts

Need not in-5.2 volts of present embodiments.All-5.2 vor signals are all being inserted

Link together on the part groove.

GND(ground)+5 volt ,+12 volts and-12 volts of power supply loopbacks

The open collector signal resets.By CPU 1 or by installing

The push-button reset switch when the rising power supply, determine.With 1

Kilo-ohm resistor draws high+and 5 volts.The groove plug-in unit is with on the plug-in unit

Circuit should adopt this signal when resetting.

SPV card slots parity is effective.If plug-in unit provides strange at 1SP

Idol is just determined this signal.Oblique line " 1 " expression letter

Number when reducing, trigger its target.

SP card slots parity.If determine/SPV, then/AD0-/AD

31 are in the odd number idol.

The professional modifier of TM0-TMI.In " starting " cyclic process, make

With, to represent professional scale.In the ACK cyclic process

The middle use is with the expression completion status.

The NuBus address/data position of A0-A31 0 to 31.It is " starting

" use in the cyclic process, with presentation address.At ACK

Use in the cyclic process with the expression data.The NuBus technology

Standard claims that these signals are AD0-AD31 or AD(31

0), because 32 same circuits in first cyclic process

Carry in second cyclic process then middle carrying address

Data.

The warning of PFW power fail.220 watts of resistors are opened collector

The road signal draws high+and 5 volts.When signal is drawn high,

The source is connected.When this signal was dragged down, power supply was cut off

。Before losing efficacy, AC power sends 2 milliseconds power supply

During failure warning, power supply itself can drag down this signal.

According to IEEE 1196 standards, this point is not essential

.

The arbitration position of ARB0-ARB3 0 to 3.Advise according to IEEE 1196 technology

The open collector signal that model terminates in the card slots (is seen

, for example, the table 6 of this technical manual).In order to basis

The NuBus technical manual between each card slots to bus

Control is arbitrated.

The regional address bit of GA0-GA3 0 to 3.The hard coded two of card slots

The system address.Each pin is connected to GND or open-circuit position

(or+5 volts and do not open a way).

Starting this signal certainly provides an address to be illustrated on the A0-A31

。Also in order to the arbitration of starting to total line traffic control situation.

ACK confirms.In order to expression " starting " round-robin is confirmed.

The RQST request.Certainly this signal is with the control of request to bus.

The non-main request of NMRQ.According to IEEE 1196 technical manuals eventually

An open collector signal that ends in card slots (is seen

, for example, the table 6 of this technical manual).

Plug-in unit sends to make with this signal and receives the signal that interrupts.

CLK NuBus clock.Coordinate business non-right on the NuBus

Claim 10 megahertz clocks.

Those of ordinary skill is in the art all known the structure and the purposes of decoding device 60.This is mainly concerned with a kind of application that has the comparison means of a starting device, wherein comparer with the NuBus address with appear at signal on the specific circuit recognition device and compare and determine when the address is in the storage space of storer 62 special uses of plug-in unit.But the purposes one of decoding device in standard of the present invention is new things in order to keep the storage space of 256 megabyte, a kind of decoding device that a comparison means and a starting device simply are housed of therefore will having a talk below.Develop other decoding device that can fulfil function of the present invention and be ordinary skill in the art.

In the general business between plug-in unit 50a and CPU 1, storer 62 is coupled to (following being about to spoken of) on the CPU 1 selectively by NuBus 10 and relevant interface 9 thereof, so as on NuBus 10 receiver address and data (maybe ought write fashionable reception data) are provided.CPU 1 comprises a generating device of the address, in order to produce from the unit 2 different addresses of 0,000 0000 to unit FFFF FFFFF.Export from CPU 1 by processor bus 5 address (this address is 32 bit wides) from CPU 1.Then, 32 bit address enter in the interconnect bus 25, appear at then on the interface 9, determine that by interface 9 whether this address is in the NuBus address space of $ 6,000 0000 beginnings.Below the address, storer 2 and I/O circuit can be by CPU 1 visits at this.More than the address, accessed then is at the super space of plug-in unit or the storer in the little space at this address and this.Interface 9 determines whether choosing a certain NuBus address, and after CPU 1 being added to the address signal synchronization on the NuBus and determining the NuBus entitlement favourable to LPU1, the address is appeared on the NuBus 10 by interconnect bus 11.For the purpose of explanation, we suppose that the plug-in unit 50a shown in Figure 14 has among the Cao $9 of specific number in Zai $9 system.Decoding device 60 is by NuBus 10 receiver address signals, and determines that these addresses are whether for the storage space use of this plug-in unit.

Decoding device 60 has a comparison means 70, and the card slots that the highest effective hexadecimal digit that comparison means 70 will (be used to read and write) address and the plug-in unit with decoding device 60 insert the place compares with the specific number of hexadecimal representation.Decoding device also has a control and a clock signal device 71, and device 71 comprises NuBus clock and " starting " and " affirmation " signal again.Decoding device also can comprise known thereby element that do not illustrate in a driver, the prior art here, this element provides the electric current that is enough to the output of decoding device is driven into the target that can influence this output, and this target is the chip of storer 62 and selects (CS) circuit and pin.This also is the part of decoding device 60 for comparison means 73() address is compared, whether accept the interview so that determine the little space of card slots.Determining address on the present NuBus 10 when one of them comparison means (70 or 73) is in the super space of plug-in unit or little space the time, and this specific comparison means is just selected (CS) circuit together with the chip that control device 71 startings are connected to storer 62.Chip is selected (being called the chip initiating signal sometimes) circuit, and is well-known, is in order to represent that to storer (for example storer 62) it is accept the interview (so that read or write).All be coupled on the circuit 64 on the line of chip select road, as shown in Fig. 4 and Figure 14.

The highest effective binary digit A3 that the comparison means 70 of decoding device 60 has four exclusive-OR gates (" XOR ") (for example exclusive-OR gate 76) will (appear on the input end 92) GA3 signal and 32 bit address circuits compares, and this highest effective binary digit is that input is on the input end 91 of exclusive-OR gate 76.Self-evident, as the front had been said, the NuBus signal in the decoding device 60 all (on the plug-in unit of impact damper 59) through conversion; Therefore, GA3 ... GA0, address signal A31 ... A24 and " starting ", " affirmation " and " clock " these signals that use in decoding device all are the process conversion.For example, " starting " signal shown in Figure 12 is NuBus " starting " signal of conversion.If the highest effective binary digit of address equals signal GA3, then logical zero can appear on the output terminal of exclusive-OR gate 76, and this output is sent on the four-input terminal exclusive-OR gate 77 via circuit 93.Address signal A31 to A28 and some signal (for example electric power signal and earth signal) all are added to comparison means 70 on input end 83.These signals are provided on the various exclusive-OR gates of comparison means 70, as shown in figure 12 then.Each exclusive-OR gate in the comparison means 70, its output have only just be in logical zero when two outputs of removing a certain specific exclusive-OR gate equate fully.Like this, each exclusive-OR gate be with as the specific identification line unit wherein one be loaded with the circuit of binary digit and a wherein circuit on four most significant address line roads, aspect binary digit, compare.As can be seen, when a certain specific number with hexadecimal representation equals the highest effective hexadecimal digit of address, each exclusive-OR gate can produce logical zero at its output terminal, impels the output terminal of exclusive-OR gate 77 also to become logical zero, thereby makes node 70a become logical zero.Node 70a is coupled to the output terminal of exclusive-OR gate 77, also is coupled to one of them input end of NOT-AND gate 90, and 90 of NOT-AND gates are the parts of control device 71.The output terminal of comparison means 73 is coupled on the node 73a in the control device 71, also is coupled on another input end of NOT-AND gate 90.When a certain address is in the slot space at plug-in unit the time, the output terminal of comparison means 73 can be in logical zero, and the output terminal of node 78(NOT-AND gate 90) can be in logical one.When a certain address is in the super space in card slots the time, the output terminal of comparison means 70 can be in logical zero, the output terminal of node 78(NOT-AND gate 90) can be in logical one.When address not in the little space in card slots, in the time of also not in the super space of plug-in unit, node 78 can be in logical zero (because node 70a and node 73a each can be in logical one).When address (in " starting " process) when being effective, can be logical one at the signal of AND gate 87 endpiece, and meeting (in next NuBus time clock) be clocked on the output terminal Q of trigger 80, logical one is appeared on the node 79.Therefore, be effectively and be in the space (little space or super space) in the plug-in unit special use time that when a certain address node 78 and 79 can be in logical one, impels circuit 64 to be in logical zero, thereby starts storer 62 so that accept the interview.When the term of validity of address at the end, the output terminal of AND gate 87 can be in logical zero, and meeting (by JK flip-flop 80) is clocked on the node 79, storer 62 can fail simultaneously.When a certain address was effective, " starting " (as shown in figure 12) was in logical one, and " affirmation " is in logical zero (seeing the chronogram that inserts signals such as showing " starting ", " affirmation " that are input in the device 71, " clock " among Figure 12)." affirmation " signal is in the input end process conversion of AND gate 87.Therefore, when a certain address when being effective, the output of AND gate 87 is in logical one; When a certain address when being invalid, " starting " is in logical zero, and the input end that impels AND gate 87 is at logical zero, and this value is clocked into the output terminal Q of trigger 80 under next NuBus time clock, as shown in figure 12.Logical zero at output terminal Q can make the CS circuit of storer 62 fail.Trigger 80 is timing JK flip-flop, and its input end K receives input end J(" D " by transducer); This trigger is called D flip-flop sometimes, and wherein K is the complement code of J.The loop ends signal also can be added to the RESET input of trigger 80.This signal is available from the operation circuit on the plug-in unit (for example CPU 61), and it represents the end of a certain business.The loop ends signal is a low-voltage active type signal, thereby process conversion on the input end of " resetting ".

Depending on that from the specific output at circuit 64 of control device 71 storer 62(is according to manufacturing firm) regulation CS is movable under the low-voltage (it is movable promptly to resemble under the low-voltage the ground) or in high voltage (+5 volts) activity down.In this example, suppose that storer 62 is CS low-voltage active type ("/CS "), so storer 62 is to select to such an extent that it is accepted the interview during at logical zero at device 71 output.Therefore circuit 64 is to work when logical zero (low-voltage) at the output of NOT-AND gate 72, and this impels CS to be pulled to equal haply the current potential on ground, thereby represents that to memory chip (storer 62) they are accepting the interview.

If the specific number of address does not match with the highest effective hexadecimal digit, then a logical one can appear at least one output terminal of four of exclusive-OR gate output terminals in comparison means 70, this impels on the output terminal of OR-gate 77 and occurs 1, and this logical one appears on the node 70a.This means that this address is not in the super space of plug-in unit.In this case, have only when this address be in 42(little space, district) time, storer 62 just can be accepted the interview.

Decoding device 60 also comprises a comparison means 73, keeps " card slots space " (being district 42 shown in Figure 3) that is positioned at the 1/16th actual address space, system top in order to give this particular plug-in.More particularly, comparison means 73 inserts 16 megabyte that the specific number of the groove at place is given the plug-in unit allocate memory according to plug-in unit.Comparison means 73 has a NOT-AND gate 85 determining when the address that offers plug-in unit is in the district 42.The exclusive-OR gate of comparison means 73 (" XOR ") (for example exclusive-OR gate 88) and OR-gate 89 compares time the highest effective hexadecimal digits with the specific number that plug-in unit inserts the card slots at place, equal to appear at the highest inferior hexadecimal digit of the address on the 32 bit address buses of NuBus 10 to determine when this specific number.When this reciprocity situation occurring, each XOR gate of device 73 (for example door 88) can produce logical zero at its output terminal, and the output that impels OR-gate 89 is at logical zero.The output terminal of OR-gate 89 is one of them input end of OR-gate 75.Address (A31 ... A28) four effective binary digits the highest all are added on the input end of NOT-AND gate 85; This output terminal have only when the address be just to be in logical zero in little space region 42 time.The output terminal of NOT-AND gate 85 is one of them input end of OR-gate 75.Two input ends of OR-gate 75 have only just all be in logical zero when the address are little space in the district 42 at plug-in unit.Therefore the output terminal of OR-gate 75 have only when the address be just to be in logical zero in the little space at plug-in unit the time.Address lines (A27, A26, A25 and A24) constitutes time the highest effective hexadecimal digit of the address on the 32 bit address buses that appear at NuBus 10.

As can be seen, when in the card slots a plug-in unit (for example plug-in unit 50a) being inserted specific number specific number $X, decoding device 60 can impel this plug-in unit for oneself reserving from the auxiliary storage space of the dedicated memory space of unit $ X000 0000 to $ XFFF FFFF and the special use from unit $ FX00 0000 to unit $ FXFF FFFF.

Business between CPU 1 and the NuBus 10 generally needs interface 9 to carry out some action, and this interface is called NuBus interface 9.The practical function process of interface depends on to CPU 1 selected microprocessor and relevant bus thereof.The simplest form is that interface may be the decoding device that another kind has six demoders (each for example resembles decoding device 60); This decoding device receives the signal specific of six different specific number specific numbers $0, $1, $2, $3, $4 and $5, these six signals each for a use in six demoders; This layout can cause the actual address storage space of electronic computer system shown in Figure 1 to be divided into as shown in Figure 3 the sort of situation.Interface 9 also needs to coordinate the difference aspect timing between CPU 1 and the NuBus clock, and the attaching problem of definite main device all buses (no matter being NuBus 10 or processor bus 5,25 and 6) of asking, make only on all buses 10,5 and 25, to occur an address each time.Therefore as shown in Figure 12, may have some decoding devices, each decoding device receives different signal specific.The lead-out terminal of these decoding devices is coupled on the CS pin of storer 2.Simultaneously, CPU 1 is as long as be placed on signal on the address bus 5 of coupling interface 9 and just can visit all card slots that are connected to NuBus 10, and this can appear on the NuBus 10 address signal of CPU 1.Equally, CPU 1 can provide data to the NuBus card slots by data are placed on the data bus 6, thereby impel data-signal to appear on the NuBus interface 9 via interconnect bus 12, those data-signals can be brought on the NuBus 10 then, received by suitable card slots, this depends on an address signal that appears on the NuBus 10 again.In fact, CPU 1 and relevant circuit thereof comprise storer 2, can appear on the NuBus 10, just as if it was originally the same on the plug-in unit in groove 0 or groove 1,2 and 3.In the relevant below argumentation of NuBus interface, " processor bus " speech typically refers to and is coupled to CPU 1 and is coupled to the data bus 6 of storer 2 and the address bus 5 and 25 shown in Fig. 1.

NuBus interface 9 shown in Fig. 5 has three state machines and NuBus clock, their contact effects at six card slots (29,30,31,32,33 and 34), NuBus 10, CPU 1 and storer 2 and in the middle of plaing between the relevant circuit on the motherboard 14.Usually, interface 9 should be at each main frame (for example CPU 1 and the CPU on plug-in unit, for example CPU 61) between determine the attaching problem of the bus asked, in case 2 different addresses of two different main frames appear on the bus (for example bus 5 or NuBus 10) simultaneously; In other words, interface 9 must clash on same bus to prevent the address by to asking to use the result who arbitrates between each main frame of same bus to determine the attaching problem of bus.Equally, in each datacycle process, interface 9 also should be by using the result who arbitrates between all main frames of same bus to determine the attaching problem of bus to asking, in case the arbitrary bus of data (for example bus 6 or NuBus 10) goes up conflict.In addition, interface 9 must make the signal of the main frame of filing a request and desiredly will or coordinated by the timing of the bus of host computer control (in order to reading of data) by host driven (in order to visit or write data).The interface effect can adopt method known in the programmable logic array to put into practice.

The publication material intermediary of IEEE 1196 technical manuals and the Texas Instruments Inc spoken of the above signal on the above-mentioned NuBus of appearing at that continued.Generally speaking, the NuBus standard code appear at logic, physics and the electrical standard of four kinds of signals on the NuBus bus 10.These signals comprise such as utility signals such as clock and specific identification line unit, address/data signal together with various control signals, arbitration signal and electric power signal.Some this class NuBus signal appears at NuBus interface 9 left sides shown in Figure 5 as can be seen.The signal flow that CPU 1 or register 2 are provided is through interface or make interface that CPU 1 can be got in touch each other with NuBus 10.Following table has been introduced the signal that is used for the NuBus state machine relevant with NuBus interface 9.The particular of interface 9 depends on the particular CPU 1 selected for use for using and deviser's target on motherboard.

Table 3

NuBus state machine in the NuBus interface 9 makes

With some signals

Signal instruction

RQST NuBus signal; The low-voltage active type; The expression request is right

Bus is controlled.

NuBus is from the decode address of processor CPU 1, and expression is added to

Address reference on the NuBus; The low-voltage active type.From

Decode in a decoding device in the address of CPU 1, this decoding

Device is that those skilled in the art can make

Come out, it determines that when address on the bus 25 is at NuBus

$ 6,000 0000 is to the address realm of $ FFFF FFFF.

Starting NuBus signal; The low-voltage active type; Have on the expression NuBus

The address occurs.

ARB0-ARB3 NuBus signal; The low-voltage active type; For NuBus is carried out

The arbitration address of the bus host of controlling and competing.

ACK NuBus " affirmation " signal; The low-voltage active type; Subordinate

The NuBus device is being confirmed " starting " business.

RMC processor CPU 1 signal is illustrated in processor CPU 1 bus

Read on 6 and 25/revise/write

AS processor CPU 1 address strobe, expression is from the ground of CPU 1

Effective and the circulation of request of location circuit.The low-voltage active type (

“/AS”）。

NuBus business in the/BUSLOCK input store 2 can not interrupt processor

Bus 6,5 and 25.

DSACKx is from the data strobe confirmation signal of storer 2.

BG processor CPU 1 bus is awarded and is allowed, and expression is with processor bus

5,6 and 25 award and give NuBus, be connected to storage so that adopt

The NuBus and the storer 2 of device 2 state machines 104 are got in touch.

C16M processor CPU 1 clock signal is in order to examine from processor

Whether the signal of CPU 1 is effective.

When the R/W read-write reads or writes in order to expression.

The request to bus that/BR NuBus proposes is asked total to processor

Line [mainly be that bus 6(is via bus 12) and bus 5 and 25

] control.

/ BGACK is from the NuBus signal of NuBus state machine 104, affirmation place

The reason machine allows to awarding of processor bus.In general, NuBus

By sending one/BP signal the controlling processor bus is proposed

Request; Request to processor bus is granted by signal/BG

, this signal is by the NuBus that is connected to storer 2 state machines 104

Receive, confirm what awarding of recipient processor bus allowed for control

With.

/ BERR is from the bus error signal of NuBus, and is wrong in the expression system

Mistake.This signal is sent by NuBus timeout state machine 105 usually

, it is monitoring the business that surpasses about 25 microseconds; Bus timeout

State machine confirms that any this business is to be in error condition, from

And send signal/BERR to processor.

/ DS data strobe: a kind of NuBus signal, expression is from NuBus

The data circuit of bus is effectively and represents circulation of request

。

In general, when processor CPU 1 produced actual address from $ 6,000 0000 to $ FFFF FFFF, processor CPU 1 will visit NuBus 10 and file a request to it.Demoder on the motherboard on being coupled to bus 25 show that an address on the bus 25 has and between during the highest effective hexadecimal digit of (comprise and) one, the CPU 1 that receives NuBus state machine 103 determines to exist above-mentioned the sort of request.In this case, the output of this all demoder impel/the NuBus signal claims.At this moment status pole 103 can have NuBus 10 so that after on address signal driving N uBus 10 at definite CPU 1, and clock coordination is got up during with the request of NuBus control and NuBus, and same address is provided on the bus 10.If a plug-in unit response on the NuBus, then data just are transferred.If there is not the plug-in unit response, then produce the NuBus timeout mode, bus error signal is arranged simultaneously, (/BERR) sending to processor, this can cause the execution of error handler usually.NuBus timeout state machine 105 is being monitored last " starting " signal of NuBus and NuBus goes up the time of confirming between (ACK) signal.When the time between this signal surpassed 255 NuBus clocks, according to the NuBus standard, the NuBus timeout state machine produced above-mentioned bus error signal.Fig. 8 display processor CPU 1 is by the business of NuBus interface 9 to NuBus, more particularly, by processor to the relevant signal of the business of NuBus state machine 103.All signals that CPU 1 side of machine 103 is received on 103 right sides of square frame shown in Fig. 8 all are the NuBus signals.The right side of machine 103 is NuBus sides of system, and has 6 card slots.The left side of interface 9 is CPU 1 and storer 2 parts of system.Also be like this among Fig. 9.The signal that enters (being that arrow is a sensing machine 103) machine 103 from the NuBus side is the NuBus signal normally, and the signal that comes out at NuBus side slave 103 is by CPU 1 that produce or CPU 1 and machine 103 results of interaction.Equally, all signals that enter machine 103 in the CPU of machine 103 1 side are that some are usually from the signal of CPU 1 or storer 2 or the circuit relevant with system this part.All signals of machine 103 and 104 CPU 1 side are by bus 12 carryings of Fig. 1, and all signals of machine 103 and 104 NuBus side are by bus 11 carryings.

The business of common CP U 1 to NuBus is waited for from state machine 103 signal/NuBus is affirmed (with itself and 10 megahertz NuBus clock synchronizations.When this signal once certainly, and other bus host is on NuBus 10 certainly during the RQST signal, original waiting status, i.e. state A, B just gets the hang of.State B has affirmed the RQST signal of NuBus and has also filed a request among the bus host of RQST signal certainly for 10 what its while in office of NuBus by means of CPU 1.In order just to arbitrate according to the NuBus standard, CPU 1 distributes to Cao $0.

After the state B then is state C, and during state C, whether arbitrate signal and affirmation (ACK) signal are taken a sample underway to examine any other NuBus business, and perhaps whether some other NuBus main frame has won NuBus 10.Some a certain professional underway and other bus hosts do not win control, then reserved state C yet.If during state B, there is any other bus host that bus is filed a request, the D[that then just gets the hang of annotates: because processor CPU 1 is from Cha Jiancao $0 access bus, thereby it loses all the time to other card slots, because arbitration is what to carry out according to the specific number of NuBus standard].If there is not other bus to win this bus, and do not carry out other business, E then gets the hang of.

State E determines NuBus bus 10 " starting " signal, and the address is driven on the NuBus 10 from CPU 1.Be understood that, latch and impact damper be in order to temporarily with address and data storage at these state machines 103 and 104, and normally be stored in the system.After the state E is state F, and state F waits for affirmation (ACK) signal from the plug-in unit of originally accepting the interview.When ack signal on NuBus 10 and other main frame were not filed a request to bus 10, G just got the hang of.In state G, produce and be added to of the circulation of the DSACKx signal of processor CPU 1 with terminal procedure.If other main frame is not determined the RQST signal during state G, H just gets the hang of.State H is the state that NuBus 10 is in " parked " state, in other words, is not get the hang of A but the E that directly gets the hang of from the NuBus business of processor CPU 1.If sure RQST signal during state F, G or H then must be arbitrated again to NuBus 10, determining existing bus host, and state A is not the H but enter waiting status of getting the hang of.The available known state machine technique of the ordering of these states carries out.Following table has been summed up related state and signal in processor CPU 1 to NuBus interface, and these all are to be carried out by the CPU 1 that receives NuBus state machine 103.

Table 4

The state of processor CPU 1 to NuBus

The determined signal instruction of state

The A idle condition.Wait for that processor CPU 1 produces

The NuBus address access (visit from

$ 6,000 0000 storages to $ FFFF FFFF

The unit) and wait for that in the NuBus card slots each insert

Negate (from plug-in unit) RQST signal.

B. RQST files a request to NuBus, and processor CPU 1 exists

To filing a request, and do not exist other by sure

The RQST signal.

C. RQST is to the check of arbitration victory.It should all negate the arbitration line

The road is because the arbitration of processor CPU 1 number is zero

。If a last cyclic system is waited for ack signal, then

Keep more.If being in, a certain arbitration circuit agree

Decide state, then in next " starting " business

After try again.

D RQST waits for the next round arbitration." starting " shows next

The wheel arbitration effectively.

E " starting ", A0-A31 start professional.32 bit address buses at NuBus

(NuBus) go up processor CPU 1 address certainly.

Machine ACK such as F A0-A31.Wait for the affirmation of subordinate device.If

CPU 1 is writing to (for example one of NuBus device

Plug-in unit) then CPU 1 affirms A0-A31(NuBus)

。Should notice whether RQST is come to determine bus certainly

Whether still be in " parked " state.If it is right

RQST adds that then state machine can be at state G certainly

Be recycled to state A afterwards.

G DSACK0, DSACK1 is DSACKx certainly.The business that the NuBus subordinate is finished

With processor CPU 1 circulation.NuBus still locates

In " parked " state.

H waits for that next processor CPU 1 is to NuBus's

Professional.NuBus still is in " parked " state

, so that next circulation cannot Fast starting.

State machine shown in Figure 8 receives the CPU 1(A0-A31 from CPU 1 on bus 25) address signal.The signal that appears at state machine 103 right sides is the NuBus signal.Some signal in state machine 103 left sides also is the NuBus signal, for example clock signal/CN10M and C20M, and/NuBus, though the latter by CPU 1 by producing the NuBus address together.

The NuBus(that receives CPU 1 bus state machine 104 is as shown in Figure 9) be in order to can comprise RAM, ROM and I/O from NuBus reference-to storage 2().In one embodiment, if an address of 0,000 0000 to 5FFFF FFFF is provided on NuBus, the NuBus that then is connected to processor bus state machine 104 just claims and carries out the visit of location over the ground from 1 pair of processor bus of CPU.Also to introduce another embodiment (Figure 10), wherein the visit of the RAM of storer 2 be undertaken by visit $ 0,000 0000 to $ 3FFF FFFF, to motherboard

The visit of ROM or I/O is changeed $ F0FF FFFF by visit $ F000 0000 and is carried out.Usually, data are sent to NuBus main frame (i.e. plug-in unit in the NuBus card slots) or after the NuBus main frame transmits, and the control of processor bus 5 and X is just turned back to processor CPU 1.

State and signal that the following table introduction is relevant with the business of the NuBus that receives CPU 1 bus.

Table 5

State is by sure signal instruction

The A1 idle condition.Wait is received processor bus respectively

The unit (for example $ 0,000 0000 to

$ 3FFFF FFFF and $ F000 0000 to

$ F0FF FFFF) address on the NuBus.

If processor bus is not in lock-out state (example

As passing through the lock bus signal of CPU 1 certainly

) and CPU 1 CPU 1 is not being conducted interviews

, then can ask to some extent processor bus.If

Certainly " lock bus " then postpones NuBus

To the visit of storer 2, up to affirming again

Till " lock bus " signal, and state still

So be in the A1 state.

B1 BR is " bus request " certainly.NuBus is to handling

The machine bus is filed a request to be connected to storer

The business of 2 NuBus.Waiting for CPU 1 is agree

Fixed " bus is awarded and allowed " signal and the choosing of negative address

Logical.

C1 BGACK, A0-A31 is certainly to the control of processor bus and definite

The address and/or the data of (on bus 25)

D0-D31

(on bus 6)

R/W

D1 AS; DS; A0-A31 is by sure address strobe.By sure data

(on bus 25) gating.

E1 D0-D31 wait for valid data from storer 2 (or

DSACK person write on the storer 2 in the data valid period

）。Wait is from storer 2 expression circulation knots

The data strobe of bundle is confirmed (DSACK) signal.

F1 ACK(NuBus) be connected to processor bus NuBus business

Finish.Wait and determine that whether next circulation exists

Advance under the situation of NuBus controlling processor bus

OK.NuBus can be by " locking is noted certainly

Signal " be locked on the processor bus this letter

Number impel CPU 1 if abandoning locating on the business

The control of reason machine bus, and unlikely generation contention

The incident of CPU 1 is until to " zero note "

Till signal is affirmed; To " locking is noted

" the state B1 that impels certainly of signal is recycled to F1

。

Receive the NuBus of CPU 1 bus, the state A1 shown in the table 5 begins above professional output for it.In state A1, state machine 104 is in idle condition, is waiting at storer 2 storage spaces ($ 0,000 0000 to $ 5FFF FFFF for example; Or in another embodiment of Figure 10, $ 0,000 0000 to $ 3FFF FFFF and $ F000 0000 to $ F0FF FFFF) in a address on the NuBus 10.By impel (Buslock) signal of all " lock bus " that the business in this space, address is identified of NuBus certainly under the response condition of " examination more later on ", can prevent the visit of NuBus to all processor bus.If the address is in storer 2 spaces, and " lock bus " signal is not affirmed, then entered the B1 state.

At state B1, CPU 1 discharges processor bus by " bus is awarded and allowed " signal (BusGrant) signal that sends response " bus request " Bus Reguest signal; " bus is awarded and allowed " signal is confirmed by means of " bus award allow affirmation " (BusGrant Acknowlegement) signal among the next state C1 by the NuBus device.Each address all is driven on the processor address bus, and data then are to shift under state D1 and E1.Business is finished in F1, and at this moment the NuBus ack signal obtains on NuBus 10 certainly.

In another embodiment of Figure 10, the RAM of the address reference-to storage 2 of NuBus device by $ 0,000 0000 to $ 3FFF FFFF scope is provided.In the present embodiment, the NuBus device is indirectly by providing scope in $ F000 0000 to $ F0FF FFFF(card slots space on NuBus 10) the part of ROM storage space of address visit motherboard and the part of the I/O storage space of motherboard (this normally lie by for the actual RAM assembly of I/O use).In the present embodiment, scope is not visited ROM or I/O in the address of $ 4,000 0000 to $ 5FFF FFFF on the NuBus 10, but on CPU 1 bus (for example bus 5) at the storage space of the address of this scope certain travel all over motherboard ROM and I/O.For meeting the regulation of NuBus standard, the ROM of the motherboard that (distributing to Cha Jiancao $0 at least) NuBus can visit partly is installed in card slots Kong Jian $0 top.Concrete allocation scheme in the card slots space of storer between motherboard I/O depends on deviser's needs.In a most preferred embodiment, Cha Jiancao $0 in two, make and to receive that the address visit motherboard ROM(of $ F080 0000 to $ F0FF FFFF is the ROM of storer 2 on the NuBus 10) 8 megabyte districts, receive 8 megabyte districts of the address visit I/O storage space of $ F000 0000 to $ F07F FFFF on the NuBus 10.These 8 specific megabyte spaces of ROM and I/O storage space depend on need be maybe will be with the zone of which type of storer NuBus device.Total system (motherboard) ROM and motherboard I/O tend to pack in the 16 megabyte districts of card slots Kong Jian $0.Can adopt known demoder so that carry out from card slots Kong Jian $0 to the suitably decoding of ROM and I/O unit.

Claims (13)

1, a kind of electronic computer system, comprise a main circuit board, a CPU (central processing unit) and some card slots are arranged on this main circuit board, each card slots has the suitable device that receives a printed circuit board plug-in, described CPU (central processing unit) (CPU) is coupled with storer, be used for receiving memory unit address and data being provided for described CPU from described CPU, described storer is configured on one of described main circuit board and described plug-in unit at least, described main circuit board has the I/O circuit, it is coupled to described storer so that data are provided for described storer, and be coupled to described CPU so that receive control signal from described CPU, it is characterized in that, the card slots of described main circuit board is less than 16, described main circuit board comprises one 32 bit address buses, it is coupled to described CPU and is coupled to described storer to visit described storer, and described CPU comprises a generating device of the address, in order to produce 2 ³²Individual different address, its scope from Dan Yuan $0000 0000 to Dan Yuan $FFFF FFFF, described unit is represented with hexadecimal notation, each described card slots has a specific number in described system, and be coupled to described bus to visit described storer, each described card slots is coupled on the specific identification line unit on the described main circuit board, the card slots that each described specific identification line unit is coupled for described specific identification line unit provides a specific not varying signal, the described signal specific of a certain particular plug-in groove is discerned the specific number of described particular plug-in groove, wherein, the described specific number of a certain particular plug-in groove is (ID), described specific number keeps the storage space of 256 megabyte for each described card slots, make described 256 megabyte storage spaces in unit $ (ID) 000 0000 beginnings, finish at unit $ (ID) FFF FFFF, thereby make any plug-in unit among the card slots X have the dedicated memory space that finishes at Dan Yuan $XFFF FFFF in Dan Yuan $X000 0000 beginning, described all unit all are to represent with hexadecimal notation.

2, a kind of personal electric computer system, comprise a main circuit board, this main circuit board has a CPU (central processing unit) and some card slots, each card slots has the suitable device that receives a printed circuit board plug-in, described CPU (central processing unit) (CPU) is coupled with storer, be used for receiving memory unit address and data being provided for described CPU from described CPU, described storer is configured on one of described main circuit board and described plug-in unit at least, described main circuit board has the I/O circuit, it is coupled to described storer so that data are provided for described storer, and be coupled to described CPU so that receive control signal from described CPU, it is characterized in that, the card slots of described main circuit board is less than 16, described main circuit board comprises one 32 bit address buses, it is coupled to described CPU and is coupled to described storer to visit described storer, and described CPU has a generating device of the address, in order to produce 2 ³²Individual different address is for the usefulness of the described storer of visit on described 32 bit address buses, described 2 ³²Individual different address defining scope from the unit 0000 memory address space to unit FFFF, described all unit are all represented with hexadecimal notation, each described card slots has a specific number in described system, and be coupled to described 32 bit address buses so that receive storage address on the described plug-in unit be configured in the described card slots, each described card slots is coupled on the specific identification line unit on the described main circuit board, the card slots that each described specific identification line unit is coupled for described specific identification line unit provides a specific not varying signal, each described signal specific provides specific number for the card slots that receives described signal specific, wherein, described electronic computer system has the 256 megabyte storage spaces of scope from Dan Yuan $X000 0000 to Dan Yuan $XFFF FFFF, reservation is to the storer special use on the plug-in unit in the card slots of specific number Deng Yu $X, and Qi Zhong $X can be any integer of Cong $0 to $E.

3, personal electric computer system as claimed in claim 2 it is characterized in that ， $X can be any integer of Cong $9 to $E, and wherein said main circuit board has 6 card slots.

4, personal electric computer system as claimed in claim 3, it is characterized in that described specific identification line unit has four circuits, each bar circuit is loaded with binary value, and wherein said 32 bit address buses also comprise control signal, and come down to a NuBus bus.

5, personal electric computer system as claimed in claim 4, it is characterized in that, described computer system has the 16 megabyte storage spaces of scope Cong $FX00 0000 to $FXFF FFFF, keeps to the storer special use on the plug-in unit in the slot of specific number Deng Yu $X.

6, a kind of printed circuit board plug-in, has plurality of terminals, these terminals suitable with the main circuit board that is arranged on a personal electric computer system on one of 6 card slots on supporting terminal be electrically connected, wherein, the CPU (central processing unit) (CPU), one that comprises described main circuit board is coupled to the first memory of described CPU, one 32 bit address buses and an I/O circuit, described storer is in order to receiving memory unit address and data to be provided for described CPU from described CPU, described 32 bit address buses are coupled to described CPU and go up in order to from described CPU receiver address; Described I/O circuit is coupled on the described first memory data being provided for described first memory, and is coupled on the described CPU, so that receive control signal from described CPU; It is characterized in that, each described card slots is coupled on the described 32 bit address buses, described CPU comprises a generating device of the address, in order to produce 2 scopes from the unit 0000 to unit FFFF different addresses, described all unit are all represented with hexadecimal notation, each described card slots has a specific number in described electronic computer system, and be coupled on the specific identification line unit on the described main circuit board, described signal specific identification circuit device comprises four circuits, every circuit is loaded with binary value, wherein, described main circuit board comprises six specific number specific number $9, $A, $B, $C, the card slots of $D and $E, the specific identification line unit that each described card slots has oneself provides the signal specific of oneself to discern the specific number of card slots, thereby, the card slots of specific number specific number $9 is Cha Jiancao $9, and the described specific identification device that is coupled to described Cha Jiancao $9 will be to the described Cha Jiancao $9 value of providing $9, described plug-in unit has a second memory and is configured on the described plug-in unit, described second memory is a random access memory (RAM), there is selection to be coupled on the described CPU by described 32 bit address buses, to receive memory unit address and on described address bus, to provide data, described second memory is coupled on the described address bus, described 32 bit address buses provide an address in first cyclic process, and in second cyclic process, be received in data on the described address, described plug-in unit also has a decoding device that is coupled on the described specific identification line unit, in order to receive described signal specific, described decoding device compares the highest effective hexadecimal digit of described specific number and described address, to determine when that described specific number with hexadecimal representation equals the highest effective 16 system numerals of described address, described decoding device makes described second memory to be visited can provide data when described specific number with hexadecimal representation equals the highest effective hexadecimal digit of described address, therefore the described specific number in described card slots is the occasion of X, when the address between Mei Dang $X000 0000 and the $XFFF FFFF appears on the described 32 bit address buses, described second memory is accessed, thereby the storage space of 256 megabyte keeps to the described plug-in unit special use in described card slots, the storage space of described 256 megabyte finishes at Dan Yuan $XFFF FFFF in Dan Yuan $X000 0000 beginning.

7, printed circuit board plug-in as claimed in claim 6, it is characterized in that, described 32 bit address buses also comprise control signal, wherein, described decoding device compares described specific number and any address that appears on the described 32 bit address buses, and described decoding device impels 16 megabyte storage spaces to keep to described card slots special use, is the occasion of X in described specific number, the storage space of described 16 megabyte finishes at Dan Yuan $FXFF FFFF in Dan Yuan $FX00 0000 beginning.

8, printed circuit board plug-in as claimed in claim 7, it is characterized in that, described decoding device determines when the highest effective hexadecimal digit Deng Yu $F, and described decoding device compares time the highest effective hexadecimal digit of described specific number and described address, to determine when that described specific number with hexadecimal representation equals time the highest effective hexadecimal digit, described decoding device makes described second memory to be visited when described specific number with hexadecimal representation equals time the highest effective hexadecimal digit and can provide data when the highest described effective hexadecimal digit is $F, described specific number in described card slots is the occasion of X, when the address between Mei Dang $FX00 0000 and the $FXFF FFFF appears on the described 32 bit address buses, described second memory is accepted the interview, thereby make described 16 megabyte storage spaces in Dan Yuan $FX00 0000 beginning, finish at Dan Yuan $FXFF FFFF.

9, printed circuit board plug-in as claimed in claim 7 is characterized in that, described plug-in unit also comprises one second CPU (central processing unit) (the 2nd CPU), is coupled on the described second memory, to visit described second memory and to receive data from described second memory.

10, printed circuit board plug-in as claimed in claim 9, it is characterized in that, described the 2nd CPU is coupled on the described 32 bit address buses, so that carry out the NuBus business in fact on described 32 bit address buses, described plug-in unit can become a bus host in described NuBus bus traffic.

11, printed circuit board plug-in as claimed in claim 10 is characterized in that, described second memory is by described the 2nd CPU local access and need not to carry out the NuBus bus traffic on described plug-in unit.

12, printed circuit board plug-in as claimed in claim 11, it is characterized in that, described decoding device comprises comparison means, in order to determine on the described plug-in unit from the address of above-mentioned the 2nd CPU whether in the local address space at described plug-in unit, described decoding device is to prevent to carry out the NuBus bus traffic in the local address space at described plug-in unit the time in described address, the local address space of described plug-in unit, at described plug-in unit is in card slots X the time, comprises Dan Yuan $0000 0000 to $l0000 0000, $X000 0000 to $XFFF FFFF, $FX000 0000 to $FXFF FFFF.

13, a kind of printed circuit card, has plurality of terminals, this terminal is suitable to be electrically connected with a some supporting terminal that is configured in the card slots that is fit to the described plug-in unit of reception, described card slots is positioned on the main circuit board of a computer system, described main circuit board comprises a CPU (central processing unit) (CPU), be coupled to the storer of described CPU, one 32 bit address buses and an I/O circuit, described storer is in order to receive memory unit address and data to be provided for described CPU from described CPU, described 32 bit address buses are coupled on described CPU and the described storer in order to visit described storer, described I/O circuit then is coupled on the described storer so that data are provided for described storer, and being coupled to described CPU goes up so that receive control signal from described CPU, it is characterized in that, described card slots is coupled on the described 32 bit address buses, described CPU comprises a generating device of the address, in order to produce 2 scopes from the unit 0000 to unit FFFF different addresses, described unit is all represented with hexadecimal notation, described card slots has a specific number in described electronic computer system, and be coupled on the specific identification line unit on the described main circuit board, described specific identification line unit provides a signal specific for described card slots, described signal specific is discerned the specific number of described card slots, described plug-in unit comprises that one is coupled to the decoding device on the described specific identification line unit, be used to accept signal specific, more described specific number of described decoding device and the address that appears on the 32 bit address buses, described decoding device keeps 256 megabyte storage spaces to described card slots special use, like this, when the described specific number of described card slots is X, described 256 megabyte storage spaces, from Dan Yuan $X000 0000, finish at Dan Yuan $XFFF FFFF, described unit is represented with hexadecimal notation, and wherein, described plug-in unit in card slots X comprises that one is arranged on the second memory on the described plug-in unit, described second memory is coupled on the described CPU by described 32 bit address buses, so that receive the address of storage unit and data be provided for described CPU from described CPU, described second memory is coupled on the described 32 bit address buses, described 32 bit address buses then provide an address in first cyclic process, in second cyclic process, then be received in the data on the described address, wherein said second memory is retained in storage unit that Dan Yuan $X000 0000 beginning finishes at Dan Yuan $XFFF FFFF as special use, wherein, X can be any number between 1 and 14.

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