CN101699777B - Down link synchronization method applied to CDMA20001x EV-DO system - Google Patents

Abstract

The invention discloses a down link synchronization method applied to a CDMA20001x EV-DO system, mainly comprising the following steps: storing M half-slots in receiving signals with the s moment as a start and respectively extracting data on the pilot frequency burst position of each half-slot; carrying out interrelated accumulation on the data on the pilot frequency position of the n<th> half-slot and the data on the n<th> intercept with the local PN pattern number being i; padding zeros to the M point interrelated accumulation result until N point and then carrying out FFT; computing the squares of the moduli of the N point FFT result; comparing the maximum of the squares of the moduli with a preset threshold, if the maximum exceeds the threshold, finishing synchronization, or keeping searching other PN patterns; and if the related results corresponding to 16 PN patterns fail to exceed the threshold, enabling s to be equal to s+1, delaying one chip on the start positions of the receiving signals and repeating the above steps until synchronization is finished. The method can realize reliable down link synchronization when the receiving signals have larger frequency offsets and Ec/N0 of the pilot channel is lower.

Description

The down link synchronisation method that is used for CDMA2000 1x EV-DO system

Technical field

The present invention relates to a kind of CDMA20001x of being applied to EV-DO(hereafter EV-DO) the synchronous implementation method of system descending.

Background technology

CDMA20001x obtains one of extensively commercial 3G cellular radio Communication system at present, but along with the continuous growth of wireless data service demand, the tenability of the high-speed packet data service of CDMA20001x can not satisfy the demand of future development.For this reason, 3GPP2 has proposed the EV-DO technology, at sudden, the preceding/reverse link loading asymmetry of data service and the characteristics of big channel capacity, in the mode of smooth evolution, provides higher data transmission capabilities specially.

Compare the CDMA20001x system, EV-DO can provide higher air interface rate.Forward link has adopted technology such as time-derived channel scheduling, dynamic rate control and high order modulation, and simultaneously, reverse link has used technology such as reverse pilot, power control and speed control, makes network can more reasonably arrange various wireless data services.

The time-derived channel structure of EV-DO system forward link as shown in Figure 1, the forward link baseband signal that the base station sends has all been passed through the scrambling of pseudo noise (PN) sequence, different PN sequence phases is used for the different base station of difference.Each base station will send special pilot channel so that the travelling carriage in this residential quarter carries out synchronously, travelling carriage must be caught the PN sequence phase of residential quarter, place the very first time, and with local PN sequence (error must in the magnitude of part chip) accurate descrambling with it synchronously.

The frame period of EV-DO is 26.667ms(32768 chip period), spreading rate is 1.2288Mchip/s, is divided into 16 time slots (slot), and each time slot is divided into 2 half cracks (half-slot) again, and structure of time slot is as shown in Figure 2.

The PN sequence signature multinomial of I, Q two-way is respectively:

P _I(x)=x ¹⁵+x ¹⁰+x ⁸+x ⁷+x ⁶+x ²+1

P _Q(x)=x ¹⁵+x ¹²+x ¹¹+x ¹⁰+x ⁹+x ⁵+x ⁴+x ³+1

Corresponding generator polynomial is respectively:

$i\left(n\right)=i(n-15)\&CirclePlus;i(n-13)\&CirclePlus;i(n-9)\&CirclePlus;i(n-8)\&CirclePlus;i(n-7)\&CirclePlus;i(n-5)$

$q\left(n\right)=q(n-15)\&CirclePlus;q(n-12)\&CirclePlus;q(n-11)\&CirclePlus;q(n-10)\&CirclePlus;q(n-6)\&CirclePlus;q(n-5)$

$\&CirclePlus;q(n-4)\&CirclePlus;q(n-3)$

Wherein, symbol

Expression mould 2 adds computing.The generation of PN sequence generally uses linear feedback shift register (LFSR) to realize that the PN sequence LFSR structure chart on I road and Q road as shown in Figure 3.

The m sequence period length of 15 grades of shift registers is 2 ¹⁵-1, insert one 0 in continuous 14 0 backs, carry out then unipolarity to ambipolar mapping (bit 0 is mapped as+1; Bit 1 is mapped as-1) cycle of obtaining is 2 ¹⁵The PN sequence of (32768 chips) joins end to end and periodically repeats.

The initial moment of system zero bias reference PN sequence is defined as: first 0 the delivery time in continuous 15 0.With frequently between the base station, utilize PN sequence biased exponent (PN offset index) to distinguish, biased exponent (value from 0 to 511, totally 512 kinds of value possibilities) multiply by the hysteresis number of chips that 64 chips are exactly this base station PN sequence Relative Zero bias reference PN sequence.

At receiving terminal, utilize PN sequence descrambling flow process as shown in Figure 4.Suppose that receiver is the reception signal of an initial store M half crack (a corresponding 1024M chip) length with a certain moment s, real part and the imaginary part of establishing this signal are respectively r _I(s+k), r _Q(s+k), k=0 wherein, 1,2 ... 1024M-1 utilizes the local multiple PN sequence P that generates _I(k), P _Q(k) descrambling to received signal, the I behind the descrambling, Q road signal are:

y _I(s+k)=r _I(s+k)P _I(k)+r _Q(s+k)P _Q(k)；

y _Q(s+k)=r _Q(s+k)P _I(k)-r _I(s+k)P _Q(k);k=0,1,2…1024·M-1。

The catching method of existing PN sequence generally is that reception signal starting point s is slided at whole PN sequence period, for each possible Phase synchronization moment s, with the scrambling sequence y of correspondence _I(s+k), y _Q(s+k) (k=0,1,2 ... 1024M-1) data that extract pilot frequency burst position add up again, and the accumulation result in m half crack is designated as θ _m(s):

${\mathrm{\&theta;}}_m\left(s\right)=\underset{k=464}{\overset{559}{\mathrm{\&Sigma;}}}{y}_I(s+1024\&CenterDot;m+k)+j\&CenterDot;\underset{k=464}{\overset{559}{\mathrm{\&Sigma;}}}{y}_Q(s+1024\&CenterDot;m+k);m=\mathrm{0,1},...M-1;$

Again with M result (θ ₀(s), θ ₁(s) ..., θ _M-1(s)) ask for mould value square after adding up, be designated as | θ (s) | ²:

${\left|\mathrm{\&theta;}\left(s\right)\right|}^2={\left|\underset{M=0}{\overset{M-1}{\mathrm{\&Sigma;}}}{\mathrm{\&theta;}}_m\left(s\right)\right|}^2$

Then in a PN sequence period, make | θ (s) | ²Maximum moment s is and receives signal PN sequence phase synchronization point

$\hat{s}=\arg \underset{s}{\max }|\mathrm{\&theta;}\left(s\right){|}^2.$

Pilot channel is time division multiplexing among the EV-DO, the scrambling sequence of pilot frequency burst position in each half crack of only adding up during search.When realizing, in order to simplify correlation computations, only the data of pilot frequency burst position are carried out descrambling to received signal.Receiving terminal needs intercept local PN sequence before work is relevant at this moment, and method is: after the PN sequence that obtains a certain biased exponent correspondence, intercept 96 middle chip data of per 1024 chips.But the sequence that obtains after the PN sequence intercepting of different biased exponents is different (this paper is referred to as the PN pattern).Because the PN biased exponent of residential quarter, unknown place, travelling carriage need be searched for all possible PN pattern when carrying out initial acquisition.

The relation of PN biased exponent and PN pattern as shown in Figure 5, the position (being called for short the PN intercept herein) of the pilot burst in each half crack of schematically having drawn among the figure is numbered Pi(i=0,1,, 511) the PN intercept represent that biased exponent is first segment data after the PN sequence intercepting of i.Because PN sequence hysteresis number of chips is unit with 64chip, the then every increase 16 of PN biased exponent, PN sequence hysteresis number of chips increases by 1024 chips, just equals the length in a half crack, has marked the situation of the PN intercept appearance of numbering P0 among the figure.Analyze as can be known, local PN sequence has 16 kinds of different patterns, PN sequence after all the other 496 kinds of interceptings can be that unit sequence skew obtains with the PN intercept by these 16 kinds of patterns: when the biased exponent of any two kinds of PN sequences differs 16 or 16 integral multiple, have identical PN pattern, and on sequence leading or several PN intercepts that lag behind.Therefore, when catching, be that 0 to 15 PN pattern detects the base station pilot signals that can guarantee to find any PN biased exponent to biased exponent.

In the real system, receive the E of signal _c/ N ₀(E _cFor receiving signal averaging chip energy, N ₀Be noise power spectral density) may be very low, and only accounted for the part transmission time slot for the pilot channel of PN sequence capturing; In addition, may there be bigger radio frequency crystal oscillator frequency deviation in travelling carriage or be in the vehicle-mounted high-speed mobile environment.These all will increase the difficulty of PN sequence capturing.

For traditional catching method, at low E _c/ N ₀Situation under, need to increase correlation lengths (namely increasing above-mentioned half timeslot number M) in the hope of improving acquisition performance, but exist at receiving terminal under the situation of frequency shift (FS), the more long frequency shift (FS) of correlation length is also more big to the influence of catching the result.The tradition catching method can't be taken into account the performance of two aspects simultaneously.

Summary of the invention

At the existing in prior technology shortcomings and deficiencies, purpose of the present invention is exactly to propose a kind of down link synchronisation method for CDMA20001x EV-DO system.This method is applicable to programming device (including but not limited to FPGA, DSP etc.) realization, can for conventional method, can receive the bigger frequency shift (FS) of signal existence and the E of pilot channel to 16 kinds of PN pattern parallel searches _c/ N ₀When low, realize reliable down-going synchronous; And can be according to the channel circumstance of reality, configuration parameter flexibly, better utilization hardware resource.

The present invention is achieved through the following technical solutions above-mentioned purpose: be used for the down link synchronisation method of CDMA20001x EV-DO system, comprise:

Step 1, be the data in initial M half crack of reception signal buffer memory with current time s, extract the data of each half crack pilot frequency burst position respectively;

Step 2, make n=0, i=0 number is n relevant the adding up of PN intercept data of i with the data that receive n half crack of signal pilot frequency burst position and local PN pattern, obtains 1 spot correlation accumulation result;

Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 spot correlation accumulation result;

Step 4, with the M spot correlation accumulation result end zero padding of step 2 and step 3 gained to the N point, carry out the FFT conversion, obtain N point transformation result, wherein M＜N and N are 2 integral number power;

Step 5, N point transformation result is asked for mould value square, obtain N point mould value result;

The N point mould value result's that step 6, search step 5 obtain maximum;

Step 7, maximum and default thresholding that step 6 is searched for compare, if surpass default thresholding, then successfully catch the PN phase place; Otherwise i=i+1, n=0 returns step 2, until i=15;

Step 8, if the maximum of 16 kinds of PN pattern correspondences all have to surpass default thresholding, s=s+1 then receives the signal original position chip of delaying time, and returns step 1;

Described PN pattern refers to the sequence that obtains after the PN sequence intercepting of different biased exponents; The position of pilot burst is the PN intercept in each half crack, and the PN intercept that is numbered Pi represents that biased exponent is first segment data after the PN sequence intercepting of i, i=0 wherein, and 1 ..., 511.

In described down link synchronisation method, after step 7 is successfully caught the PN phase place, also execution in step 9, the position that in N point mould value result, occurs according to maximum

To received signal and the frequency offseting value that exists between the local PN sequence

Estimate:

When

The time,

When

The time,

T wherein _cChip period for single-time sampling.

Synchronizing process of the present invention is: be storage 1024M chip lengths (corresponding M half crack) in the initial reception signal constantly with s, extracting the data of each half crack pilot frequency burst position more respectively; Number be i(0≤i≤15 with the data of the individual half of the n(0≤n≤M-1) crack pilot frequency burst position and local PN pattern) n intercept data

Relevant adding up; The result that the M spot correlation is added up mends 0 to N point and carries out the FFT conversion again, then N point FFT transformation results is asked for mould value square; With the maximum in the mould value square and default thresholding relatively, then finish synchronously if surpass thresholding, otherwise continue to search for other PN patterns; If the correlated results of 16 kinds of PN pattern correspondences does not all surpass thresholding, then s=s+1 receives 1 chip of signal original position time-delay, repeats above-mentioned steps, until finishing synchronously.

From above technical scheme and synchronizing process as can be known, compare with existing traditional catching method, advantage of the present invention and beneficial effect are:

1) is initial reception signal constantly with s, only to the pilot frequency locations data accumulating operation of be correlated with, reduced amount of calculation, in programming device, use the matched filter realization.

2) the segmentation correlated results is carried out the FFT conversion, and square maximizing as a result of search N point mould value, compare with default thresholding, can judge whether this phase place is the locking phase of PN sequence.Because related operation to received signal is that segmentation is carried out, thereby total correlation length of the present invention (M half crack) no longer is subjected to the restriction of frequency shift (FS).Through actual verification, frequency shift (FS) and E that the present invention can be in receiving signal existence ± 10kHz scope _c/ N ₀During 〉=-20dB, realize reliable down-going synchronous, and this method is adapted at realizing on the programming device.

3) if the points N value of FFT conversion is too little, the peak value during the PN Phase synchronization has bigger shake (being called the grid effect), thereby influences acquisition performance.The present invention is before the FFT conversion, by to P accumulation result (θ ₀(s), θ ₁(s) ..., θ _P-1(s)) end mends 0, increases the FFT points N, thereby has further improved the accuracy of acquisition performance and Frequency offset estimation.

4) 16 kinds of PN patterns of parallel search have effectively shortened mean acquisition time.When the present invention carries out parallel search to 16 kinds of PN patterns, to each search window or phase point, detected 16 kinds of PN patterns simultaneously after, slide again one and search for window or phase point; Rather than as serial search of the prior art, only search for a PN pattern at every turn, a PN pattern has been searched for a frame after, the following a kind of PN pattern of search again.Parallel search of the present invention remains come calculating one by one of branchs to 16 kinds of PN patterns in concrete calculating.

5) can carry out frequency deviation when successfully catching the PN phase place estimates.

Description of drawings

Fig. 1 is the schematic diagram of CDMA2000 1xEV-DO system forward link time-derived channel;

Fig. 2 is the schematic diagram of CDMA2000 1xEV-DO system forward chain time gap structure;

Fig. 3 generates the schematic diagram of I, Q two-way PN sequence for CDMA2000 1xEV-DO system utilizes LFSR;

Fig. 4 carries out the schematic diagram of descrambling to baseband signal for the multiple PN sequence of receiving terminal utilization;

Fig. 5 is the schematic diagram of PN biased exponent and PN pattern;

Fig. 6 carries out the schematic diagram of related operation to received signal for the present invention;

Fig. 7 realizes synchronous flow chart for the present invention.

Embodiment

The present invention is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiments of the present invention are not limited thereto.

Embodiment

The present invention can realize at programming device, carries out the process of related operation to received signal as shown in Figure 6, and whole acquisition procedure as shown in Figure 7; Specifically may further comprise the steps:

Step 1, with the data that current time s is initial M half crack of reception signal buffer memory (1024M chip lengths), be designated as r (s+k) (r (s+k)=r _I(s+k)+jr _Q(s+k), k=0,1,2 ... 1024M-1), extract the data of each half crack pilot frequency burst position respectively.

Step 2, make n=0, i=0 number is n the PN intercept data of i with receiving the data of n half crack of signal pilot frequency burst position and local PN pattern

(k=0,1,2 ... 95) relevant adding up obtains 1 spot correlation accumulation result.Wherein the length of PN intercept data can be got 1 to 96 any value in the chip, and namely the relevant length that adds up of each PN intercept can be got 1 to 96 any value in the chip, and computational efficiency is the highest when wherein getting 96 chips.The relevant matched filter that can use 96 complex tap in programming device that adds up realizes that n correlator is output as:

${\mathrm{\&theta;}}_i^n\left(s\right)=\underset{k=0}{\overset{95}{\mathrm{\&Sigma;}}}[r(s+1024\&CenterDot;n+464+k)\&CenterDot;{\mathrm{pn}}_i^n{\left(k\right)}^{*}];$

Wherein symbol * represents the complex conjugate computing.

Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 spot correlation accumulation result.

Step 4, with the M spot correlation accumulation result of step 2 and step 3 gained (

) the end zero padding to the N point, carry out the FFT conversion, obtain N point transformation result K=0,1 ..., N-1.Wherein M＜N and N are 2 integral number power; The FFT conversion can be used special-purpose FFT chip or use Nlog in programming device ₂N complex multiplier and 2Nlog ₂N complex adder realizes.

Step 5, with N point transformation result

K=0,1 ..., N-1 asks for mould value square, obtains N point mould value result, is designated as Asking for of mould value square can be by 2N real multipliers and N real add musical instruments used in a Buddhist or Taoist mass realization.

Step 6, the N point mould value result's that obtains by N-1 comparator search step 5 maximum be designated as metric (s), and the record maximum is in N point mould value result

The middle position that occurs

$\hat{k}=\arg \underset{k}{\max }\left({\left|Z_{\mathrm{FFT}}{\left(k\right)|}_s^i\right|}^2\right),k=\mathrm{0,1}...N-1;$

$\mathrm{metric}\left(s\right)={\left|Z_{\mathrm{FFT}}{\left(k\right)|}_s^i\right|}^2.$

Step 7,1 comparator of employing, maximum and default thresholding that step 6 is searched for compare, if surpass default thresholding, then successfully catch the PN phase place, finish synchronously, forward step 9 to; Otherwise i=i+1, n=0 returns step 2, until i=15.

Step 8, if the maximum of 16 kinds of PN pattern correspondences all have to surpass default thresholding, s=s+1 then receives the signal original position chip of delaying time, and returns step 1.

Step 9, record current time s and corresponding PN pattern i; And according to the maximum position

To received signal and the frequency offseting value that exists between the local PN sequence

Estimate:

When

The time,

When

The time,

T wherein _cBeing the chip period of single-time sampling, is 1/1228800 second in the system;

Be invariant; Frequency offseting value

Estimation can adopt 1 comparator and 1 multiplier to realize.

Above-described embodiment is example with the single-time sampling, is preferred implementation of the present invention, but embodiments of the present invention are not restricted to the described embodiments, for example the principle of many times of over-samplings with realize and can on the described basis of present embodiment, simple extension obtain; Other any do not deviate from change, the modification done under spiritual essence of the present invention and the principle, substitutes, combination, simplify, and all should be the substitute mode of equivalence, is included within protection scope of the present invention.

Claims (7)

1. be used for the down link synchronisation method of CDMA20001x EV-DO system, it is characterized in that may further comprise the steps:

Step 1, be the data in initial M half crack of reception signal buffer memory with current time s, extract the data of each half crack pilot frequency burst position respectively;

Step 2, make n=0, i=0 number is n relevant the adding up of PN intercept data of i with the data that receive n half crack of signal pilot frequency burst position and local PN pattern, obtains 1 spot correlation accumulation result;

Step 3, make n=n+1, repeating step 2 until n=M-1, obtains M-1 spot correlation accumulation result;

Step 4, with the M spot correlation accumulation result end zero padding of step 2 and step 3 gained to the N point, carry out the FFT conversion, obtain N point transformation result, wherein M＜N and N are 2 integral number power;

Step 5, N point transformation result is asked for mould value square, obtain N point mould value result;

The N point mould value result's that step 6, search step 5 obtain maximum;

Step 7, maximum and default thresholding that step 6 is searched for compare, if surpass default thresholding, then successfully catch the PN phase place; Otherwise i=i+1, n=0 returns step 2, until i=15;

Step 8, if the maximum of 16 kinds of PN pattern correspondences all have to surpass default thresholding, s=s+1 then receives the signal original position chip of delaying time, and returns step 1;

Described PN pattern refers to the sequence that obtains after the PN sequence intercepting of different biased exponents; The position of pilot burst is the PN intercept in each half crack, and the PN intercept that is numbered Pi represents that biased exponent is first segment data after the PN sequence intercepting of i, i=0 wherein, and 1 ..., 511.

2. the down link synchronisation method for CDMA20001x EV-DO system according to claim 1, it is characterized in that: the length of the described PN intercept of step 2 data is got 1 to 96 any value in the chip.

3. the down link synchronisation method for CDMA20001x EV-DO system according to claim 2, it is characterized in that: the length of the described PN intercept of step 2 data is got 96 chips; The relevant matched filter that uses 96 complex tap in the programming device that is accumulated in is realized.

4. the down link synchronisation method for CDMA20001x EV-DO system according to claim 1, it is characterized in that: the described FFT conversion of step 4 is used special-purpose FFT chip or use Nlog in programming device ₂N complex multiplier and 2Nlog ₂N complex adder realizes.

5. the down link synchronisation method for CDMA20001x EV-DO system according to claim 1 is characterized in that: asking for by 2N real multipliers and N real add musical instruments used in a Buddhist or Taoist mass of the described mould value of step 5 square realizes.

6. according to each described down link synchronisation method for CDMA2000 1x EV-DO system among the claim 1-5, it is characterized in that, after step 7 is successfully caught the PN phase place, also carry out:

Step 9, the position that in N point mould value result, occurs according to maximum

To received signal and the frequency offseting value that exists between the local PN sequence

Estimate:

When

The time,

When

The time, T wherein _cChip period for single-time sampling.

7. the down link synchronisation method for CDMA2000 1x EV-DO system according to claim 6 is characterized in that: the described frequency offseting value of step 9

Estimation adopt 1 comparator and 1 multiplier to realize.

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