CN101699628B - Silicon-coated insulated transistor with double super-shallow isolation structures and manufacturing method thereof - Google Patents
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Abstract
The invention discloses a silicon transistor on an insulator with double super-shallow isolation structures and a manufacturing method thereof. The manufacturing method comprises the following steps: firstly, providing a silicon substrate on the insulator which comprises a silicon layer, forming a first super-shallow channel structure and a second super-shallow channel structure in the silicon layer, forming a first type doped region serving as a collector electrode, and forming a second type light doped region serving as a base electrode in the silicon layer between the two super-shallow channel structures; secondly, forming a second type doped region in the silicon layer to make the first and second doped regions adjacent to the first and second super-shallow channel structures and the second type light doped region; and finally, forming a first type emitting electrode structure on the surface of the second type light doped region. The internal resistance of a base electrode connecting wire connected with the base electrode is decreased so as to improve the current driving force of a whole device.
Description
Technical field
The present invention relates to a kind of transistorized manufacture method, particularly about a kind of silicon-on-insulator transistor and preparation method thereof with double super-shallow isolation structures.
Background technology
Common metal oxide semiconductor (MOS) device is because the characteristic of low power consumption and high integration, it has been widely used in integrated circuit (IC) design and the making, yet MOS device and bipolar junction transistor (BJT) device relatively, and it is withstand voltage, service speed, current driving capability are all inferior than BJT device.So some stress at a high speed, the IC application scenario of high withstand voltage, big current drives and analog circuit, still mostly cooperate and adopt the BJT device, power transistor IC for example, electronic power switch IC device etc.
Known the BJT device architecture vertical view and the structure cutaway view that are produced on the NPN on silicon-on-insulator (SOI) substrate are respectively as Fig. 1 and shown in Figure 2.This SOI substrate 10 comprises a slice silicon substrate 12, one layer insulating 14 and one deck silicon layer 16, be formed with shallow channel (STI) structure 18 around the silicon layer 16, above-mentioned silicon layer 16 is positioned at the top of SOI substrate 10, in this silicon layer 16, be formed with a N type doped region 20 respectively as collector electrode, a P type light doping section 22 and a P type doped region 24 that is connected lead as base stage as base stage, this P type light doping section 22 is between N type doped region 20 and P type doped region 24, then be provided with in addition a heavily doped P type polysilicon layer 26, in order to as emitter on the surface of P type light doping section 22.Because the type of flow of charge carrier can influence the electrical property efficiency of entire device, so in this known BJT structure, when charge carrier when P type doped region 24 flow to the base stage, because P type doped region 24 is excessive with the adjacent surface of P type light doping section 22, cause base resistance excessive, and the current driving capability of entire device can't further be promoted.For the interface of N type doped region 20,,, easily produce breakdown effect in addition so breakdown voltage herein is lower because electric current herein is bigger with P type light doping section 22.
Therefore, the present invention is directed to above-mentioned technical problem, propose a kind of silicon-on-insulator transistor and preparation method thereof, effectively to overcome the problems of the prior art with double super-shallow isolation structures.
Summary of the invention
Main purpose of the present invention is to provide a kind of silicon-on-insulator transistor with double super-shallow isolation structures and preparation method thereof, it sets up a super shallow channel structure respectively in the base stage both sides, breakdown voltage between base stage and the collector electrode is improved, the internal resistance that can make the base stage that is connected with base stage connect lead again diminishes, to improve the current driving capability of entire device.
For reaching above-mentioned purpose, the invention provides a kind of silicon-on-insulator transistor with double super-shallow isolation structures, it comprises: a slice silicon-on-insulator substrate, this substrate comprises one deck silicon layer, be formed with isolation structure around this silicon layer, in silicon layer, also be provided with first a type doped region as collector electrode, the second type doped region, first, the second surpass shallow channel structure and second a type light doping section as base stage, wherein first, the second type doped region is adjacent to each other, first, the second surpass the shallow channel structure respectively with first, the second type doped region adjacency, and the second type light doping section is positioned at first, the second surpass between the shallow channel structure, and with first, the second type doped region adjacency, also be provided with the first type emitter structure in addition on this silicon-on-insulator substrate, this structure is positioned at the second type surface of adulteration area.
The present invention also provides a kind of manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures, a slice silicon-on-insulator substrate at first is provided, it comprises one deck silicon layer, around silicon layer, be formed with isolation structure, then in silicon layer, form first, second super shallow channel structure, in silicon layer, form first a type doped region afterwards as collector electrode, with with the first surpass shallow channel structure adjacency, and in the silicon layer between first, second super shallow channel structure, form second a type light doping section as base stage, with the first type doped region adjacency.Then in silicon layer, form the second type doped region then, with the first type doped region, the second type light doping section, the second surpass shallow channel structure adjacency, the last first type emitter structure that forms on the surface of the second type light doping section.
Further understand and understanding for the auditor is had architectural feature of the present invention and beneficial effect thereof, sincerely help with preferred embodiment figure and cooperate embodiment to be described in detail, illustrate as after.
Description of drawings
Fig. 1 is the silicon-on-insulator transistor structure vertical view in the background technology.
Fig. 2 is along the structure cutaway view of A-A ' tangent line in the silicon-on-insulator transistor of Fig. 1.
Fig. 3 is the structure vertical view of the first embodiment of the present invention.
Fig. 4 is along the structure cutaway view of B-B ' tangent line among first embodiment of Fig. 3.
Fig. 5 (a) makes each step structure cutaway view of first embodiment for the present invention to Fig. 5 (e).
Fig. 6 is the structure vertical view of the second embodiment of the present invention.
Fig. 7 is along the structure cutaway view of C-C ' tangent line among second embodiment of Fig. 6.
Fig. 8 (a) makes each step structure cutaway view of second embodiment for the present invention to Fig. 8 (h).
Description of symbols among the figure:
10 silicon-on-insulator substrates, 12 silicon substrates
14 insulating barriers, 16 silicon layers
18 shallow channel structures, 20 N type doped regions
22 P type light doping sections, 24 P type doped regions
26 polysilicon layers, 28 N type doped regions
30 P type doped regions 32 the first surpass the shallow channel structure
34 the second surpass shallow channel structure 36 P type light doping sections
38 N type emitter structures, 40 light dope deep-well region
44 second heavy doping shallow well districts, 42 first heavy doping shallow well districts
Embodiment
The present invention has mainly set up super shallow channel structure (VSTI) more and has improved the device current actuating force in transistor, below introduce the first embodiment of the present invention earlier, sees also Fig. 3 and Fig. 4, and Fig. 4 is the cutaway view of Fig. 3 along B-B ' tangent line.
Because silicon-on-insulator transistor can be divided into NPN transistor or PNP transistor, but no matter be which kind of transistor, its structure is all identical, and only material has N type or P type two species diversity, below introduces NPN transistor earlier.
Silicon-on-insulator transistor of the present invention comprises a slice silicon-on-insulator substrate 10, it comprises silicon substrate 12, insulating barrier 14, silicon layer 16, silicon substrate 12 is positioned at bottommost, silicon layer 16 is positioned at the top, 14 of insulating barriers also are formed with square shallow channel (STI) structure 18 in addition around silicon layer 16 between silicon substrate 12 and silicon layer 16.
Transistor has also comprised a N type doped region 28 as collector electrode, a P type doped region 30 that connects lead as base stage, first, the second surpass shallow channel structure 32,34, one as base stage and the doping content P type light doping section 36 low than P type doped region 30, it all is arranged in silicon layer 16, in addition, P type light doping section 36 is between first, the second surpass shallow channel structure 32, between 34, P type light doping section 36 and N type doped region 28 again, P type doped region 30, first, the second surpass shallow channel structure 32,34 adjacency, the N type, P type doped region 28,30 respectively with first, the second surpass shallow channel structure 32,34 adjacency, P type doped region 30 is adjacent to each other with N type doped region 28.
Also be provided with N type emitter structure 38 in addition on silicon-on-insulator substrate 10, it is heavily doped polysilicon emitter structure, and it is positioned at the surface of P type light doping section 36, and first, second super shallow channel structure 32,34 of cover part.
In the device size design, the width a of shallow channel structure 18 is 0.5 micron; The width b of first, second super shallow channel structure 32,34 is 0.3 micron; The width c of P type light doping section 36 is 0.32 micron; Width d between the N type doped region 28 that the first surpasses shallow channel structure 32 and shallow channel structure 18 is 0.3 micron; Width d between the P type doped region 30 that the second surpasses shallow channel structure 34 and shallow channel structure 18 is 0.3 micron; P type doped region 30 and P type light doping section 36 overlapping width e are 0.1 micron; The width f of N type emitter structure 38 is 0.62 micron.
Because overlapping width e is 0.1 micron, in other words, between P type doped region 30 and base stage, set up more and the second surpassed the area that shallow channel structure 34 can significantly reduce the adjacent surface of P type doped region 30 and base stage, the internal resistance value that connects the P type doped region 30 of lead as base stage is diminished, to improve the current driving capability of entire device.In addition, between N type doped region 28 and base stage, set up more and the first surpass shallow channel structure 32 breakdown voltage between base stage and the collector electrode is improved, to reduce the probability that device produces collapse.
So far the structure introduction of NPN transistor finishes, if will consult the transistorized structure of PNP, only need above-mentioned N type doped region 28, P type doped region 30, P type light doping section 36 are replaced getting final product with P type doped region, N type doped region, N type light doping section, P type emitter structure respectively with N type emitter structure 38.Similarly, for any NPN transistor embodiment described below, its corresponding PNP transistor all can utilize this species diversity to replace getting final product with expression.
Below continue to introduce the manufacture method of above-mentioned NPN transistor first embodiment, see also Fig. 5 (a) to Fig. 5 (e), at first shown in Fig. 5 (a), a slice silicon-on-insulator substrate 10 is provided, it comprises silicon substrate 12, insulating barrier 14, silicon layer 16, and silicon substrate 12 is positioned at bottommost, and silicon layer 16 is positioned at the top, 14 of insulating barriers also are formed with square shallow channel structure 18 in addition around silicon layer 16 between silicon substrate 12 and silicon layer 16.Then shown in Fig. 5 (b), in silicon layer 16, form first, second super shallow channel structure 32,34.Afterwards shown in Fig. 5 (c), in silicon layer 16, form a N type doped region 28 as collector electrode, with with the first surpass shallow channel structure 32 adjacency, and in the silicon layer 16 between first, second super shallow channel structure 32,34, form a P type light doping section 36 as base stage, with N type doped region 28, first, second super shallow channel structure 32,34 adjacency.Then shown in Fig. 5 (d), in silicon layer 16, form a P type doped region 30, with N type doped region 28, P type light doping section 36, the second surpass shallow channel structure 34 adjacency.Last shown in Fig. 5 (e), form a N type emitter structure 38 on the surface of P type light doping section 36, and first, second super shallow channel structure 32,34 of these emitter structure 38 cover parts.
The silicon-on-insulator substrate 10 that is provided with shallow channel structure 18 as the step of Fig. 5 (a) for a slice directly is provided in above-mentioned manufacture method, in addition, also available another kind of method replaces this step.At first can provide silicon substrate 12, then just on this silicon substrate 12, form insulating barrier 14 and silicon layer 16 in regular turn, around silicon layer 16, form shallow channel structure 18 more at last and just finish this step.
So far the manufacture method introduction of NPN transistor finishes, if will understand the transistorized manufacture method of PNP, only need above-mentioned N type doped region 28, P type doped region 30, P type light doping section 36 are replaced getting final product with P type doped region, N type doped region, N type light doping section, P type emitter structure respectively with N type emitter structure 38.Similarly, for the manufacture method of any NPN transistor embodiment described below, the transistorized manufacture method of its corresponding PNP all can utilize this species diversity to replace expression to get final product.
For the N type doped region 28 and the internal resistance value of P type doped region 30 are even lower, below introduce the NPN transistor of the second embodiment of the present invention, see also Fig. 6 and Fig. 7, Fig. 7 is the cutaway view of Fig. 6 along C-C ' tangent line.
Second embodiment and the first embodiment difference only are to have set up a light dope deep-well region 40 more, first, the second heavy doping shallow well district 42,44, wherein light dope deep-well region 40 and N type doped region 28 homotypes, and be arranged in N type doped region 28, and with the first surpass shallow channel structure 32, shallow channel structure 18 adjacency, the first heavy doping shallow well district 42 and N type doped region 28 homotypes, and in the light dope deep-well region 42 that the first surpasses between shallow channel structure 32 and the shallow channel structure 18, and with the first surpass shallow channel structure 32, shallow channel structure 18 adjacency, the other second heavy doping shallow well district 44 and P type doped region 30 homotypes, and in the P type doped region 30 that the second surpasses between shallow channel structure 34 and the shallow channel structure 18, and with the second surpass shallow channel structure 34, shallow channel structure 18 adjacency.
In addition, the difference in the device size design only is that the width d in first, second heavy doping shallow well district 42,44 is 0.3 micron.
In other words, the light dope deep-well region 40 and the first heavy doping shallow well district 42 in N type doped region 28, have been set up more, in P type doped region 30, set up the second heavy doping shallow well district 44 more, this kind change can make the N type doped region 28 and the internal resistance value of P type doped region 30 be even lower, and makes the current driving capability of device bigger.
This second embodiment can only lack the light dope deep-well region 40 and the first heavy doping shallow well district 42, or only lacks the second heavy doping shallow well district 44, and the internal resistance value of N type doped region 28 or P type doped region 30 is reduced.
Please continue to consult the manufacture method of second embodiment of the invention, to shown in Fig. 8 (h), wherein Fig. 8 (a) is identical to the step of Fig. 5 (c) with Fig. 5 (a) to Fig. 8 (c), so repeat no more as Fig. 8 (a).Then as Fig. 8 (d) shown in, the light dope deep-well region 40 of one of formation and N type doped region 28 homotypes in N type doped region 28, with the first surpass shallow channel structure 32, shallow channel structure 18 adjacency.Afterwards shown in Fig. 8 (e), in the light dope deep-well region 40 that the first surpasses between shallow channel structure 32 and the shallow channel structure 18, forming first a heavy doping shallow well district 42 with N type doped region 28 homotypes, with the first surpass shallow channel structure 32, shallow channel structure 18 adjacency.Then shown in Fig. 8 (f), in silicon layer 16, form a P type doped region 30, with N type doped region 28, P type light doping section 36, the second surpass shallow channel structure 34 adjacency.Next step is then shown in Fig. 8 (g), also can form second a heavy doping shallow well district 44 with P type doped region 30 homotypes between the second surpassing P type doped region 30 between shallow channel structure 34 and the shallow channel structure 18, with the second surpass shallow channel structure 34, shallow channel structure 18 adjacency.Last shown in Fig. 8 (h), form a N type emitter structure 38 on the surface of P type light doping section 36, and first, second super shallow channel structure 32,34 of these emitter structure 38 cover parts.
When this transistorized second embodiment only lacks the light dope deep-well region 40 and the first heavy doping shallow well district 42, only need in above-mentioned manufacture method, omit the step of Fig. 8 (d) and Fig. 8 (e).When this second embodiment only lacked the second heavy doping shallow well district 44, the step that only need omit Fig. 8 (g) in above-mentioned manufacture method got final product.
In sum, the present invention sets up super shallow channel structure respectively in the base stage both sides, and the breakdown voltage between base stage and the collector electrode is improved, and the internal resistance that can make the base stage that is connected with base stage connect lead again diminishes, to improve the current driving capability of entire device.
The above person is preferred embodiment of the present invention only, is not to be used for limiting scope of the invention process, so any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (22)
1. the silicon-on-insulator transistor with double super-shallow isolation structures is characterized in that, comprises:
A slice silicon-on-insulator substrate, it comprises one deck silicon layer, is formed with isolation structure around the described silicon layer;
The first type doped region, it is arranged in described silicon layer, as collector electrode;
The second type doped region, it is arranged in described silicon layer, and with the described first type doped region adjacency;
First super-shallow isolation structures, it is arranged in described silicon layer, and with the described first type doped region adjacency;
Second super-shallow isolation structures, it is arranged in described silicon layer, and with the described second type doped region adjacency;
The second type light doping section, its between described first, second super-shallow isolation structures, and with described first, second type doped region adjacency, with as base stage; And
The first type emitter structure, it is positioned on the described silicon-on-insulator substrate, and is positioned at the surface of the described second type light doping section.
2. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1 is characterized in that, also comprises: a light dope deep-well region, and itself and the described first type doped region homotype, and be arranged in the described first type doped region; And a heavy doping shallow well district, itself and the described first type doped region homotype, and in the described light dope deep-well region between described first super-shallow isolation structures and described isolation structure.
3. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1, it is characterized in that, also comprise: more comprise a heavy doping shallow well district, itself and the described second type doped region homotype, and in the described second type doped region between described second super-shallow isolation structures and described isolation structure.
4. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1 is characterized in that: described silicon-on-insulator substrate also comprises: a slice silicon substrate; And a layer insulating, it is positioned on the described silicon substrate, and between described silicon layer and described silicon substrate.
5. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1, it is characterized in that: the described first type doped region, the described first type emitter structure are respectively P type doped region, P type emitter structure, and the then described second type doped region, the described second type light doping section are N type doped region, N type light doping section.
6. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1, it is characterized in that: the described first type doped region, the described first type emitter structure are respectively N type doped region, N type emitter-base bandgap grading structure, and the then described second type doped region, the described second type light doping section are P type doped region, P type light doping section.
7. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1 is characterized in that: the doping content of the described second type doped region is higher than the doping content of the described second type light doping section.
8. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1 is characterized in that: the described first type emitter structure is heavily doped polysilicon emitter structure.
9. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1 is characterized in that: described first, second super-shallow isolation structures is super shallow channel structure.
10. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1 is characterized in that: described isolation structure is the shallow channel structure.
11. the silicon-on-insulator transistor with double super-shallow isolation structures according to claim 1 is characterized in that: described isolation structure is square isolation structure, and is positioned at around the described silicon layer.
12. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures is characterized in that, comprises the following steps:
(A) provide a slice silicon-on-insulator substrate, it comprises one deck silicon layer, is formed with isolation structure around described silicon layer;
(B) in described silicon layer, form first, second super-shallow isolation structures;
(C) in described silicon layer, form first a type doped region as collector electrode, with with the described first super-shallow isolation structures adjacency, and in the described silicon layer between described first, second super-shallow isolation structures, form second a type light doping section as base stage, with the described first type doped region adjacency;
(D) in described silicon layer, form the second type doped region, with the described first type doped region, the described second type light doping section, the described second super-shallow isolation structures adjacency; And
(E) form the first type emitter structure on the surface of the described second type light doping section.
13. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12, it is characterized in that: after described step (C) is carried out, and before described step (D) is carried out, in the described first type doped region, form a light dope deep-well region with the described first type doped region homotype, then the heavy doping shallow well district of one of formation and the described first type doped region homotype in the described light dope deep-well region between described first super-shallow isolation structures and described isolation structure.
14. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12, it is characterized in that: after described step (D) is carried out, and before described step (E) is carried out, form a heavy doping shallow well district with the described second type doped region homotype at the described second type doped region between described second super-shallow isolation structures and described isolation structure.
15. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12 is characterized in that: described step (A) comprises the following step:
(A1) provide a slice silicon substrate;
(A2) on described silicon substrate, form a layer insulating;
(A3) on described insulating barrier, form described silicon layer; And
(A4) around described silicon layer, form described isolation structure.
16. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12, it is characterized in that: the described first type doped region, the described first type emitter structure are respectively P type doped region, P type emitter structure, and the then described second type doped region, the described second type light doping section are N type doped region, N type light doping section.
17. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12, it is characterized in that: the described first type doped region, the described first type emitter structure are respectively N type doped region, N type emitter structure, and the then described second type doped region, the described second type light doping section are P type doped region, P type light doping section.
18. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12 is characterized in that: the doping content of the described second type doped region is higher than the doping content of the described second type light doping section.
19. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12 is characterized in that: the described first type emitter structure is heavily doped polysilicon emitter structure.
20. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12 is characterized in that: described first, second super-shallow isolation structures is super shallow channel structure.
21. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12 is characterized in that: described isolation structure is the shallow channel structure.
22. the manufacture method with silicon-on-insulator transistor of double super-shallow isolation structures according to claim 12 is characterized in that: described isolation structure is square isolation structure, and is positioned at around the described silicon layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040058503A1 (en) * | 2002-09-24 | 2004-03-25 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
| US20060008223A1 (en) * | 2003-08-15 | 2006-01-12 | Luxtera, Inc | PN diode optical modulators fabricated in rib waveguides |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040058503A1 (en) * | 2002-09-24 | 2004-03-25 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
| US20060008223A1 (en) * | 2003-08-15 | 2006-01-12 | Luxtera, Inc | PN diode optical modulators fabricated in rib waveguides |
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| JP特开2000-183074A 2000.06.30 |
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