CN101692647B - Tunnel forwarding system in which IPv4 packets are encapsulated by IPv6 head in router - Google Patents
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Abstract
The invention provides a tunnel forwarding system in which IPv4 (Internet Protocol version 4) packets are encapsulated by an IPv6 (Internet Protocol version 6) head in a router and belongs to the technical field of IPv6 routers. The invention is characterized in that the tunnel forwarding system consists of an FPGA-based (Field Programmable Gate Array) tunnel processing circuit, two CAMs (Content Addressable Memories) in cascaded connection, two one-port SRAMs (Static Random Access Memories), a double-port SRAM and a CPU control unit with the supported capacity of a V6 routing table being 64k*288bits in the maximum and the guaranteed line rate of forwarding being 3.2Gbit/s when the clock frequency is 100MHZ. A routing lookup table constructed by the CAM supports the dynamic allocation of the entry number and is responsible for the read-write and maintenance of the routing table at the same time. If IP data packets received by the tunnel forwarding system are V4 packets, the V4 packets are encapsulated with a V6 packet head to form V6 tunneling packets; if the IP data packets are V6 data packets, the V6 data packets dispense with the transformation; then, the lookup information of the packets are extracted, and the routing lookup is carried out; and the packets are processed according to the returned results: forwarding on a V4 or V6 basis, and turning over to the CPU to process or discard.
Description
Technical field
Adopt the tunnel repeater system of IPv6 head encapsulation IPv4 bag to belong to Next Generation Internet IPv6 high-performance core router technical field in the router.
Background technology
The IPv6 agreement has solved that the IPv4 protocol address is exhausted, fail safe is not enough and problem such as poor mobility.Carrying out the transition to IPv6 from IPv4 is a progressive and very long process, and both will coexist the long duration.Along with the extensive development of IPv6, the last introducing of IPv6 a large number of services pure IPv6 backbone network appears.Because the incompatibility of IPv6 and IPv4 agreement, after the existing network user is moved to pure IPv6 network, can't with the resourceful IPv4 network interconnection.This make former IPv4 network user and resource migration to the process of IPv6 network very slowly, the pure IPv6 network usage that causes having built up is not high.In order to promote the transition of IPv4-IPv6 network, to be badly in need of a kind of IPv4 and IPv6 network can realized and to exchange visits, the IPv4 packet is through the tunneling technique or the protocol conversion technology of IPv6 Network Transmission.
Adopt the tunneling technique of IPv4 protocol encapsulation IPv6 message to use wider at present; Also ripe, the tunneling technique of IPv6 protocol encapsulation IPv4 message is then not mature enough, adopts the tunneling technique of IPv6 head encapsulation IPv4 message also not have unified international standard at present; Some adopt the tunneling technique major part of IPv6 head encapsulation IPv4 message to realize with software on the market; The architecture of encapsulation has nothing in common with each other, and speed is low, can not satisfy the practical application needs of express network.
The present invention realizes adopting in the router tunnel of IPv6 head encapsulation IPv4 bag to transmit, and solves the IPv4 network and realizes interconnected problem through pure IPv6 backbone network, and method is simple, efficient, reaches encapsulation and the forwarding speed of 3.2Gbit/s.
FPGA (Field Programmable Gate Array) is the extensive programmable digital IC-components of bringing into use the end of the eighties in last century.It makes full use of exploitation and the application that Computer-aided Design Technology is carried out device.The user also can carry out functional simulation and real-time simulation on computers by means of computer design special IC chip voluntarily, in time pinpoints the problems, and the adjustment circuit improves design.Like this, the designer needn't start strap circuits, debugging checking, need only operate on computers the very short time, can design the ideal circuit very nearly the same with real system.And the FPGA device adopts standardized structural, volume is little, integrated level is high, low in energy consumption, speed is fast, can unlimited programming repeatedly, therefore, become the first-selected device of scientific research product development and miniaturization thereof, its application is very extensive.
CAM (Content Addressable Memory) is a kind of special memory; It will be imported all data item of storing among data and the CAM and walk abreast simultaneously relatively; Judge rapidly the input data whether with CAM in the stored data items coupling, and provide data item corresponding address and match information.CAM is the device that uses maximum realization fast routing lookups at present; CAM can accomplish the exact-match lookup of keyword at limited several hardware clock in the cycle; If employing pile line operation; Keyword of searching of each clock cycle input, then CAM can be at lookup result of each hardware clock cycle flowing water output.
TCAM (Ternary Content Addressable Memory) also is a kind of CAM; But its each bank bit has three kinds of states: 0,1 or X (being indifferent to); Each list item all comprises numerical value Bit String and mask bit string, therefore can be used for confirming longest prefix match.
Summary of the invention
The object of the invention is to provide the tunnel repeater system that adopts IPv6 head encapsulation IPv4 bag in a kind of router, and FPGA and CAM technology are adopted in concrete realization.Adopt router of the present invention can connect IPv6 backbone network and IPv4 isolated island, realize passing through between the IPv4 isolated island transparent transmission of IPv6 backbone network.
Characteristic of the present invention:
Contain: tunnel treatment circuit, SRAM one-port memory, SRAM dual-ported memory, CAM Content Addressable Memory and a CPU control unit that is integrated on the fpga chip, wherein:
Described tunnel treatment circuit; Contain: IP packet input interface circuit, packet filtering circuit, bag input rank memory FIFO, IPv6 protocol encapsulation circuit, IPv6 bag queue memory FIFO, packet-related information extract circuit, search instruction queue memory FIFO, CAM control circuit, result for retrieval queue memory FIFO, IPv6 packet relevant information queue memory FIFO, IPv6 packet memory RAM, bag transtation mission circuit, CAM maintenance instruction queue memory FIFO, the 0th and submit bag queue memory FIFO, the 1st and submit bag queue memory FIFO, submit bag transtation mission circuit and cpu interface circuit, wherein:
IP packet input interface circuit; Input receives the ready for data signal and the data bus signal of higher level's physical and datalink layer treatment circuit output; The output read signal is given higher level's physical and datalink layer treatment circuit; The input of said IP packet input interface circuit data output and packet filtering circuit links to each other; The IPv4 of input and output and IPv6 packet header signal and bag tail signal are counted respectively, the tail count output signal is wrapped in packet header send to cpu interface circuit, and receive the reset signal sum counter reset signal of cpu interface circuit input;
The packet filtering circuit; Input links to each other with IP packet input interface circuit; Also submit bag queue memory FIFO with the 0th respectively, the fast signal of expiring of bag input rank memory FIFO output links to each other; Output is submitted the input of bag queue memory FIFO with the 0th respectively, the input of bag input rank memory FIFO links to each other; Packet header signal and bag tail signal to input and output are counted, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;
Bag input rank memory FIFO is a fifo queue memory, and data width is 36, and input links to each other with the IP bag output of above-mentioned packet filtering circuit, and read signal is from IPv6 protocol encapsulation circuit, and reset signal is from cpu interface circuit;
IPv6 protocol encapsulation circuit; Input links to each other with said bag input rank memory FIFO; Output links to each other with IPv6 bag queue memory FIFO, and input also receives the fast signal of expiring of IPv6 bag queue memory FIFO output in addition, and IPv6 protocol encapsulation circuit is counted the packet header signal and the bag tail signal of input and output; And send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;
IPv6 bag queue memory FIFO; It is a fifo queue memory; Data width is 40, and data input pin links to each other with above-mentioned IP v6 protocol encapsulation circuit, reads input signal and links to each other with the output of reading that packet-related information extracts circuit; Output extracts circuit with packet-related information and links to each other, and reset signal is from cpu interface circuit;
Packet-related information extracts circuit; Input links to each other with the output of IPv6 bag queue memory; Output links to each other with search instruction queue stores FIFO, IPv6 packet memory RAM, IPv6 packet relevant information queue memory FIFO respectively; Packet header signal and bag tail signal to input and output are counted, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;
Search instruction queue memory FIFO; Be a fifo queue memory, data width is 100, and data input pin extracts circuit with above-mentioned packet-related information and links to each other; The output of reading of reading input signal and CAM control circuit links to each other, and data output end links to each other with the CAM control circuit;
The CAM control circuit; Input links to each other with search instruction queue memory FIFO output, CAM maintenance instruction queue memory FIFO output respectively; The CAM memory read/write control command bus signals and the bi-directional data request bus REQDATA signal of the output of CAM control circuit link to each other with the CAM memory; The CAM control circuit links to each other with the data/address bus of SRAM one-port memory; CAM control circuit input also with the reading confirmation signal, search matched signal, search the output useful signal and link to each other of CAM memory output; The retrieving information output of CAM control circuit output links to each other with result for retrieval queue memory FIFO, in addition the read signal of CAM control circuit respectively with search instruction queue memory FIFO read input, CAM maintenance instruction queue memory FIFO reads input and links to each other, CAM control circuit output links to each other with cpu interface circuit; The list item that routing table is preserved sends to cpu interface circuit; The CAM control circuit is counted the information of IPv6 route query times and query hit, and these information are sent to cpu interface circuit as query State information, and receives the reset signal sum counter reset signal of cpu interface circuit input;
Result for retrieval queue memory FIFO; Be a fifo queue memory, data width is 148, and data input pin links to each other with the output of CAM control circuit; The output of reading of reading input signal and bag transtation mission circuit links to each other, and the input of data output end and bag transtation mission circuit links to each other;
IPv6 packet relevant information queue memory FIFO; Be a fifo queue memory, data width is 60, and data input pin extracts circuit with above-mentioned packet-related information and links to each other; The output of reading of reading input signal and bag transtation mission circuit links to each other, and data output end and bag transtation mission circuit link to each other;
CAM maintenance instruction queue memory FIFO; Be a fifo queue memory, data width is 90, and data input pin links to each other with cpu interface circuit; The read signal of reading input signal and the output of CAM control circuit links to each other, and data output end links to each other with the data input pin of CAM control circuit;
The bag transtation mission circuit; Send read signal to result for retrieval queue memory FIFO, IPv6 packet relevant information queue memory FIFO respectively; And link to each other with the output of result for retrieval queue memory FIFO, IPv6 packet relevant information queue memory FIFO; The read signal of bag transtation mission circuit output, read the address and link to each other with IPv6 packet memory RAM; Data output end and the bag transtation mission circuit of IPv6 packet memory RAM link to each other, and the output of bag transtation mission circuit also submits bag queue memory FIFO with the 1st and the outer up FIFO of FPGA sheet links to each other, and the bag transtation mission circuit is counted respectively IPv4, IPv6 packet header signal and the bag tail signal of input and output; And send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;
IPv6 packet memory RAM is the interior read-write memory of the FPGA sheet of a dual-port; There are data to write port and a data output port; Data are write inbound port and are linked to each other with the IPv6 data output end that packet-related information extracts circuit; All signals and the bag transtation mission circuit of read port link to each other, and IPv6 packet memory RAM data width is 36, and reading-writing port has 14 address wires respectively;
Submit bag queue memory FIFO for the 0th; Be a fifo queue memory, data width is 36, and data input pin links to each other with above-mentioned packet filtering circuit; Read input signal and link to each other with the output of reading of submitting the bag transtation mission circuit, data output end wraps transtation mission circuit and links to each other with submitting;
Submit bag queue memory FIFO for the 1st; Be a fifo queue memory, data width is 36, and data input pin links to each other with the bag transtation mission circuit; Read input signal and link to each other with the output of reading of submitting the bag transtation mission circuit, data output end wraps transtation mission circuit and links to each other with submitting;
Submit the bag transtation mission circuit; Input is submitted bag queue memory FIFO, the 1st and is submitted bag queue memory FIFO and link to each other with the 0th; Data output end links to each other with the data input pin of SRAM dual-ported memory; The length signals output of submitting transferred data in CPU interrupt signal, SRAM dual-ported memory data initial address and termination address, the SRAM dual-ported memory that wraps the transtation mission circuit transmission links to each other with cpu interface circuit; Cpu interface circuit is exported to the CPU response signal input of submitting the bag transtation mission circuit; Submit the bag transtation mission circuit IPv4, IPv6 packet header signal and the bag tail signal of input and output are counted respectively, and send to cpu interface circuit, receive the reset signal sum counter reset signal of cpu interface circuit input simultaneously;
Cpu interface circuit; Link to each other with inner each circuit of the tunnel treatment circuit of realizing by FPGA; Receive IPv4, IPv6 input and output packet header signal and the bag tail signal-count of each circuit input; And the query State of CAM control circuit counting; Cpu interface circuit links to each other with cpu address bus, data/address bus, the read-write control signal of the outer CPU control unit of FPGA sheet; The interrupt signal of output and the interruption of CPU control unit input link to each other, and cpu interface circuit also links to each other with address bus, data/address bus, the read-write control signal of SRAM dual-ported memory data-out port, and cpu interface circuit receives the reset signal of CPU control unit input; And send reset signal in the FPGA other each circuit; Reset signal is sent to IP packet input interface circuit, packet filtering circuit, IPv6 protocol encapsulation circuit, packet-related information extraction circuit, CAM control circuit, submits bag transtation mission circuit, bag transtation mission circuit, and cpu interface circuit also links to each other with the data input pin of CAM maintenance instruction queue memory FIFO, receives the routing table list item data of CAM control circuit output; The length and the interrupt requests information of transferred data in the SRAM dual-ported memory data initial address that bag transtation mission circuit output is submitted in reception and termination address, the SRAM dual-ported memory are also to submitting bag transtation mission circuit transmission CPU interrupt response index signal;
Said packet filtering circuit is a circuit unit, wherein: input IP bag data register, input links to each other with the output of IP packet input interface circuit; The output of input IP bag data register links to each other with IPv4 packet register, IPv6 packet register respectively; The output of IPv4 packet register links to each other the also output of accepting state controller simultaneously with the input of IPv4 packet delay time register group, IPv4 packet header check and store device, life span register, bag type register, State Control machine respectively; The output of IPv4 packet delay time register group and the input of data selector A link to each other; The input of verification of IPv4 data packet head and maker upgrades register output with IPv4 the output of check and store device, life span respectively and links to each other; The output of life span register links to each other with the input of input that subtracts a subtracter A and State Control machine; The output that subtracts a subtracter A links to each other with the input that life span is upgraded register, and the output that life span is upgraded register links to each other with maker, State Control machine with the verification of IPv4 data packet head respectively; The input of data selector A links to each other with the output of output, the verification of IPv4 data packet head and the maker of IPv4 packet delay time register group and the output of State Control machine respectively again, the output of data selector A with upgrade after IPv4 packet register input link to each other;
The output of IPv6 packet register links to each other with the input of IPv6 packet delay time register group, jumping figure register, next stature register, IPv6 destination address register, State Control machine respectively, the also output of accepting state controller simultaneously; The output of jumping figure register links to each other with the input that subtracts a subtracter B and the State Control machine links to each other, and the output that jumping figure upgrades register also links to each other with the State Control machine; The output that subtracts a subtracter B links to each other with the input that jumping figure upgrades register; The input of data selector B links to each other with the output that IPv6 packet delay time register group, jumping figure are upgraded register, State Control machine respectively, and the IPv6 packet register input after the output of data selector B and the renewal links to each other; The input of next stature register links to each other with the output of IPv6 packet register, and output links to each other with the State Control machine; The output of IPv6 destination address register links to each other with the input of comparator, and another input of comparator links to each other with this router IPv6 address register output; The output of comparator links to each other with the input of State Control machine; The output of this router IPv6 address register input and cpu interface circuit links to each other;
The input of data selector C respectively with upgrade after IPv4 packet register, the output of IPv6 packet register after upgrading link to each other, the fast signal of expiring of State Control machine and bag input rank memory FIFO is continuous; The output of data selector C is submitted bag queue memory FIFO with the 0th respectively, bag input rank memory FIFO links to each other, and the packet header signal of while data selector C and bag tail the signal output part also input of sum counter link to each other; Counter receives the counter O reset signal of cpu interface circuit output, and the input that tail signal-count signal sends cpu interface circuit to is wrapped in packet header;
Said IPv6 protocol encapsulation circuit is a circuit unit; Wherein: bag input rank memory fifo interface circuit; The data output end of data input pin and bag input rank memory FIFO links to each other; The read signal of output and the input signal of reading of bag input rank memory FIFO link to each other, and the control input/output terminal links to each other with the State Control machine circuit; IPv4 header data register; Input and bag input rank memory fifo interface circuit output end and State Control machine circuit output link to each other; An output changes packet header, IPv6 tunnel circuit with IPv4 packet header and links to each other, and another output links to each other with the multi-channel data selector circuit input end; IPv4 load data register, input and bag input rank memory fifo interface circuit output end link to each other, and output links to each other with the multi-channel data selector circuit input end; The IPv6 data register, the output of input and bag input rank memory fifo interface circuit links to each other, and output links to each other with the multi-channel data selector circuit input end; Packet header, IPv6 tunnel data register, input changes IPv6 tunnel packet header circuit with IPv4 packet header and the State Control machine circuit links to each other, and output links to each other with the multi-channel data selector circuit; The output of multi-channel data selector circuit links to each other with the input of IPv6 bag queue memory FIFO; Bag input rank memory fifo interface circuit sends to counter circuit with the data packet head signal and the tail signal that receive; The multi-channel data selector circuit also sends the data packet head of output, bag tail signal to counter circuit; The input and output packet header bag tail signal-count of counter circuit output and the state counter value input of cpu interface circuit link to each other, and receive the counter O reset signal of cpu interface circuit input simultaneously;
It is a circuit unit that said packet-related information extracts circuit; Form by a series of circuit: IPv6 bag queue memory interface circuit; Said data input pin links to each other with IPv6 bag queue memory FIFO; The read signal of output links to each other with the input signal of reading of IPv6 bag queue memory FIFO; The control input/output terminal links to each other with the State Control machine circuit, and output is handed over marker register, packet priority register, bag source port numbered register, wraps initial address register, wrapped the termination address register, the packet number register, wraps destination address register, Tunnel Identifier register and bag and write the RAM circuit and link to each other with wrapping; The input of IPv6 package informatin transtation mission circuit hands over marker register, packet priority register, bag initial address register, bag source port numbered register, bag termination address register, packet number register to link to each other with said wrapping; Control information comes from the State Control machine, output termination IPv6 packet relevant information queue memory FIFO; The input of search instruction transtation mission circuit links to each other with packet number register, bag destination address register, Tunnel Identifier register, and output links to each other with search instruction queue memory FIFO, and the control input end links to each other with the State Control machine; The output that bag writes the RAM circuit links to each other with IPv6 packet memory RAM, and its control input end links to each other with the State Control machine; The input of counter links to each other with the input packet header signal and the input bag tail signal of IPv6 bag queue memory fifo interface circuit respectively; Also link to each other with packet header signal and the bag tail signal that bag writes RAM circuit output; Also link to each other with the counter O reset signal of cpu interface circuit input simultaneously, the packet header tail signal-count of output links to each other with cpu interface circuit;
Said CAM control circuit is a circuit unit; Be made up of a series of circuit: the data input pin of search instruction queue memory fifo interface circuit links to each other with search instruction queue memory FIFO output; The read signal of output and the read signal of search instruction queue memory FIFO link to each other; And output also interconnects with the State Control machine, the control signal of accepting state controller output; CAM writes the input of data register and the output of search instruction queue memory fifo interface circuit and CAM maintenance instruction queue memory fifo interface circuit links to each other, and output links to each other with CAM data/address bus read-write control circuit; The output of the output of the input of CAM operational order transtation mission circuit and search instruction queue memory fifo interface circuit, CAM maintenance instruction queue memory fifo interface circuit links to each other, and output directly links to each other with command line INST, LTIN, SEGSEL, GMASK, CRB and the request gating signal REQSTB of CAM memory; SRAM writes the input and the CAM maintenance instruction queue memory fifo interface circuit output end of data register, and the output of search instruction queue memory fifo interface circuit is continuous, and output links to each other with SRAM data/address bus read-write control circuit input; The output of SRAM data/address bus read-write control circuit links to each other with SRAM read data register, result for retrieval register and SRAM one-port memory, and output links to each other signal input end with state machine; The output of the input of CPU read data register and CAM read data register, the output of SRAM read data register link to each other, and output links to each other with cpu interface circuit; The input of result for retrieval register links to each other with the output of sequence of data packet register, and output links to each other with result for retrieval queue memory FIFO; The input of sequence of data packet register links to each other with the output of search instruction queue memory fifo interface circuit and the output of State Control machine; The input of counter links to each other with the output of result for retrieval register, and also the calculator reset signal with the cpu interface circuit input links to each other, and the query State counting output of its output links to each other with cpu interface circuit;
Said bag transtation mission circuit is a circuit unit; Form by a series of circuit: IPv6 packet relevant information queue memory fifo interface circuit; Data input pin links to each other with the output of IPv6 packet relevant information queue memory FIFO; The control input and output side links to each other with the state machine control circuit; The read signal of output is read input with IPv6 packet relevant information queue memory FIFO and is linked to each other, and output links to each other with the input of bag storage initial address register, bag storage termination address register, packet length register, packet priority register, source port numbered register, packet number register A respectively; Result for retrieval queue memory fifo interface circuit; Data input pin links to each other with the output of result for retrieval queue memory FIFO; The control input and output side links to each other with the state machine control circuit, and output links to each other with the input of packet number register B, destination interface numbered register, purpose ply-yarn drill numbered register, next-hop IP v6 address register, next-hop IP v4 address register, tunnel IPv6 destination address register respectively; Bit wide is that the input of 36 additional data registers group links to each other with the data output end of packet priority register, packet length register, source port numbered register, source ply-yarn drill numbered register, destination interface numbered register, purpose ply-yarn drill numbered register, next-hop IP v6 address register, next-hop IP v4 address register, tunnel IPv6 destination address register respectively; The input of source ply-yarn drill numbered register is from cpu interface circuit; Increase 10 adders, the output of input and bag storage initial address links to each other, and output links to each other with address register A; The output of the input of address register B and bag storage initial address links to each other; The output that increases 1 adder is read the output of address register with the IPv6 packet memory respectively, the input of address register C links to each other; Multi-channel data selector A, input link to each other with address register A, address register B, address register C respectively, and the control input end links to each other with the output of state machine control circuit, and output links to each other with the input that the IPv6 packet memory is read address register; Data comparator A, the output of input and bag storage termination address register and the output that the IPv6 packet memory is read address register link to each other, and output links to each other with the input of state machine control circuit; Bit wide is 36 an IP data register, and input links to each other with the data output end of IPv6 packet memory RAM, and output links to each other with the input of multi-channel data selector B; Multi-channel data selector B; Data input pin is that the output of 36 additional data registers group, the output of IP data register that bit wide is 36 link to each other with bit wide respectively, output with submit packet register, the IPv4 of band additional data or the input of IPv6 packet register and link to each other; The output of submitting the packet register links to each other with the 1st input of submitting bag queue memory FIFO; The output of the IPv4 of band additional data or IPv6 bag register mails to the up FIFO that links to each other with FPGA; IPv4 or the IPv6 bag register of band additional data also send the data packet head signal and the bag tail signal that send to counter respectively; Counter also links to each other with the counter O reset signal of cpu interface circuit input, and the packet header bag tail signal-count signal of counter output sends to cpu interface circuit;
Said CAM memory; It is the FPGA chip external memory of system; Read-write control command bus signals and request of data bus REQDATA signal are from the CAM control circuit; The address bus signal of output links to each other with read-write with the address bus of SRAM one-port memory respectively with read-write, the reading confirmation signal, search matched signal, search and export useful signal and link to each other with CAM control circuit input of output;
Said SRAM one-port memory is the outer static SRAM memory of FPGA sheet of system, and read-write input signal and address signal are from the output of CAM memory, and the data input/output terminal links to each other with the CAM control circuit;
Said SRAM dual-ported memory; It is the outer static dual-port SRAM memory of FPGA sheet of system; Be divided into data and write inbound port and data-out port; The BDB Bi-directional Data Bus that data are write inbound port with submit the bag transtation mission circuit and link to each other; Data are write reading writing signal line, the address bus of inbound port and are submitted the output that wraps transtation mission circuit and link to each other, and the BDB Bi-directional Data Bus of data-out port links to each other with cpu interface circuit, and the output of the reading writing signal line of data-out port, address bus and cpu interface circuit links to each other.
Through adopting the tunnel repeater system of IPv6 head encapsulation IPv4 bag in the router of said method structure; Be made up of a slice fpga chip EP1S25F780, two IDT75k62100 (TCAM), two IDT71T75602 (SRAM), a slice CY7C1300A (SRAM dual-ported memory) chip, FPGA and peripheral chip adopt same clock to carry out work.
FPGA has only a master clock CLK; When this clock frequency was 100MHZ, the reset signal of above-mentioned all modules came from cpu interface circuit, and the reset signal of cpu interface circuit comes from the CPU control unit; The clock of above-mentioned all modules all is CLK; But for avoiding repetition, do not carry in the above, the performance index that the tunnel repeater system that adopts IPv6 head encapsulation IPv4 to wrap in the router reaches are:
The shared master clock 100MHZ CLK of IDT75k62100 and FPGA, the operating frequency of two IDT71T75602 is 50MHZ, the clock source of this 50MHZ and main 100MHZ is identical, is that 100MHZ CLK master clock obtains through two divided-frequency;
Through utilizing the look-up table of CAM system construction, support the dynamic assignment of list item bar number, support the IPv6 route querying of IPv6 bag, system can guarantee with 3.2Gbit/s linear speed transceive data bag.
Through said method, the route querying device maximum of using two IDT75k62100 of a slice EP1S25780 and cascade to make up is supported the IPv6 route table items of 64K*288bits.
This tunnel transmission treatment system can process IP v6 tunneling data bag, IPv4 packet and the non-tunneling data bag of IPv6, maximum processing 32k byte data bag.System can guarantee 3.2Gbit/s linear speed transceive data bag, can packet loss if surpass 3.2Gbit/s, but the bag of not losing can correctly transmit, if packet rate is got back to 3.2Gbit/s again, and still can packet loss.
The whole bag of bag buffer memory is submitted in support.
Each circuit module in the FPGA and CAM system are controlled and safeguard through CPU.
Description of drawings
The tunnel repeater system that adopts IPv6 head encapsulation IPv4 bag in Fig. 1 router in the core router ply-yarn drill the position and with the relation of peripheral devices
Annexation between the chip of the tunnel repeater system of employing IPv6 head encapsulation IPv4 bag in Fig. 2 router
Relation in Fig. 3 router between each sub-circuit of the tunnel repeater system FPGA inside of employing IPv6 head encapsulation IPv4 bag
Fig. 4 packet filtering circuit
Fig. 5 IPv 6 protocol encapsulation circuit
Fig. 6 packet-related information extracts circuit
Fig. 7 CAM control circuit
Fig. 8 bag transtation mission circuit
The list item data structure of Fig. 9 CAM memory stores
Explain: 128 of purpose IPv6 addresses (127～0), Tunnel Identifier account for 1, retention position 0.
The list item data structure of Figure 10 SRAM one-port memory storage
Explain: sign (bit71～69): 000---IPv4 transmits; 001---submit; The common IPv6 of 010---abandoning 011---transmits; 100---the IPv6 tunnel is transmitted;
Purpose ply-yarn drill numbering: bit71～68; Destination interface numbering: bit67～64.
Totally 128 of IPv6 tunnel destination addresses are made up of bit63～0 of the 3rd and the 4th list item of SRAM one-port memory.
The PPP bag data structure that Figure 11 IP packet input interface circuit receives through higher level's processing of circuit
Data structure among Figure 12 bag input rank memory FIFO
Explain: (1) bit35～34 are the indication end to end of bag: 10---packet begins, and 00---the packet intermediate data, 01---packet finishes, and 11---packet error.Bit33～32 are the MOD territory; Last 32 effective byte indication; Only just meaningful when the bag tail: 00---last four bytes are all effective; 01---three bytes effective (bit31～8) in last four bytes, 10---two bytes effective (bit31～16) in last four bytes, 11---a byte effective (bit31～24) in last four bytes; Invalid bit is filled with 0.Bit31～31, the particular content of packet.
Data structure among Figure 13 IPv6 packet relevant information queue memory FIFO
Data structure among Figure 14 search instruction queue memory FIFO
Figure 15 CAM maintenance instruction queue memory data fifo structure
Data structure among Figure 16 result for retrieval queue memory FIFO
Figure 17 sends to the data structure of up FIFO
Explain: (1) bit35～34 are the indication end to end of bag: 10---packet begins, 0o---packet intermediate data, and 01---packet finishes, and 11---packet error.Bit33～32 are the MOD territory; Last 32 effective byte indication; Only just meaningful when the bag tail: 00---last four bytes are all effective; 01---three bytes effective (bit31～8) in last four bytes, 10---two bytes effective (bit31～16) in last four bytes, 11---a byte effective (bit31～24) in last four bytes; Invalid bit is filled with 0.Bit31～31, the particular content of packet.
(2) source position numbering: bit15～8, totally 8, bit11～8 identification sources port numberings wherein, bit15～12 identification sources ply-yarn drills numbering.
(3) destination interface numbering: bit19～8, totally 12, but only used bit11～8 at present, other position 0 is used for indicating the output port after packet arrives the target ply-yarn drill.
Figure 18 submits data structure
Explain: bit35～34 are the indication end to end of bag: 10---packet begins, and 00---the packet intermediate data, 01---packet finishes, and 11---packet error.Bit33～32 are the MOD territory; Last 32 effective byte indication; Only just meaningful when the bag tail: 00---last four bytes are all effective; 01---three bytes effective (bit31～8) in last four bytes, 10---two bytes effective (bit31～16) in last four bytes, 11---a byte effective (bit31～24) in last four bytes; Invalid bit is filled with 0.Bit31～31, the particular content of packet.
Figure 19 adopts the data structure of the tunneling data bag of IPv6 head encapsulation IPv4 message
Embodiment
The tunnel repeater system that adopts IPv6 head encapsulation IPv4 to wrap in the router is used on the interface card, solves the IPv4 network and realizes interconnected problem through pure IPv6 backbone network, the concrete employing FPGA technology that realizes.It realizes that by tunnel treatment circuit and external SRAM dual-ported memory chip, SRAM one-port memory chip, CAM memory chip, CPU control unit the tunnel treatment circuit is realized by a slice FPGA.Accompanying drawing 1 is seen in the position in the high-performance core router by this system, and it is as shown in Figure 2 to constitute between the chip of this system annexation.
Can know by figure; Adopt the tunnel repeater system of IPv6 head encapsulation IPv4 bag to receive packet in the router according to the ppp protocol encapsulation from physical and datalink layer treatment circuit; This packet only contains protocol domain, information field and region filling, and the tunnel transmission treatment system is extracted wherein pure IPv6 data message and IPv4 data message according to the protocol domain sign.The IPv4 data message is encapsulated, add the IPv6 data packet head, become IPv6 tunneling data bag; Destination address and jumping figure to the IPv6 data message check, gives CPU control unit for the IPv6 packet of this router on directly with destination address and handle.For destination address is not the IPv6 packet of this router; Therefrom extract route querying information; And will the information of searching submit to CAM and search system (CAM+SRAM) and search; The tunnel treatment circuit that constitutes by FPGA, according to searching the result who returns, decision to the IPv6 packet carry out common IPv6 transmit, adopt that the tunnel of IPv6 head encapsulation IPv4 bag is transmitted, IPv4 transmits, abandon or on give CPU and handle.The bag of transmitting sends to follow-up switching structure coprocessor through up FIF0 memory and switching fabric is handled.
After the tunnel transmission treatment system powered on, the CPU control unit carried out initialization through cpu interface circuit to whole system, and CAM is configured to 288 search patterns, and configuration SRAM list item.After initialization was accomplished, system just can operate as normal.
The storage bit wide of the single list item of CAM that system uses is 72, so the list item length of supporting is the integral multiple of 72bit, because the destination address of IPv6 bag is 128, therefore needs 2 content-addressable memory items to come the destination address of storing IP v6 bag at least.The IPv4 bag gets into after the router; When leaving router; If adopting the tunnel of IPv6 head encapsulation IPv4 bag transmits; System except the IPv6 address that the tunnel end outlet will be provided, also need provide tunnel packet leave behind the current router by way of next hop router IPv6 address, provide the SRAM of lookup result to need 256 at least like this.The list item length of the SRAM one-port memory support that system uses is the integral multiple of 72bit, like this since, in fact the memory capacity that provides of SRAM is 288, corresponding SRAM has 4 memory cell.288 SRAM must have 288 CAM pairings, could on sequential, mate, so system adopt 4 content-addressable memory items totally 288 represent a route table items.The bit71 of first list item～69 get 100; Explanation is the IPv6 list item, if bit68 gets 1, explains that what look into is the route with the tunnel packet of IPv6 encapsulation; If bit68 gets 0; Explain that what look into is the route of common IPv6 bag, bit67～64 reservation need not, the corresponding IPv6 destination address in bit63～0 high 64.The bit71 of second list item～64 reservation need not, the corresponding IPv6 destination address in bit63～0 low 64.Also have 2 list items keep need not, put 0, as shown in Figure 9.
Each route table items structure that the SRAM one-port memory that system uses is supported is shown in figure 10: the bit71 of first list item～69 constitute the flag of route searching results, are used to represent that the type of lookup result: IPv4 transmits, common IPv6 transmits, the IPv6 tunnel is transmitted, abandon, give CPU control unit on the data; Purpose ply-yarn drill numbering is made up of bit71～68 of second list item, totally 4, is used to represent that packet passes through the purpose ply-yarn drill that switching fabric will arrive; Destination interface numbering is made up of bit67～64, totally 4, be used to represent that the packet of transmitting arrives the purpose ply-yarn drill through switching fabric after, which port through ply-yarn drill sends; The bit63 of first list item and second list item～0 li storage be that next jumps destination address; If common IPv6 transmits, then the IP address of next jumping is 128, if IPv4 transmits; Then the IP address of next jumping is 32, and bit31～0 of having only second list item this moment effectively; Flag equals at 000 o'clock, and packet is transmitted with IPv4, equals at 001 o'clock, and packet is dropped, and equals at 010 o'clock, packet by on give CPU control unit, equal at 011 o'clock, packet is transmitted with common IPv6, equals at 100 o'clock, packet is transmitted with the IPv6 tunnel; Bit63～0 li the storage of third and fourth list item of SRAM be IPv4 packet when transmitting with the IPv6 tunnel style, 128 IPv6 destination addresses of IPv6 tunnel end outlet router.
The whole system operation flow process is following:
1) IP packet input interface circuit reads treated ppp protocol packet and data source port numbering from physical and datalink layer treatment circuit; Treated ppp protocol packet only contains protocol domain, information field and region filling, and other part of PPP information bag is disallowable at higher level's circuit.According to the 16 bit protocols numbering of PPP bag, extract wherein pure IPv6 or IPv4 packet, the pure IPv6 message or the IPv4 message that will remove PPP 16 bit protocol territories and region filling send to the packet filtering circuit.
2) the packet filtering circuit receives IPv4 and IPv6 packet, if reception is clean culture IPv4 packet, then the life span TTL territory of IPv4 bag is checked, if its TTL is 0, then with this IPv4 data packet discarding; If TTL is greater than 1, then the TTL territory to the IPv4 packet subtracts 1 operation, if after subtracting 1, TTL equals 0, then this IPv4 packet is sent to the 0th and submits bag queue memory FIFO; If the IPv4 packet that receives is a multi-case data, also sends to the 0th and submit bag queue memory FIFO; If the TTL of the clean culture IPv4 that receives bag is not 0; It is not 0 that TTL subtracts the TTL that obtains after 1 operation yet; Then let this IPv4 bag accomplish TTL and subtract 1 operation, regenerate new stem verification and this bag of relief passes through, send to next stage bag input rank memory FIFO.
The IPv6 packet that the packet filtering circuit receives divides three kinds: clean culture, multicast, appoint and broadcast.In follow-up processing, native system is to appointing the processing of broadcasting the same with clean culture, and all processing modes to clean culture also are applied to simultaneously appoint and broadcast, but no longer explanation.
After the packet filtering circuit received the IPv6 bag, the jumping limit of at first checking bag if its jumping limit is 0, just abandoned this IPv6 bag; If its jumping limit more than or equal to 1, then subtracts 1 operation with jumping limit, if after subtracting 1, jumping figure is 0, then this IPv6 packet is sent to the 0th and submits bag queue memory FIFO; After if jumping figure subtracts 1, jumping figure still is not 0, and the packet filtering circuit is just checked this IPv6 bag destination address; If just sending to the 0th, multicast packet submits bag queue memory FIFO.
If the destination address of the IPv6 packet that receives is this router, divide two kinds of situation, first kind is situation: this packet is not the IPv6 tunnel packet, then sends to the 0th and submits bag queue memory FIFO; Second kind is situation: this packet is a tunnel packet, and the bag less than 61 bytes all abandons so, and what be not less than 61 bytes just sends to next stage bag input rank memory FIFO.
If the destination address of the IPv6 packet that receives is not this router; Also divide two kinds of situation: first kind of situation is that this packet is the IPv6 tunnel packet; Bag less than 61 bytes all abandons so, and what be not less than 61 bytes just sends to next stage bag input rank memory FIFO; Second kind of situation is that this packet is not an IPv6 tunneling data bag, then the size of packet do not checked directly to send to next stage bag input rank memory FIFO.
3) IPv6 protocol encapsulation circuit is through bag input rank memory fifo interface circuit read data packet, and according to the version number of IP data, bag input rank memory fifo interface circuit knows that the data of reading in are IPv4 packet or IPv6 packet.
If IPv4 data; Under the control of State Control machine circuit; Bag input rank memory fifo interface circuit reads the IPv4 header data; And it is kept in the IPv4 header data register, the data in the IPv4 header data register are exported to IPv4 packet header again changes packet header, IPv6 tunnel circuit.Corresponding each the IPv4 packet header of packet header, IPv6 tunnel circuit is changeed in IPv4 packet header; Generate an IPv6 encapsulation packet header: the source address in IPv6 packet header is exactly the IPv6 address of this router, and destination address the highest 96 bit127～32 in packet header put 0, and minimum 32 is exactly the destination address of working as the IPv4 packet of pre-treatment; Next stem territory, packet header is set to metric 101; It is metric 64 that jumping limit is made as, and the traffic classes of bag is set to 0, and the number of failing to be sold at auction puts 0.The IPv6 packet header that generates sends in the data register of packet header, IPv6 tunnel.Multi-channel data selector will be kept in the data register of packet header, IPv6 tunnel IPv6 packet header be kept in the IPv4 header data register data successively gating send among the IPv6 bag queue memory FIFO of next stage; Meanwhile wrap the loading section that input rank memory fifo interface circuit continues to read the IPv4 packet; And they are kept in the IPv4 load data register; After the data in having sent IPv4 header data register; Multi-channel data selector is the output of gating IPv4 load data register immediately, and the IPv6 tunnel packet does not send among the IPv6 bag queue memory FIFO of next stage just as flowing water with breaking like this.
If IPv6 tunnel packet; Bag input rank memory fifo interface circuit reads the IPv6 head; And the IPv6 head abandoned; And then read the IPv4 header data of IPv6 tunnel packet, and it is kept in the IPv4 header data register, the data in the IPv4 header data register are exported to IPv4 packet header again changes packet header, IPv6 tunnel circuit.Under the control of State Control machine circuit, corresponding each the IPv4 packet header of packet header, IPv6 tunnel circuit is changeed in IPv4 packet header, and generate an IPv6 encapsulation packet header again: the source address in IPv6 packet header is exactly the IPv6 address of this router; Destination address the highest 96 bit127～32 in packet header put 0; Minimum 32 is exactly destination address when the IPv4 packet of pre-treatment, and it is metric 101 that next stem territory, packet header is set to, and jumping limit is made as metric 2; The traffic classes of bag is set to 0, and the number of failing to be sold at auction puts 0.The IPv6 packet header that generates sends in the data register of packet header, IPv6 tunnel.Multi-channel data selector will be kept in the data register of packet header, IPv6 tunnel IPv6 packet header be kept in the IPv4 header data register data successively gating send among the IPv6 bag queue memory FIFO of next stage; Meanwhile wrap input rank memory fifo interface circuit and continue to read the IPv4 data payload part of IPv6 tunnel packet; And they are kept in the IPv4 load data register; After the data in having sent IPv4 header data register; Multi-channel data selector is the output of gating IPv4 load data register immediately, and the IPv6 tunnel packet of so having upgraded does not send among the IPv6 bag queue memory FIFO of next stage just as flowing water with breaking.
The IPv6 packet that bag input rank memory fifo interface circuit reads is if not tunnel packet; Then the IPv6 packet is not carried out any processing; Only it is temporarily stored in the IPv6 data register; Through multi-channel data selector, directly it is sent to the IPv6 bag queue memory FIFO of next stage.
4) packet-related information extracts circuit and from IPv6 bag queue memory FIFO, reads the IPv6 packet through IPv6 bag queue memory fifo interface circuit, and each beat is read 40, and wherein 8 is side information, and 32 is the IP packet.In the IPv6 bag queue memory fifo interface circuit beat calculator, a bag calculator are arranged, the packet beat number of beat calculator recorder, each beat contains 32 IP data, the packet number of bag calculator recorder.During system initialization, beat calculator and bag calculator are by clear 0.When IPv6 bag queue memory fifo interface circuit receives a packet; The beat counter value that this packet first segment beat of data is corresponding; It is exactly the initial address that this IPv6 packet is preserved in the IPv6 memory RAM; The counter value that packet final section beat of data is corresponding is exactly the termination address that this packet is preserved in the IPv6 memory RAM.After every reception one beat data, counter value adds 1.The initial address of packet and termination address are exported, and are kept at respectively in bag initial address register, the bag termination address register.Correspondingly, when receiving a packet, the bag counter value that this packet first segment beat of data is corresponding is exactly the corresponding sequence number of this packet, and this sequence number is exported to the packet number register holds.Whenever receive a packet, the bag counter value adds 1, and it is after last beat that receives packet, to take place that the bag calculator adds 1.
Under the effect of State Control machine circuit; IPv6 bag queue memory fifo interface circuit writes the RAM circuit through bag; The IPv6 bag that receives is sent to the IPv6 packet memory RAM that links to each other with packet-related information extraction circuit; IPv6 packet memory RAM is the two-port RAM memory of a read-write and clock synchronization, and a port is used for write data specially, and a port is used for read data specially.
Under the effect of State Control machine circuit, the source port of IPv6 bag queue memory fifo interface circuit extraction packet is numbered, and the source port numbering is sent to the source port numbered register.For the IPv6 packet that receives, if its next stem territory is 0, then puts and submit sign, and this is submitted sign export to and wrap the friendship marker register, in this register, preserve.
Under the effect of State Control machine circuit, the traffic classes of IPv6 bag queue memory fifo interface circuit extraction bag is kept in the packet priority register.If the IPv6 bag is a tunnel packet, just the Tunnel Identifier register is put 1, otherwise put 0.
Wrap and hand over the value of marker register, packet priority register, bag source port number register, bag termination address register, bag initial address register, packet number register to export to IPv6 package informatin transtation mission circuit; IPv6 information transtation mission circuit sends the data to packet-related information and extracts the IPv6 packet relevant information queue memory FIFO that circuit links to each other under the control of State Control machine circuit.
CAM work receives its command line and the total line traffic control of request msg; The search instruction transtation mission circuit generates CAM command line control data: request gating signal REQSTB, operational order type signal INST, search type signal LTIN, section selects signal SEGSEL, mask register to select signal GMASK, CAM command line control data sends to search instruction queue memory FIFO by the search instruction transtation mission circuit.
Packet number register, Tunnel Identifier register and bag destination address register send to packet-related information through the search instruction transtation mission circuit and extract the search instruction queue memory FIFO that circuit links to each other; Wherein 72 bit width REQDATA data of the corresponding CAM data/address bus input of the data of Tunnel Identifier register and bag destination address register preservation are used for carrying out CAM and search.
5) the inner search instruction queue memory fifo interface circuit of CAM control circuit reads search instruction from search instruction queue memory FIFO, and the REQDATA data are write CAM writes data register.The operation of CAM memory receives the control of command line, and the bus control command REQSTB, INST, LTIN, SEGSEL, the GMASK that therefore read write CAM operational order transtation mission circuit.Also that search instruction is the corresponding sequence of data packet of search instruction queue memory fifo interface circuit number is saved in the sequence of data packet memory.
After content-addressable memory item and the initialization of SRAM list item are accomplished; In the process of CAM operation; Operating system will be constantly to content-addressable memory item and SRAM list item delete, operation such as interpolation, these operations are that CPU sends the CAM maintenance instruction through cpu interface circuit to CAM maintenance instruction queue memory FIFO and accomplishes.The CAM control circuit reads the CAM maintenance instruction of CAM maintenance instruction queue memory FIFO through CAM maintenance instruction queue memory fifo interface circuit; And the REQDATA data are write CAM write data register, the bus control command REQSTB, INST, LTIN, SEGSEL, the GMASK that read write CAM operational order transtation mission circuit.The SRAM list item that CAM maintenance instruction queue memory fifo interface circuit is also write needs is kept at SRAM and writes in the data register.
Under the effect of State Control machine circuit; CAM data/address bus read-write control circuit and the SRAM bus control circuit that reads and writes data writes corresponding list item in CAM and the SRAM memory, and the result that maybe will search exports to CAM read data register, SRAM read data register.If CAM is carried out attended operation, the CPU read data register sends to cpu interface circuit with CAM that reads and SRAM data, submits CPU through cpu interface circuit.If the instruction that CAM is operated is from search instruction queue memory fifo interface circuit; Then the result of SRAM retrieval and the sequence number of sequence of data packet register holds are outputed to the result for retrieval register, send to the result for retrieval queue memory FIFO that links to each other with the CAM control circuit through the result for retrieval register.
6) the bag transtation mission circuit is through IPv6 packet relevant information queue memory fifo interface circuit; Read and wrap in initial address, the termination address stored among the IPv6 packet memory RAM, submit sign and sequence of data packet number, and termination address is kept in the termination address register.Result for retrieval queue memory fifo interface circuit; Read result for retrieval queue memory FIFO, submit flag according to what flag and IPv6 packet relevant information queue memory fifo interface circuit obtained, the state machine control circuit is known that the bag transtation mission circuit carries out processing mode to packet or is to transmit according to IPv4; Be that packet is submitted; Be with data packet discarding, or be to transmit this packet, or be to transmit this packet according to the IPv6 tunnel style according to common IPv6.If the sequence of data packet that obtains via IPv6 packet relevant information queue memory fifo interface circuit and result for retrieval queue memory fifo interface circuit in addition number is saved in 4 packet number register A and packet number register B respectively; Data among packet number register A and the packet number register B are input to data comparator B; If result relatively is that two data are unequal; Mistake appears in illustrative system; Data comparator B sends index signal to cpu interface circuit, through cpu interface circuit whole system is resetted.According to top method system is carried out initialization after resetting.
IPv6 packet relevant information queue memory fifo interface circuit is numbered from IPv6 packet relevant information queue memory FIFO reading of data packet length, packet priority, source port, and it is kept at respectively in data packet length register, packet priority register, the source port numbered register.Result for retrieval queue memory fifo interface circuit reads destination interface numbering, purpose ply-yarn drill numbering, next-hop IP v6 or IPv4 address, tunnel IPv6 destination address, respectively they is kept in destination interface numbered register, purpose ply-yarn drill numbered register, next-hop IP v6 register or IPv4 address register, the tunnel IPv6 destination address register.
If data are transmitted according to IPv4; Then with the value of packet length register, packet priority register, source ply-yarn drill numbered register, source port numbered register, destination interface numbered register, purpose ply-yarn drill numbered register, the output of next-hop IP v4 register, be kept at 3 bit wides and be in 36 the additional data registers group.Under the effect of State Control machine; MUX B divides 3, and to clap 3 bit wides be that data in 36 the additional data registers group send; These data are added on the front of IPv4 packet as the additional data head of IPv4 packet, send to up FIFO.
What be right after IPv4 additional data head is exactly the IPv4 packet; Under the effect of State Control machine circuit; Increase 10 adders and receive bag storage initial address, this address value is realized adding 10 operations, and the result is exported to address register A preserve from input; Multi-channel data selector A selects the data among the address register A to export to IPv6 packet memory RAM and reads address register, reads address register and will read the address bus of reading that the address sends to IPv6 packet memory RAM read port.IPv6 packet memory RAM will read data to send to bit wide be 36 IP data register; MUX B gating bit wide is 36 an IP data register, and the IPv4 packet first count data additional data hair that just follows IPv4 closely is given up FIFO like this.
Under the effect of State Control machine circuit, increase 1 adder and read the value that IPv6 packet memory RAM reads address register, this address is carried out submitting to address register C behind the add-one operation.Data among the multi-channel data selector A gating address register C are given IPv6 packet memory RAM with these data and are read address register.The process of system operation after this is the same during with transmission IPv4 packet first count data.
Each clock cycle, data comparator A compares the value that the IPv6 packet memory RAM that imports reads the bag storage termination address register of address register value and input, if both are equal, data all output of this packet is described.If also have other data in the packet memory circuit, under the effect of State Control machine, the bag transtation mission circuit also carries out same processing to follow-up packet.
If data are transmitted according to common IPv6, the course of work of bag transtation mission circuit is totally similar with the course of work of transmitting the IPv4 packet, has only fraction different.Different part is:
(1) if data transmit according to common IPv6; Then with the value of packet length register, packet priority register, source ply-yarn drill numbered register, source port numbered register, destination interface numbered register, purpose ply-yarn drill numbered register, the output of next-hop IP v6 register, be kept at 6 bit wides and be in 36 the additional data registers group.Under the effect of State Control machine; It is that 36 things in the additional data registers group send with 6 bit wides that MUX B divides 6 bats; These data are added on the front of IPv6 packet as the additional data head of IPv6 packet, give next stage up FIFO.
(2) address of the first count data of IPv6 packet is to send to address register B through bag storage initial address; Send to IPv6 packet memory RAM through multi-channel data selector A again and read address register, can not add 10 operations through increasing 10 adders.
If data are transmitted according to the IPv6 tunnel, the course of work of bag transtation mission circuit is totally similar with the course of work of transmitting the IPv6 packet, has only fraction different.Different part is: if data are transmitted according to IPv6; Then with the value of packet length register, packet priority register, source ply-yarn drill numbered register, source port numbered register, destination interface numbered register, purpose ply-yarn drill numbered register, next-hop IP v6 register, the output of tunnel IPv6 destination address register, be kept at 10 bit wides and be in 36 the additional data registers group; Under the effect of State Control machine; When sending tunnel IPv6 packet; The IPv6 destination address that tunnel packet is 128 comes from IPv6 protocol encapsulation circuit, and will use bit wide here is the tunnel IPv6 destination address replacement that CAM tables look-up and obtains of passing through of preserving in 36 additional data registers group.
If data are not carried out IPv4, common IPv6 forwarding, the forwarding of IPv6 tunnel, still to submit, the course of work of bag transtation mission circuit is totally similar with the course of work of transmitting the IPv6 packet, has only fraction different.Different place is:
(1) during the submitting of IPv6 packet, the additional data of IPv6 packet has only a bat, and additional data only contains active ply-yarn drill numbering and numbers with source port.Other data that less than is 36 are filled with 0.
(2) data of selecting through multi-channel data selector B send to submits the packet register, sends to the 1st and submits bag queue memory FIFO through submitting the packet register.
If data are not carried out IPv4, common IPv6 forwarding, the forwarding of IPv6 tunnel, need not submit yet, still abandon, under the effect of State Control machine circuit, the bag transtation mission circuit no longer carries out any operation to IPv6 packet memory RAM.Multi-channel data selector A and multi-channel data selector B do not carry out any operation yet.
Be dropped packet back other packet in addition if follow; The forwarding information of State Control machine circuit indication IPv6 packet relevant information queue memory fifo interface circuit and result for retrieval queue memory fifo interface circuit extraction next one packet then, according to the sign of forwarding information according to top said mode carry out packet forwarding, submit, discard processing.
7) to submit bag queue memory FIFO not empty as long as the 0th is submitted bag queue memory FIFO or the 1st; Submit the bag transtation mission circuit just can take turns never empty the 0th submit bag queue memory FIFO and the 1st and submit and wrap that read data packet sends to the SRAM dual-ported memory among the queue memory FIFO; The data packet byte number of in the SRAM dual-ported memory, storing of submitting reaches certain threshold value; Or receive when not receiving new data packets in a period of time behind the packet, submit the bag transtation mission circuit just to cpu interface circuit transmission interrupt signal, and the length that will submit initial address, termination address and transferred data that packet stores in dual-ported memory RAM sends cpu interface circuit to; Cpu interface circuit sends interrupt signal to CPU; If CPU is not in a hurry, just interrupt requests is carried out correspondingly, start and to submit the bag data and transmit; Cpu interface circuit will be submitted packet and from the SRAM dual-ported memory, read out, and redispatch and handle to CPU.
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| CN1564542A (en) * | 2004-04-20 | 2005-01-12 | 清华大学 | Tunnel set-up method for carrying out internet of IPV4 network on IPV6 network |
| CN1571360A (en) * | 2003-07-18 | 2005-01-26 | 华为技术有限公司 | Method for implementing intra-site automatic tunnel |
| CN1604587A (en) * | 2003-10-01 | 2005-04-06 | 华为技术有限公司 | A network transition accessing method |
| WO2006053856A1 (en) * | 2004-11-18 | 2006-05-26 | International Business Machines Corporation | Tunneling ipv6 packets |
-
2009
- 2009-10-12 CN CN2009100935323A patent/CN101692647B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571360A (en) * | 2003-07-18 | 2005-01-26 | 华为技术有限公司 | Method for implementing intra-site automatic tunnel |
| CN1604587A (en) * | 2003-10-01 | 2005-04-06 | 华为技术有限公司 | A network transition accessing method |
| CN1564542A (en) * | 2004-04-20 | 2005-01-12 | 清华大学 | Tunnel set-up method for carrying out internet of IPV4 network on IPV6 network |
| WO2006053856A1 (en) * | 2004-11-18 | 2006-05-26 | International Business Machines Corporation | Tunneling ipv6 packets |
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| CN101692647A (en) | 2010-04-07 |
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