CN101685774A - Heteroepitaxial growth process based on interface nano-structure - Google Patents

Abstract

The invention provides a heterogeneous epitaxial growth process based on the interface nanostructure. There is a lattice mismatch between the substrate material and the epitaxial layer material, and the formation of the epitaxial layer includes four stages: first, metal nanoparticles are formed on the substrate; then, nanowires are grown; then, a mask layer is deposited and the nanowires The upper part of the nanowire is exposed; finally, the exposed nanowire part is used as a window to grow an epitaxial layer laterally. The invention uses high crystal quality nanowires as windows for lateral growth, and a mask layer is separated between the laterally grown epitaxial layer and the substrate, eliminating the limitation of lattice matching between the epitaxial layer material and the substrate material. The invention can successfully solve the problem of heterogeneous growth among crystal materials with mismatched crystal lattices, and provides a new idea for realizing optoelectronic integration.

Description

A Heteroepitaxial Growth Process Based on Interfacial Nanostructure

Technical field:

The invention relates to a heterogeneous epitaxy growth process in the field of optoelectronics, in particular to a heterogeneous epitaxy growth method between semiconductor crystal materials with lattice mismatch (that is, lattice mismatch).

Background technique:

Today's world is undergoing a major transition from discrete to integrated optoelectronic devices. Due to various constraints and constraints in terms of materials, structures and processes, optoelectronic integration must solve a series of important basic scientific problems in order to make great progress.

It is an ideal way to realize optoelectronic integration by growing various material systems on one material substrate (that is, material compatibility), which integrates the excellent properties of various materials. For example: silicon (Si) crystal is the most commonly used and cheapest microelectronic material; but because Si is an indirect bandgap material, it cannot be used as an optoelectronic material, especially for a light-emitting material. The III-V compound semiconductor materials, such as gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), etc., are the most commonly used optoelectronic materials. If the integration of silicon materials and III-V materials can be realized, the two can be combined; on a semiconductor chip, both microelectronic integrated circuits and optoelectronic devices can be made; it is expected to promote the development of optoelectronic integration technology.

The existing heteroepitaxial layered growth method mainly faces the problem of lattice mismatch and thermal mismatch (D.Colombo, E.Grilli, M.Guzzi, S.Marchionna, M.Bonfanti, "Analysis of strainrelaxation by microcracks in epitaxial GaAs grown on Ge/Si substrates”, Journal of Applied Physics, vol.101, pp.103519, 2007.). For example, in the heteroepitaxial growth of GaAs/Si, since the lattice mismatch between the two is as high as 4.1%, the defect density in the epitaxial layer is as high as 10 ⁸ /cm ² . In order to solve this problem, the technologies currently used are: buffer layer technology (N.Gopalakrishnan, K.Baskar, H.Kawanami, et al., Effects of the lowtemperature buffer layer thickness on the growth of GaAs on Si by MBE, J. Cryst.Growth, vol.250, pp.29-33, 2003), flexible substrate technology (CLChua, WYHsu, CHLin, et al., Overcoming the pseudomorphic critical thickness limit using compliant substrates, Appl.Phys.Lett., vol. 64, pp.3640-3642, 1994) and lateral epitaxy technology (JDSchaub, R.Li, CLSchow, et al., Resonant-Cavity-Enhanced High-Speed Si Photodiode Grown by Epitaxial Lateral Overgrowth, IEEEPHOTONICS TECHNOLOGY LETTERS, vol.12, pp.1647, 1999). in:

Buffer layer (buffer) technology: the transition from the lattice constant of the substrate (such as Si) to the lattice constant of the epitaxial layer (such as GaAs) is achieved by introducing a buffer layer. The lattice constant is relaxed by introducing misfit dislocations, preventing or inhibiting threading dislocations caused by lattice mismatch from penetrating into the epitaxial layer, thereby improving the crystal quality of the epitaxial layer. But in order to relax the lattice constant, the growth temperature of the buffer layer is usually much lower than the normal growth temperature, so the defect density of the buffer layer itself is higher, which reduces the crystal quality of the epitaxial layer grown on top (JACarlin, SARingel, et al. al., Impact of GaAs buffer thickness on electronic quality of GaAs grown on graded Ge/GeSi/Si substrates, Appl. Phys. Lett., vol.14, pp.1884, 2000). Therefore, the defect density of the epitaxial layer is difficult to be lower than 10 ⁶ /cm ² , which cannot be used to prepare high-performance optoelectronic devices, especially for light-emitting devices;

Compliant Substrate technology: introduces a flexible layer material between the substrate and the epitaxial layer, and absorbs or releases the strain caused by lattice mismatch through the elastic deformation of the flexible layer, thereby reducing the defects of the epitaxial layer . There are two types of flexible layers currently used: twist-bonded thin layers and strontium titanate (SrTiO ₃ ) thin layers. For twist-bonded thin layers, due to the complex bonding process, it is difficult to achieve large-area preparation, and the residual stress and thin layer surface fluctuations are relatively large (FEEjeckam, MLSeaford, YHLo, HQHou, et al., Appl.Phys. Lett., vol.71, pp.776, 1997). For strontium titanate (SrTiO ₃ ) thin layer, Motorola first reported in 2001 (K.Eisenbeiser, J.Finder, R.Emrick, et al., RF devices implemented on GaAs on Si substrates using a SrTiO3 buffer layer, in Proc. GaAs IC Symp., Baltimore, MD, 2001), there is no follow-up report due to the problem of test repeatability. Therefore, flexible substrate technology is still in the exploratory stage, and the problem of lattice mismatch has not been completely solved;

Lateral epitaxy technology: first grow a GaAs thin layer on a Si substrate as a seed layer, then cover a layer of mask (such as SiO ₂ ), use photolithography to create a window on the mask to expose the GaAs seed layer, and finally carry out lateral epitaxy. Epitaxial growth of GaAs. Due to the large condensation nucleation energy of GaAs on the mask, GaAs cannot grow directly on the mask; therefore, GaAs only grows at the window, and gradually expands laterally, and finally forms a continuous layer of GaAs covering the mask layer. However, the GaAs in the window region is directly grown on the Si substrate, which still has a high defect density, which reduces the quality of the laterally grown GaAs crystal. At the same time, the photolithography process is relatively complicated and will introduce impurity pollution.

In summary, the above methods are not ideal for solving the lattice mismatch problem. In view of this, exploring new processes and new solutions to solve the problems caused by the lattice mismatch between the epitaxial layer and the substrate, and to improve the crystal quality of the epitaxial layer is a problem that is difficult to overcome in the existing technology.

C.Patrik T.Svensson，et al，Epitaxial III-V Nanowires on Silicon，Nano.Lett.，vol.4，pp.1987-1990，2004)。At present, the growth of semiconductor nanowires usually uses metal nanoparticles as a catalyst, and uses semiconductor epitaxial growth technology to grow columnar nanowires vertically or inclined to the horizontal plane of the substrate at the position of the metal particles. Since the contact area of the nanowires with the substrate is very small (less than 1 square micron), the lattice mismatch does not create defects in such a small area. Therefore, the crystal quality of the nanowires is not affected by the substrate, and there is no lattice mismatch problem in the heteroepitaxy of the nanowires. At present, defect-free high-quality GaAs nanowires have been grown on Si substrates (Thomas

C. Patrik T. Svensson, et al, Epitaxial III-V Nanowires on Silicon, Nano. Lett., vol.4, pp.1987-1990, 2004).

However, at present, the structure of semiconductor devices basically belongs to the parallel layered structure, and the corresponding process is also aimed at the layered structure; and for the vertical or inclined nanowire structure, it is very difficult to fabricate devices on such a thin nanowire, and it requires complex processes. , expensive electron beam lithography and other equipment. Therefore, how to use high-quality nanowires and transform them into planar layered structures is also a technical problem to be solved urgently.

Invention content:

The purpose of the present invention is to find out a kind of new epitaxy scheme, realize that the degree of lattice mismatch is bigger (degree of lattice mismatch=((lattice constant of epitaxial material-substrate lattice constant)/substrate lattice constant) ×100%) for high-quality epitaxy of both materials. The object of the present invention can be achieved in the following manner.

The present invention provides a heterogeneous epitaxial growth process based on interface nanostructures, wherein there is a lattice mismatch between the substrate material and the epitaxial layer material, and the formation of the epitaxial layer includes the following four stages:

first forming metal nanoparticles on the substrate;

Then grow nanowires;

then depositing a mask layer and exposing the upper portion of the nanowire;

Finally, the exposed nanowire part is used as a window to grow the epitaxial layer laterally.

The metal nanoparticles formed in the first stage have a diameter of 10-500nm.

Among them, it is preferred that the lattice mismatch between the substrate material and the epitaxial layer material exceeds 0.1%.

In the second stage of nanowire growth, metal nanoparticles are used as catalysts, and semiconductor columnar nanowires are grown vertically or inclined to the horizontal plane of the substrate at the position of the metal particles, wherein the diameter of the nanowires is similar to that of the metal particles.

In the third stage, the mask layer is deposited so that the nanowire and the substrate are buried in the mask layer, and the upper part of the nanowire is exposed by etching, grinding or ultrasonic methods, while the bottom of the nanowire and the surface of the substrate are still masked. layer cladding.

In the fourth stage, the exposed part of the nanowire is used as a window to perform lateral epitaxial growth of semiconductor material to form a continuous semiconductor epitaxial layer.

The substrate material is selected from the following crystals: silicon, gallium arsenide, indium phosphide or germanium.

The epitaxial layer material is selected from group III-V semiconductor materials or group IV semiconductor materials, preferably selected from gallium arsenide, indium phosphide, gallium nitride, gallium phosphide, indium arsenide or silicon germanium.

The solution of the invention combines the advantages of the nanowire growth technology and the lateral epitaxial growth technology. By first growing nanowires that are vertical or inclined to the substrate, at this time, because the contact area between the epitaxial layer material nanowire and the substrate is small (nanoscale), and the atoms in the nanowire can be stretched laterally; therefore, even if the epitaxial layer The lattice constant does not match the substrate, and the nanowires with low defect density and high quality can still be grown on the substrate.

Compared with the lateral epitaxial growth technology, this solution adopts the nanowire as the epitaxial window, does not need complex photolithography process, and reduces the pollution caused by the photolithography process. At the same time, due to the higher crystalline quality of the nanowires, the crystalline quality of the subsequent lateral epitaxial layer is also higher. Therefore, this solution has the advantages of simple process and higher crystal quality of the epitaxial layer.

Description of drawings:

Fig. 1 is a schematic diagram of forming nano-metal particles on a Si substrate;

2 is a schematic diagram of a semiconductor nanowire grown using metal particles as a catalyst;

Figure 3 (a) is a schematic diagram of the grown mask layer covering the substrate and nanowires;

Figure 3(b) is a schematic diagram of exposing the upper part of the nanowires by means of etching, grinding or ultrasonic waves;

Figure 4(a) is a schematic diagram of the initial stage of lateral epitaxial growth using nanowires as windows;

Figure 4(b) is a schematic diagram of the final effect of lateral epitaxy using nanowires as windows.

Detailed ways:

The present invention will be described in detail below in conjunction with the accompanying drawings in order to better understand the essence of the present invention.

example 1:

GaAs/Si Heteroepitaxial Growth

1. First, coat a metal film such as gold with a thickness of about 0.5 nm on the Si substrate, and after high-temperature annealing, obtain metal nanoparticles with a radius of about 10 nm, as shown in Figure 1;

2. Then, metal nanoparticles are used as catalysts, and GaAs columnar nanowires perpendicular to the horizontal plane of the substrate are grown at the position of the metal particles by using the semiconductor epitaxial growth process. The diameter of the GaAs nanowire is similar to the diameter of the metal particle, and the height is greater than 10nm, as shown in Figure 2;

3. Then continue to deposit a layer of silicon dioxide (SiO ₂ ) material as a mask layer, so that the nanowires are buried in the mask layer, as shown in Figure 3(a); then use an etching method to expose the upper part of the nanowires , while the bottom of the nanowire and the substrate surface are still covered by the mask layer, as shown in Figure 3(b);

4. Finally, use the exposed part of the nanowire as a window to perform lateral epitaxial growth of the GaAs semiconductor material, as shown in Figure 4(a), and continue growing to form a continuous semiconductor epitaxial layer, as shown in Figure 4(b).

Example 2:

InP/Ge Heteroepitaxial Growth

1. First, coat a layer of platinum metal film with a thickness of about 2nm on the Ge substrate, and after high-temperature annealing, obtain metal nanoparticles with a radius of about 100nm;

2. Then, using metal nanoparticles as a catalyst, using a semiconductor epitaxial growth process, grow InP columnar nanowires inclined to the horizontal plane of the substrate at the position of the metal particles. The diameter of the InP nanowire is similar to the diameter of the metal particle, and the height is greater than 10nm;

3. Then continue to deposit a layer of silicon nitride (Si ₃ N ₄ ) material as a mask layer, so that the nanowires are buried in the mask layer, and then use the grinding method to expose the upper part of the nanowires, while the bottom of the nanowires and the lining The bottom surface is still covered by the mask layer;

4. Finally, use the exposed part of the nanowire as a window to perform lateral epitaxial growth of the InP semiconductor material to continue growing and finally form a continuous semiconductor epitaxial layer.

Example 3

GaN/Si Heteroepitaxial Growth

1. First, coat a layer of titanium metal film with a thickness of about 10nm on the Si substrate, and after high-temperature annealing, obtain metal nanoparticles with a radius of about 500nm;

2. Then, metal nanoparticles are used as catalysts, and GaN columnar nanowires perpendicular to the horizontal plane of the substrate are grown at the position of the metal particles by using the semiconductor epitaxial growth process. The diameter of the GaN nanowire is similar to that of the metal particle, and the height is greater than 10 nm, as shown in FIG. 2 .

3. Then continue to deposit a layer of silicon oxynitride (SiON) material as a mask layer, so that the nanowires are buried in the mask layer, and then use the ultrasonic method to expose the upper part of the nanowires, while the bottom of the nanowires and the surface of the substrate remain covered by a mask layer;

4. Finally, use the exposed part of the nanowire as a window to perform lateral epitaxial growth of the GaN semiconductor material, and continue to grow to form a continuous semiconductor epitaxial layer.

Example 4

SiGe/GaAs Heteroepitaxial Growth

1. First, a layer of gold metal film with a thickness of about 8nm is plated on the GaAs substrate, and after high-temperature annealing, metal nanoparticles with a radius of about 300nm are obtained;

2. Then, using metal nanoparticles as a catalyst, using semiconductor epitaxial growth process, growing SiGe columnar nanowires perpendicular to the horizontal plane of the substrate at the position where there are metal particles. Wherein the diameter of the nanowire is similar to that of the metal particle, and the height is greater than 10nm;

3. Then continue to deposit a layer of silicon dioxide (SiO ₂ ) material as a mask layer, so that the nanowires are buried in the mask layer, and then use an etching method to expose the upper part of the nanowires, while the bottom of the nanowires and the substrate The surface is still covered by the mask layer;

4. Finally, use the exposed part of the nanowire as a window to perform lateral epitaxial growth of SiGe semiconductor material, and continue to grow to form a continuous semiconductor epitaxial layer.

Example 5

InAs/Si Heteroepitaxial Growth

1. First, coat a layer of platinum metal film with a thickness of about 5 nm on the Si substrate, and after high-temperature annealing, obtain metal nanoparticles with a radius of about 400 nm;

2. Then, using metal nanoparticles as a catalyst, using a semiconductor epitaxial growth process, grow InAs columnar nanowires inclined to the horizontal plane of the substrate at the position of the metal particles. Wherein the diameter of the nanowire is similar to that of the metal particle, and the height is greater than 10nm;

3. Then continue to deposit a layer of silicon nitride (Si ₃ N ₄ ) material as a mask layer, so that the nanowires are buried in the mask layer, and then use the grinding method to expose the upper part of the nanowires, while the bottom of the nanowires and the lining The bottom surface is still covered by the mask layer;

4. Finally, use the exposed part of the nanowire as a window to perform lateral epitaxial growth of the InAs semiconductor material, and continue to grow to form a continuous semiconductor epitaxial layer.

The above are the technical principles and non-limiting examples of the application of the present invention. The equivalent transformation done according to the conception of the present invention, as long as the scheme used still does not exceed the scope covered by the claims, should be included in this document. within the scope of the invention.

Claims (9)

1, a kind of heteroepitaxial growth process based on interface nano-structure it is characterized in that having lattice mismatch between backing material and the epitaxial film materials, and the formation of epitaxial loayer comprises following four-stage:

At first on substrate, form metal nanoparticle;

Follow grow nanowire;

Precipitate mask layer then and make the top of nano wire expose;

At last with the nano wire part exposed as window cross growth epitaxial loayer.

2, heteroepitaxial growth process according to claim 1 is characterized in that: lattice mismatch surpasses 0.1% between backing material and the epitaxial film materials.

3, heteroepitaxial growth process according to claim 1 is characterized in that: the phase I, formed metal nanoparticle diameter was 10～500nm.

4, heteroepitaxial growth process according to claim 1, it is characterized in that: nanowire growth is as catalyst with metal nanoparticle in the second stage, grow vertically or favour the semiconductor column nano wire of substrate horizontal plane in the position of metallic particles, wherein the diameter of the diameter of nano wire and metallic particles is close.

5, heteroepitaxial growth process according to claim 1, it is characterized in that: phase III deposition mask layer makes nano wire and substrate be buried in the mask layer, make the top of nano wire expose via etching, grinding or ultrasonic method, and the bottom of nano wire and substrate surface are still coated by mask layer.

6, heteroepitaxial growth process according to claim 1 is characterized in that: the part of exposing with nano wire in the quadravalence section is carried out the transversal epitaxial growth semi-conducting material and is formed one deck continuous semiconductor epitaxial loayer as window.

7,, it is characterized in that described backing material is selected from following crystal: silicon, GaAs, indium phosphide or germanium according to arbitrary described heteroepitaxial growth process among the claim 1-6.

8, according to arbitrary described heteroepitaxial growth process among the claim 1-6, it is characterized in that: described epitaxial film materials is selected from III-V family semi-conducting material or IV family semi-conducting material.

9, heteroepitaxial growth process according to claim 8 is characterized in that: described epitaxial film materials is selected from GaAs, indium phosphide, gallium nitride, gallium phosphide, indium arsenide or germanium silicon.

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