CN101673712A

CN101673712A - Layout design method for N-channel field effect transistor array in CMOS technique

Info

Publication number: CN101673712A
Application number: CN200910196472A
Authority: CN
Inventors: 付先锋; 康军; 邢庆刚
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-09-25
Filing date: 2009-09-25
Publication date: 2010-03-17

Abstract

The invention provides a layout design method for an N-channel field effect transistor array in a CMOS technique. A P pitfall doped area is formed below a shallow groove used in an N-channel field effect transistor, and the width range of the shallow groove is between 0.25 mu m and 0.31 mu m. The method provided by the invention can manufacture the shallow groove with good isolation performance and narrow width, and can reduce the leakage current of the N-channel field effect transistor, thus the performance of a component is improved, and the N-channel field effect transistor array with higher layout density also can be manufactured.

Description

The layout design method that is used for CMOS technology N channel field effect transistor array

Technical field

The invention belongs to a kind of semiconductor layout design, relate in particular to a kind of layout design method of the CMOS of being used for technology N channel field effect transistor array.

Background technology

In integrated circuit flourish today, element downsizing and the integrated trend that is inevitable also are the important topics of all circles' develop actively.When component size is dwindled gradually, integrated level (Integration) improves gradually, and interelement isolation structure also must dwindle, so element separation technical difficulty degree also increases gradually.Element separation helps regional oxidizing process, and (Local Oxidation, the field oxide that LOCOS) forms (Field Oxide) because field oxide is subject to beak (Birds Beak) feature of its profile, dwindles its size and have any problem in fact.In view of this, existing other element separation methods continue to be developed, wherein (Shallow Trench Isolation STI) is widely used most, especially is applied in the ic manufacturing process of time half micron (Sub-half Micron) with shallow trench isolation.

On integrated circuit (IC) design, N slot field-effect transistor (Native transistor) does not have trap to inject and the threshold voltage adjustment, for standard CMOS process, adopts the P type substrate of 10 ohmcm resistivity, and threshold voltage is generally between 0 to 0.2V.The N channel field effect transistor array is usually used in the circuit such as charge pump, and the device performance of N slot field-effect transistor self and the required effect of isolation between the N slot field-effect transistor usually need bigger chip area.

Below, please refer to Fig. 1, Fig. 1 is the schematic diagram that is used for the fleet plough groove isolation structure in the N slot field-effect transistor of prior art, in working order down, the PN junction reverse bias that n type interface 26a and 26b and P type substrate 10 form, P type substrate 10 is because doping content is low, its carrier depletion layer with broadening to STI16.Depletion width depends on concentration gradient and bias voltage.If adjacent PN junction exhausts in the break-through (punch through) of STI bottom, then can be between the N slot field-effect transistor isolated failure.For fear of this situation, pass through to increase the width of STI 16 in the prior art, for example the width with STI 16 increases to 0.86um, or an increase injection (field implant) realizes, but these two kinds of methods can make the volume of device increase, and have wasted the area of domain, therefore, can not be referred to as desirable solution.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of layout design method, is used to solve the too narrow electric leakage of shallow channel and too wide problem of wasting domain.

To achieve these goals, the present invention proposes a kind of layout design method of the CMOS of being used for technology N channel field effect transistor array, form P trap doped region below the shallow trench that uses in described N slot field-effect transistor, the width range of described shallow trench is between the 0.25um to 0.31um.

Optionally, the width of described shallow trench is 0.28um.

Optionally, described shallow trench is made and be may further comprise the steps: form described shallow trench on Semiconductor substrate; Mixed in described shallow trench bottom, form P trap doped region; At described shallow trench sidewall and bottom grow liners oxide layer and silicon nitride layer; In described shallow trench and described semiconductor substrate surface growth dielectric; Carry out annealing in process; Grind on surface to described dielectric, removes the dielectric on the described Semiconductor substrate and make described shallow trench flattening surface.

The useful technique effect that the present invention is used for the layout design method of CMOS technology N channel field effect transistor array is: the layout design method that the present invention is used for CMOS technology N channel field effect transistor array forms P trap doped region below shallow trench, avoided occurring the situation of depletion layer in the shallow trench bottom, even under the smaller situation of the width design of shallow trench, 0.28um for example, also can well prevent the generation of the situation of leaking electricity, thereby can make and to hold more transistor on the whole domain, improve the density of the domain of design.

Description of drawings

Fig. 1 is the schematic diagram that is used for the fleet plough groove isolation structure in the N slot field-effect transistor of prior art;

Fig. 2 is the structural representation of shallow trench of the making of the present invention's layout design method of being used for CMOS technology N channel field effect transistor array;

Fig. 3 is the contrast number figure of the leakage current of the present invention's layout design method of being used for CMOS technology N channel field effect transistor array.

Embodiment

The present invention is described in further detail below in conjunction with the drawings and specific embodiments.

Please refer to Fig. 2, Fig. 2 is the structural representation of shallow trench of the making of the present invention's layout design method of being used for CMOS technology N channel field effect transistor array, on scheming, can see, P trap doped region 15 is arranged below shallow trench 16, shallow trench 16 separates n type interface 26a and 26b, and concrete making step is as follows: form described shallow trench 16 on Semiconductor substrate 10; Mixed in described shallow trench 16 bottoms, form P trap doped region 15; At described shallow trench 16 sidewalls and bottom grow liners oxide layer 12 and silicon nitride layer 14, the purpose of grow liners oxide layer 12 is for fear of corner effect (CornerEffect), and grown silicon nitride layer 14 has prevented the Semiconductor substrate of making owing to silicon 10 and will be filled into different stress that produce of thermal coefficient of expansion between the dielectric in the groove; In described shallow trench 16 and described semiconductor substrate surface growth dielectric, described dielectric is a silica, generally is to utilize chemical gaseous phase deposition (CVD) to insert dielectric in described shallow trench 16; Carry out annealing in process, annealing temperature is between 1000 ℃ to 1200 ℃; Grind on surface to described dielectric, makes the shallow trench flattening surface, and remove the dielectric of described N channel surface.The width range of described shallow trench is between the 0.25um to 0.31um, and preferred, the width of described shallow trench is 0.28um.

Owing to the N slot field-effect transistor is that the trap that do not have that is fabricated directly on the silicon substrate injects, therefore the PN junction of drain electrode and source electrode is the PN junction that N+ and P-substrate form in the prior art.A lot of at substrate one side depletion layer meeting broadening, and extend under the shallow trench (STI).If the depletion layer break-through on both sides has then just formed current path between n type interface 26a and the 26b.Carry out the P trap in this zone and inject, can improve the concentration of the low-doped end of PN junction P type, reduce depletion width, avoid the beneath depletion layer break-through of STI.

When the width range of shallow trench is between the 0.25um to 0.31um the time, use method provided by the present invention, can avoid the generation of the situation of leaking electricity.Than the width 0.86um of the shallow trench of prior art, obviously, when designing the N channel field effect transistor array, taken less domain, in other words, on certain domain, can design more transistor exactly, improved the density of domain.

At last, please refer to Fig. 3, Fig. 3 is the contrast number figure of the leakage current of the present invention's layout design method of being used for CMOS technology N channel field effect transistor array, abscissa is represented the transistorized label tested among the figure, ordinate is represented the size of the transistor drain current tested, unit is an ampere, square dot among the figure is to use the value of the transistorized leakage current of the narrower shallow trench of width in the prior art, initial point among the figure is the value of the transistorized leakage current of shallow trench provided by the invention, triangle form point among the figure is the value of the transistorized leakage current of the shallow trench of use wider width in the prior art, on scheming, can find out intuitively, the represented leakage current of square dot is at 0.01 ampere the order of magnitude among the figure, be far longer than initial point and the represented leakage current of triangle form point, therefore as can be seen, method provided by the invention can reduce the generation of leakage current effectively, thereby improves the electric property of field-effect transistor.

Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have in the technical field of the present invention and know the knowledgeable usually, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.

Claims

1. layout design method that is used for CMOS technology N channel field effect transistor array, it is characterized in that: form P trap doped region below the shallow trench that uses in described N slot field-effect transistor, the width range of described shallow trench is between the 0.25um to 0.31um.

2. the layout design method that is used for CMOS technology N channel field effect transistor array according to claim 1, the width that it is characterized in that described shallow trench is 0.28um.

3. the layout design method that is used for CMOS technology N channel field effect transistor array according to claim 1 is characterized in that described shallow trench makes by following steps:

S1: on Semiconductor substrate, form described shallow trench;

S2: mixed in described shallow trench bottom, form P trap doped region;

S3: at described shallow trench sidewall and bottom grow liners oxide layer and silicon nitride layer;

S4: in described shallow trench and described semiconductor substrate surface growth dielectric;

S5: carry out annealing in process;

S6: grind on the surface to described dielectric, removes the dielectric on the described Semiconductor substrate and make described shallow trench flattening surface.