CN101673221A - Interrupt processing method of embedded on-chip multiprocessor - Google Patents

Abstract

The invention belongs to the technical field of on-chip multiprocessors, in particular relating to an interrupt processing method of an embedded on-chip multiprocessor. On the basis of keeping the original structure of each processor, by designing a multiprocessor interrupt dispatcher IP kernel meeting the on-chip bus standard, the invention completes the dispatching for the external interrupt andsimultaneously realizes the interrupt generated by the on-chip multiprocessor, thereby achieving the internuclear interrupt communication effect. The invention realizes the centralized dispatching for multiple interrupts inside and outside the chip, comprehensively allocates the interrupts according to the usage rate detection for each CPU while considering the real-time performance, and achievesthe effect of balancing system loads.

Description

An Interrupt Handling Method for Embedded On-Chip Multiprocessor

technical field

The invention belongs to the technical field of on-chip multiprocessors, and in particular relates to an interrupt processing method of an embedded on-chip multiprocessor.

Background technique

In a uniprocessor, an interrupt means that when the CPU is running the current program, when some abnormal event or some kind of external request or internal software interrupt request occurs, the CPU temporarily stops the program being executed and turns to execute the exception or external device. The processing program that serves the internal software interrupt. After the operation is completed, the CPU returns to the temporarily stopped program and continues to execute the original program. When there are many CPU peripherals, a large number of interrupts may be generated at a certain moment, making the CPU in an interrupted state for a long time, so that some interrupt events cannot be processed, which reduces the real-time performance and overall performance of the system.

The development of multiprocessor technology can solve the above problems, which requires a reasonable multiprocessor interrupt controller. If all interrupts are processed on the same processor core, the above problems will also occur.

The advanced programmable interrupt controller (APIC) developed by INTEL for general-purpose computers works with the external 8259A to handle external interrupts received by the processor on its interrupt input pins and interrupts generated by software. Interrupt, in a multiprocessor system, it communicates with the external I/O APIC chip, and assigns these interrupts to the processors on the system bus for processing, and at the same time dynamically modifies the arbitration priority of each local APIC through bus arbitration , to maintain its equilibrium.

In the patent "multi-core processor interrupt load balancing method and device" with the application number CN200810135521, the processor cores are dynamically divided into two groups to deal with processes and interrupts respectively. Interrupt load balancing, but at the cost of dedicating a certain number of processor cores, it is not cost-effective when the number of processor cores is small.

Multiprocessors are not only used in general-purpose computers and servers, but embedded on-chip multiprocessors have also developed rapidly, gradually developing in the fields of electronic communication, multimedia, industrial control, automation, and intelligent equipment. However, the interrupt processing method applied to the on-chip multiprocessor in the embedded field is almost blank. If the interrupt processing is implemented like a general-purpose multiprocessor computer, the original architecture of each processor core needs to be modified, which greatly increases the embedded on-chip multiprocessing. The time and cost of server system development.

Contents of the invention

The object of the present invention is to propose an interrupt processing method of an embedded on-chip multiprocessor.

The interrupt processing method of the embedded on-chip multiprocessor that the present invention proposes comprises the processing of the multiprocessor interrupt regulator based on the on-chip bus, the processing of external interrupts, and the interrupt processing between cores, specifically as follows:

(1) Multiprocessor interrupt scheduler based on on-chip bus

Centralized scheduling is achieved by designing a multi-processor interrupt scheduler (Multi-Processor Interrupt Scheduler, MPIS) IP check interrupt that conforms to the on-chip bus interface standard. The multiprocessor interrupt scheduler is connected with the on-chip bus to realize communication with each processor core and receive interrupt communication information from the processor core. The input end of the multiprocessor interrupt scheduler is connected to the external I/O device interrupt source interface, To accept external interrupt signal sources, the N output interrupt signals of the multiprocessor interrupt scheduler (the number of processor cores) are respectively connected to the original external non-maskable (or enabled) interrupt signal source ports of each processor CPU . The processing of external interrupts and inter-core interrupt communication processing is realized through the multi-processor interrupt scheduler;

(2) Processing of external interrupts

Record the external maskable and non-maskable interrupt source signals in the corresponding registers of the multiprocessor interrupt scheduler, and the program gives priority to each interrupt source (the overall priority of inter-core interrupt communication is higher than that of external non-maskable interrupts and higher than maskable interrupts. ), the program setting can mask the enabling status of the interrupt source. After judging the interrupt to be scheduled, check the running status of each CPU (including the running program information and the CPU usage rate, which are sent by each CPU to the corresponding register of MPIS, and the operation system completion), first interrupt the CPU of the running task with a lower priority, and interrupt the CPU with a lower CPU usage rate when the task priority is the same, that is, consider system load balancing while considering the real-time nature of the system;

(3) Inter-core interrupt communication processing

Inter-core interrupt communication is sent by each CPU to the multiprocessor interrupt scheduler through the on-chip bus and recorded, and then the multiprocessor interrupt scheduler sends interrupt information to the interrupted CPU according to the record file, and the CPU reads the MPIS after the interrupt Corresponding to the CPU interrupt scheduling register, do the corresponding interrupt service program or obtain the communication data.

The beneficial effects of the present invention are: the present invention is an interrupt processing method of an embedded on-chip multi-processor, which reasonably and effectively realizes external interrupt and internal interrupt communication through MPIS on the basis of not changing the core architecture of the processor. Processing speeds up the development of embedded on-chip multi-processor systems, and considers system load balancing while considering system real-time performance.

Description of drawings

FIG. 1 is a schematic diagram of the connection relationship of MPIS in an on-chip multiprocessor system.

Figure 2 is a block diagram of the internal structure of MPIS.

Fig. 3 is a schematic diagram of the implementation process of solving the external interruption of the present invention.

Fig. 4 is a schematic diagram of the implementation process of solving inter-core interrupt communication in the present invention.

Detailed ways

The method of the present invention will be described below in conjunction with the accompanying drawings.

Example 1:

A kind of interrupt processing method of embedded multiprocessor on chip that the present invention proposes, comprises following process:

1) The connection relationship of MPIS in the on-chip multiprocessor system.

Here, the 4-core processor is taken as an example. As shown in Figure 1, MPIS is added to the on-chip multi-processor system in the form of an IP core. MPIS is connected to the unified on-chip bus in the system through the slave port. The input of the MPIS The terminal is the I/O device interface to generate external interrupt signal sources, including maskable and non-maskable interrupt signal sources. In addition, MPIS also generates interrupt output signals: INT0, INT1, INT2, INT3, which are respectively connected to the original non-maskable external interrupt (or enabled) interfaces of CPU0, CPU1, CPU2, and CPU3. Through the MPIS, the external interrupt signal source and the internal interrupt communication signal source are centrally managed and dispatched.

2) The internal structure framework of MPIS.

It is assumed here that the external maskable interrupt signal is 64-way INTM[63:0], the external non-maskable interrupt signal is 32-way INTUM[31:0], the number of internal interrupt communication signals is 8, and the on-chip bus signals include: clk, chipselect, address , read, readdata, write, writedata, etc., as shown in Figure 2. Register files in MPIS include: inter-core interrupt communication registers, external non-maskable interrupt registers, external maskable interrupt registers, maskable interrupt enable registers, CPU interrupt scheduling register groups, CPU operating status register groups, CPU interrupt enable registers, etc. .

The inter-core interrupt communication register is used to store the inter-core interrupt communication signal from the CPU. There are 8 internal interrupt signals, which are defined as the 32-bit register variable CIR, that is, 8 4-bit registers, each of which 4 bits represents an inter-core Interrupt, the 0-1 bits represent the interrupted 4 CPUID numbers: 00 stands for CPU0, 01 stands for CPU1, 10 stands for CPU2, 11 stands for CPU3, 2 bits are reserved and cleared, 3 bits are 1 or 0 means the interrupt signal is generated and no.

The external non-maskable interrupt register is defined as a 32-bit register variable OUMR, and each bit is 1 or 0 to indicate whether the interrupt signal is generated or not. Similarly, the external non-maskable interrupt register is defined as a 64-bit register variable OMR.

The maskable interrupt enable register is used to identify the enable condition of the 64-bit external maskable interrupt signal source, which is defined as a 64-bit register variable MER, and each bit is 1 or 0 to represent whether the corresponding external maskable interrupt signal source is masked or not. .

CPU interrupt scheduling register group There are 4 CPU interrupt scheduling registers here, which respectively store the interrupt scheduling results of each CPU. Four 8-bit register variables are defined here: PISR0, PISR1, PISR2, and PISR3 respectively store the interrupt scheduling results of CPU0, CPU1, CPU2, and CPU3. Table 1 lists the field descriptions of PISR0:

Table 1 PISR0 field description

bit describe

0-5 The interrupt ID number (priority) of the interrupt scheduling result 6-7 Judging which interrupt type is represented by the interrupt ID number recorded in bits 0-5 of this register 00: internal interrupt communication 01: external non-maskable interrupt 10: external maskable interrupt 11: no interrupt

CPU running status register group There are 4 CPU running status registers, which respectively store the current running status of each CPU. Four 16-bit register variables are defined here: PRSR0, PRSR1, PRSR2, and PRSR3 respectively store the current running status of CPU0, CPU1, CPU2, and CPU3. Table 2 lists the field descriptions of PRSR0.

Table 2 PRSR0 field description

bit describe 0-5 The ID number (priority) of the interrupt or task priority that CPU0 is running 6-7 Judging that 0-5 of this register is the recorded interrupt type or task 00: internal interrupt communication 01: external non-maskable interrupt 10: external maskable interrupt 11: task 8-14 The current CPU usage of CPU0 (0-100) 15 Reserved, cleared

The CPU interrupt enable register is used to identify the interrupt enable status of each CPU and the mask status of all interrupt sources of external maskable interrupts. By using this register, each CPU can realize random interrupt switch under the control of the program. The CPU with interrupt turned off only runs the task program, and the CPU with interrupt enabled can run the task program and accept the interrupt at the same time. Here, 16 is defined as the register variable PIER, and its 0-3 bits are 1 or 0, which respectively represent whether CPU0, CPU1, CPU2, and CPU3 interrupts are enabled or not. 4-14 are reserved and cleared. Bit 15 is 1 or 0 to represent whether all external maskable interrupt sources are masked or not.

The interrupt logic module of MPIS makes corresponding processing according to the situation of the register file, and modifies the register file, and completes the interrupt processing of the on-chip multi-processor system together with the CPU.

3) External interrupt processing.

The processing process of MPIS for external interrupt signal sources is shown in Figure 3. When external maskable and non-maskable interrupt signals are generated, MPIS registers the signal in the corresponding bit in OMR and OUMR, and the interrupt logic finds out the interrupt that needs to be processed according to MER Source, check the corresponding bits of PRSR0, PRSR1, PRSR2, PRSR3 to find the CPU running the lowest priority task, if there are more than one CPU running the lowest same priority task, find out the CPU with the lowest current CPU usage of each CPU, and find The PISR corresponding to the obtained CPU is modified to correspond to the interrupt source information that needs to be processed first among the interrupt sources that need to be processed. If the interrupt service routine is running on the CPU, the rules are the same as above. When MPIS decides to interrupt the CPU, it sends INT0, INT1, INT2, and INT3 interrupt signals to each CPU. After each CPU generates an interrupt, it reads the corresponding PISR register value through the on-chip bus, and jumps to the corresponding CPU according to the register value. The entry address of the registered service routine executes the interrupt service routine.

4) Interrupt communication processing between cores.

The processing process of MPIS to the source of the inter-core communication interruption signal is shown in Figure 4. The CPU generates the inter-core interruption information, including the interrupted CPU and the ID of the inter-core communication interruption, and modifies the corresponding field of the CIR through the on-chip bus. The PRSR corresponding to the interrupted CPU, judging the priority and the CPU usage rate determine whether to modify the PISR register of the CPU to be interrupted, generate the interrupt signal INTn, read the PISR of the CPU through the on-chip bus after the CPU is interrupted, and set the CPU according to the register value Jump to the entry address of the corresponding registered service program to execute the inter-core interrupt service program or obtain communication data.

Claims (1)

1, an interrupt processing method of embedded multiprocessor on chip, it is characterized in that comprising based on the multiprocessor interrupt regulator of on-chip bus, the processing of external interrupt, the interrupt processing between cores, concrete steps are as follows: (1) Multiprocessor interrupt scheduler based on on-chip bus Centralized scheduling is realized by designing a multi-processor interrupt scheduler IP check interrupt that conforms to the on-chip bus interface standard; the multi-processor interrupt scheduler is connected to the on-chip bus to realize communication with each processor core and accept messages from the processor core To interrupt the communication information, the input terminal of the multiprocessor interrupt scheduler is connected to the interrupt source interface of the external I/O device to accept the external interrupt signal source, and the N output terminal interrupt signals of the multiprocessor interrupt scheduler are respectively connected to the original CPU of each processor. External non-maskable interrupt signal source port; through the multiprocessor interrupt scheduler, the processing of external interrupts and inter-core interrupt communication processing are realized; (2) Processing of external interrupts Record the external maskable and non-maskable interrupt source signals in the corresponding registers of the multiprocessor interrupt scheduler, and the program assigns priority to each interrupt source, that is, the overall priority of inter-core interrupt communication is higher than that of external non-maskable interrupts. Interrupt, the program setting can mask the enabling status of the interrupt source. After judging the interrupt to be scheduled, check the running status of each CPU, including the running program information and CPU usage, and send it to the corresponding register of MPIS by each CPU. When the system is completed, interrupt the CPU of the running task with a lower priority first, and interrupt the CPU with a lower CPU usage rate when the task priority is the same, that is, consider system load balancing while considering the real-time nature of the system; (3) Inter-core interrupt communication processing The inter-core interrupt communication is sent by each CPU to the multiprocessor interrupt scheduler through the on-chip bus and recorded, and then MPIS sends the interrupt information to the interrupted CPU according to the record file, and the CPU reads the corresponding information of the multiprocessor interrupt scheduler after the interrupt. CPU interrupt scheduling register, do corresponding interrupt service routine or obtain communication data.

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