CN101667832B - Fractional-N phase-locking device and method - Google Patents

Abstract

The invention provides a fractional-N phase-locked loop, comprising: a time-to-digital converter for converting a time difference between the reference clock and the feedback clock into a time difference signal; the elimination circuit is used for receiving the time difference signal and generating a residual error signal according to the time difference signal and the instantaneous error signal; a digital loop filter for filtering the residual error signal to generate a handle; a digital control oscillator for generating an output clock according to control of the handle; a divider circuit for receiving the fractional value to generate the instantaneous error signal; and dividing the output clock by a divisor value according to the control of the fractional value to generate a feedback clock.

Description

Mark-N phase-locking device and method

Technical field

The invention relates to the phase-locked loop, particularly eliminate mark-N phase-locked loop (the digital fractional-N phase lock loop) of function about having phase noise.

Background technology

General digital phase locked loop (Digital Phase Lock Loop, Digital PLL) receives the reference clock with first frequency, and correspondingly produces the output clock with second frequency.Wherein, output clock is that phase place locks (Phase-locked) in the phase place of reference clock, and the second frequency of output clock is higher than first frequency N doubly.Shown in Figure 1A, typical digital phase locked loop 100A includes time-to-digital converter (Time-to-digital converter, TDC) 110, digital loop filter (Digital loop filter) 120, numerically-controlled oscillator DCO (digitally controlledoscillator) 130 and removes N circuit (divide-by-Ncircuit) 140A.Time-to-digital converter (TDC) 110 has the reference clock REF of first frequency in order to measurement and has time difference between the feedback clock FB of the 3rd frequency, and correspondingly produces a time difference signal TD of this time difference of expression.Loop filter 120 is in order to filtering this time difference signal TD (can be digital signal), and generation handle C.Numerically-controlled oscillator 130 produces the output clock OUT with second frequency according to handle.Except N circuit 140A will have the output clock OUT of second frequency divided by a divider value (divisor) N, the feedback clock FB that has the 3rd frequency with generation.Should be noted that this second frequency (be the frequency of output clock OUT, and be the frequency of oscillation of numerically-controlled oscillator 130 simultaneously) is controlled by the numerical value of handle C.One embodiment, the frequency of output clock OUT (be second frequency, also be the frequency of oscillation of numerically-controlled oscillator 130) is that the numerical value according to handle increases (minimizing) and increases (minimizing).And since except N circuit 140A except the N function, the frequency of this second frequency will be higher than the 3rd frequency N doubly.When handle C too little (too large), second frequency also can too low (too high); And correspondingly, the 3rd frequency also can too low (too high).Mode according to this, feedback clock FB is slow (too fast) too, and therefore fall behind (in advance) reference clock REF.As a result, causing time difference signal TD is on the occasion of (negative value), and this is on the occasion of the time difference of (negative value) expression reference clock REF and feedback clock FB.Must notice that digital loop filter 120 includes integrating function usually.Because the integrating function of digital loop filter 120, time difference signal TD be when (negative value), will make handle C increase (minimizing).In the mode of this loop circuit (closed-loop), handle C is adjusted the sequential that sequential (timing) (being frequency or phase place) that (namely increase or reduce) can make feedback clock FB can be followed the trail of (track) reference clock REF.Under stable state, handle C settles out (settle) and is suitable numerical value, and the mean value of time difference signal TD (mean value) is necessary for zero (zero), otherwise handle C will be because of the integrating function of digital loop filter 120 lost efficacy (blow up), and can't settle out.Therefore, under stable state, the 3rd frequency must equal first frequency.As a result, make second frequency be higher than the 3rd frequency N doubly owing to remove the processing of N circuit 140A, so second frequency must be higher than first frequency N doubly.

Figure 1A digital phase locked loop 100A realizes except N circuit 140A can use expediently except N counter (for example N being made as integer (integer)).Yet, because the divisor of counter need be integer, if but N is not integer, directly realizing with the counter with fixed divisor can't normal operation.If realize processing non-integer N (non-integer N) except the N function, must hypothesis N=N _Int+ α, wherein N _IntBe integer, α is the mark (fractional number) between 0～1, but and divider value that need Set arbitrarily (shuffle) counter.One embodiment, but divider value Set arbitrarily N _IntWith (N _Int+ 1); As long as (N _Int+ 1) possibility of divider value (probability) is α and N _IntThe divider value possibility is (1-α), and effectively divider value will equal N _Int+ α.In the known technology, triangular integration modulator (delta-sigmamodulator) is usually used in this divider value of dynamic setting.

With digital phase locked loop 100A except N circuit 140A with Figure 1B have except N with replace enforcement except the digital phase locked loop PLL 100B of mark function.The circuit 140B of one embodiment includes double modulus divider (Dual-modulus divider, DMD) 150 and triangular integration modulator (Delta-sigmamodulator, DSM) 160.Double modulus divider 150 in order to output clock OUT divided by a divider value N _IntOr (N _Int+ 1), and according to binary code CARRY produces feedback clock FB.And triangular integration modulator 160 is in order to receiving fractional value α, and modulates fractional value α according to the sequential that feedback clock FB provides and become binary code CARRY.The purpose of triangular integration modulator 160 is to produce binary code CARRY, and for example producing CARRY is 0, may be for α or 1, may be (1-α), and the mean value of CARRY equals α.Mode according to this, output clock OUT by divided by Set arbitrarily at N _IntAnd (N _Int+ 1) numerical value between, and mean value is N _IntThe divider value of+α is to produce feedback clock FB.

Select arbitrarily (Shuffling) can effectively reach except N and the effect of removing mark (fractional-Ndivision) except the divider value of N circuit.Present embodiment, under stable state, difference average time of reference clock REF and feedback clock FB (being the mean value of time difference signal TD) still equals zero, but (instantaneous) time difference of moment is non-vanishing, and maximum almost can be T _DCO/ 2.Wherein, T _DCOBe cycle time of expression output clock OUT, and divider value is that Set arbitrarily is N _IntWith (N _Int+ 1) numerical value between.The time difference of moment will cause that time difference signal TD produces transient noise, cause handle C noise to occur, and then cause output clock OUT to produce phase noise.

Except being produced the phase noise by any selection divider value, nonideal time-to-digital converter 110 (in Figure 1A or Figure 1B) also can be contributed (cont r ibute) phase noise in output clock OUT.Shown in Fig. 1 C, time difference signal TD should be the ratio of reference clock REF and feedback clock FB time difference, as shown in broken broken line 170 illustrate.Yet in fact, the characteristic of time-to-digital converter will depart from brokenly broken line 170 as camber line 180.This will be made time difference signal TD generation error and output clock OUT will be produced undesired phase noise by desirable straight line skew problem.

Summary of the invention

One of purpose of the present invention is to be to provide a kind of mark of eliminating phase noise-N phase-locked loop.

One of purpose of the present invention is to be to provide a kind of mark-N phase-locked loop, to reduce or to avoid phase noise because of moment output clock that time difference is caused.

One of purpose of the present invention is to be to provide a kind of mark-N phase-locked loop, to reduce or to avoid phase noise because of output clock that nonideal time-to-digital converter is caused.

One embodiment of the invention provide a kind of mark of eliminating phase noise-N phase-locking device.This mark-N phase-locking device includes: time-to-digital converter is converted to the time difference signal in order to the time difference with reference to clock and feedback clock; Eliminate circuit, in order to the time of reception difference signal, and according to time difference signal and moment error signal generation residual value error signal (Residual error signal); The digital loop filter is in order to filter the residual value error signal, to produce handle; Numerically-controlled oscillator is in order to the control generation output clock of foundation handle; Division circuit in order to receiving the fractional value (Fract ional number) between 0 and 1, to produce this error signal moment; And according to the control of this fractional value with output clock divided by a divider value, to produce feedback clock, wherein this eliminations circuit includes: the series expansion unit, extremely preset error signal in order to mate this error signal moment; And add way circuit, this time difference is deducted default error signal, to produce this residual value error signal.

It is a kind of in order to reduce the method for numerical fraction-N phase-locked loop (digital fractiona1-N phase lock loop) phase noise that one embodiment of the invention provide, include the following step: at first, quantize the time difference of reference clock and feedback clock, with the generation time difference signal; According to the time difference signal and moment error signal, produce residual value error signal (Residual error signal); Then, filter the residual value error signal, to produce handle; Utilize the handle control generator, to produce output clock; Receive 0 and 1 fractional value, to produce the moment error signal; Afterwards, according to fractional value with output clock divided by a divider value.

Description of drawings

Figure 1A shows the schematic diagram of known digital phase-locked loop.

Figure 1B shows the schematic diagram of known digital fractional N-type phase-locked loop.

Fig. 1 C shows the transfer characteristic of a time-to-digital converter.

Fig. 2 A shows the schematic diagram of the numerical fraction N-type phase-locked loop of one embodiment of the invention.

Fig. 2 B shows the schematic diagram of the numerical fraction N-type phase-locked loop of another embodiment of the present invention.

Fig. 3 shows the schematic diagram of the embodiment of Fig. 2 A, 2B intermediate cam quadrature modulates device.

[main element label declaration]

100A, 100B, 200A, 200B phase-locked loop

110,210 transducers

120,220 filters

130,230 voltage controlled oscillators

140A, 140B, 240 division circuits

150,250 dividers

160,260 modulators

270,310,340 add way circuit

280A, 280B adaptability series expansion equation block

320 integrators

330 arithmetic units that round off

350 gain/delay elements

Embodiment

The following description will be enumerated several better example embodiment of the present invention, and those skilled in the art should understand, and the present invention can adopt various possible modes to implement, and is not limited to the embodiment of following demonstration or the feature among the embodiment.In addition, many details of knowing no longer repeat to show or give unnecessary details, to avoid fuzzy emphasis of the present invention.

Still please refer to Figure 1B, in a typical mark-N phase-locked loop (fractional-N PLL) 100B, except N mark (fractional-Ndivision) function can be carried out by the divider value of Set arbitrarily double modulus divider (Dual-modulus divider, DMD) 150 effectively.But the Set arbitrarily divider value will cause the moment error of the time difference between reference clock REF and feedback clock FB.The moment error of this time difference is to be measured and digitlization by time-to-digital converter 110.Yet time-to-digital converter 110 is normally nonideal, therefore, can produce the distortion such as aforementioned time-to-digital converter 110.The present invention can eliminate the time difference moment error and the time to the number misroute parallel operation 110 because of the imperfect distortion that causes.

Various embodiments of the present invention are utilized series expansion (series expansion), and (i.e. the non-ideal characteristic of finding out time-to-digital converter is depicted in the linear combination of one group of basic function (a linear combination of a set of basis functions).In unrestriced exemplary embodiment, can adopt Legnedre polynomial (Legnedre polynomial progression (Legendre polynomials series)) to implement.Legnedre polynomial includes the linear combination of a Legnedre polynomial.The item time (first few terms) of the first of Legnedre polynomial lists as follows:

P ₀(x)＝1 (1)

P ₁(x)＝x (2)

P ₂(x)＝(3x ²-1)/2 (3)

P ₃(x)＝(5x ³-3x)/2 (4)

P ₄(x)＝(35x ⁴-30x ²+3)/8 (5)

P ₅(x)＝(63x ⁵-70x ³+15x)/8 (6)

Legnedre polynomial is quadrature (Orthogonal) in interval [1,1].In detail, applicable to following relationship:

${\∫}_{-1}^1{P}_m\left(x\right)P_n\left(x\right)\mathrm{dx}=\frac{2}{2n+1}{\mathrm{\δ}}_{\mathrm{mn}}---\left(7\right)$

Wherein, δ _MnBe Kronecker that function (Kronecker-delta function), namely

${\mathrm{\δ}}_{\mathrm{mn}}=\left\{\begin{array}{cc}1& m=n\\ 0& m\≠n\end{array}\right.---\left(8\right)$

Legnedre polynomial can be used for as one group of fundamental equation, with the transfer characteristic of expression time-to-digital converter.Making the moment error of the time difference between reference clock REF and feedback clock FB is ε, can use the sequence of Legnedre polynomial to launch (being the linear combination of Legnedre polynomial) expression time difference signal TD (being the output of time-to-digital converter TDC):

TD＝c ₀P ₀(ε)+c ₁P ₁(ε)+c ₂P ₂(ε)+c ₃P ₃(ε)+c ₄P ₄(ε)+c ₅P ₅(ε)+… (9)

Utilize triangular integration modulator (delta-sigma modulator) Set arbitrarily divider value in numerical fraction-N phase-locked loop, the value of ε (being the moment error of reference clock REF and feedback clock FB time difference) can be predicted exactly.If expansion coefficient (c ₀, c ₁, c ₂, c ₃...) also be known, then the error of time difference signal TD also can be estimated and be eliminated exactly.

The schematic diagram of the numerical fraction of Fig. 2 A demonstration one embodiment of the invention-N phase-locked loop 200A.Numerical fraction-N phase-locked loop 200A includes time-to-digital converter (time-to-digitalconverter, TDC) 210, eliminate circuit (Cancellation circuit) 215, digital loop filter (Digital loop filter) 220, numerically-controlled oscillator (Digitally controlledoscillator, DCO) 230 and division circuit (Divider circuit) 240.One embodiment, elimination circuit 215 include and add way circuit (summation circuit) 270 and adaptability series expansion function block 280A.One embodiment, division circuit 240 include a pair of modulus divider (dual-modulusdivider, DMD) 250 and a triangular integration modulator (Delta-sigma modulator, DSM) 260.

One embodiment, time-to-digital converter 210 be in order to the time difference of witness mark clock REF and feedback clock FB, and correspondingly produce to represent the time difference signal TD (for digital signal) of this time difference.Add way circuit 270 in order to time difference signal TD is deducted default error signal PE, to produce residual value error signal (Residual error signal) RE.And digital loop filter 220 is in order to filtering residual value error signal RE, and produces handle C.Numerically-controlled oscillator 230 produces output clock OUT in order to foundation handle C.Double modulus divider 250 in order to output clock OUT divided by a divider value, to produce feedback clock FB.Wherein, divider value is controlled by a binary system delivery signal CARRY.And triangular integration modulator 260 is in order to being modulated to a mark numerical value α this binary system delivery signal CARRY, and the clock generating time instant error signal that provides according to feedback clock FB.Adaptability series expansion equation block 280A is in order to receiving moment error signal and residual value error signal RE, and produces default error signal PE.Default error signal PE can represent with the Legnedre polynomial series expansion:

$\mathrm{PE}={\hat{c}}_0{P}_0\left(\mathrm{\ϵ}\right)+{\hat{c}}_1{P}_1\left(\mathrm{\ϵ}\right)+{\hat{c}}_2{P}_2\left(\mathrm{\ϵ}\right)+{\hat{c}}_3{P}_3\left(\mathrm{\ϵ}\right)+{\hat{c}}_4{P}_4\left(\mathrm{\ϵ}\right)+{\hat{c}}_5{P}_5\left(\mathrm{\ϵ}\right)+...---\left(10\right)$

Wherein, those coefficients with small cap (hat) represent the estimation coefficient of Legnedre polynomial progression in the equation (9).One embodiment, those estimation coefficients can adopt take the algorithm of minimum mean square (least mean square, LMS) as the basis:

${\hat{c}}_n^{\left(\mathrm{new}\right)}={\hat{c}}_n^{\left(\mathrm{old}\right)}+\mathrm{\μ}\·P_n\left(\mathrm{\ϵ}\right)\·\mathrm{RE},\mathrm{for\; n}=\mathrm{0,1,2,3},...---\left(11\right)$

Wherein, μ is adaptability constant (adaptation constant).This constant must be enough little of to guarantee the convergence of adaptability computing.Old numerical value (oldvalue) before the computing of subscript " (old) " expression adaptability, and the new numerical value after the computing of subscript " (new) " expression adaptability.In fact, if time difference signal TD by standardization (normalized) and T _DCO/ 2 about (to be TD=± 1 when the time difference of reference clock REF and feedback clock FB be ± T _DCO/ 2 (T wherein _DCOThe cycle (cycleperiod) of expression output clock OUT) and moment error signal also by standardization (in interval [1,1]), then the exemplary value of μ is 0.01.Must notice that the speed of the larger convergence of μ is faster, but adaptability noise (adaptation noise) is larger; On the contrary, On the contrary, the speed of the less convergence of μ is slower, but adaptability noise (adaptation noise) is less.In fact, μ can be set as larger value to help convergence when initial condition; And after convergence, μ is set as less value to reduce the adaptability noise.One embodiment when initial condition, is made as zero and will can be by accommodation (adapted) until numerical fraction-N phase-locked loop does not reach lower state (steady state condition) with all estimation coefficients.This lower state can be suspended by timer (time-out) and confirm that (it is to arrange according to a Preset Time, this Preset Time is that numerical fraction-N phase-locked loop reaches the time of stable state) or falling into standard time interval [1,1] fully by acknowledging time difference signal TD confirms.This adaptability computing can be carried out continuously or off and on.

In brief, in an exemplary embodiments, the adaptability series expansion equation block 280A that Fig. 2 A shows is reception moment error signal and residual value error signal RE, and produces default error signal PE according to equation (10), (11) with the Legnedre polynomial of equation (1)～(6) definition.When the inferior numerical basis user's of the item of Legendre polynomial expansion (equation (10)) judgement is selected, normally select 4～6 items namely enough to obtain satisfied accuracy.Moreover those skilled in the art can be in every way, form is implemented all equations, as long as possess mathematical equivalence (mathematical equivalence).For example, convertible Legnedre polynomial progression to Taylor series (Taylor series) pass through to collect the moment error

The item of same order (order of power) (is namely collected the item of all ε, all ε ², all ε ³...).

The schematic diagram of the numerical fraction of Fig. 2 B demonstration another embodiment of the present invention-N phase-locked loop 200B.This series expansion is (to substitute residual value error signal RE) take time difference signal TD as the basis.In this, an adaptability series expansion equation block 280B who replaces is used for the adaptability series expansion equation block 280A of alternate figures 2A.Identical Legnedre polynomial progression (equation (10)) still is used for estimating predictive error signal PE, but its coefficient part then adopts following formula:

${\hat{c}}_n^{\left(\mathrm{new}\right)}=\frac{<P_n\left(\mathrm{\&epsiv;}\right),\mathrm{TD}>}{<P_n\left(\mathrm{\&epsiv;}\right),P_n\left(\mathrm{\&epsiv;}\right)>}---\left(12\right)$

Wherein, n=0,1,2,3 ..., and＜A, B〉the expression A statistical average (statistical average) of multiply by B (A times B).In brief, in the embodiment of this replacement, the adaptability series expansion equation block 280B of Fig. 2 B receive moment error signal with time difference signal TD, and produce predictive error signal PE according to equation (10), (12) with the Legnedre polynomial that is defined by equation (1)～(6).Must note, again state those skilled in the art can according to its demand in every way, form implements all equations, as long as possess mathematical equivalence (mathematical equivalence).Moreover, must notice that the unit of equation (12) is the constant of learning in advance, does not need to go out according to digital estimation.If moment, error signal was by standardization and fall within pre-set interval, for example [1 ,-1], just so can know in advance, and must not carry out the estimation of lower column of figure

$\frac{1}{<P_n\left(\mathrm{\&epsiv;}\right),P_n\left(\mathrm{\&epsiv;}\right)>}=\frac{2n+1}{2}---\left(13\right)$

Orthogonal property according to equation (7).One embodiment, all estimation coefficients are to be set as zero under initial condition, and will can not be used in adaptability computing (adapted) until numerical fraction-N phase-locked loop reaches lower state (steady state condition).Must notice that adaptability computing (adaptation) (equation (12)) can be implemented continuously or off and on.

Time-to-digital converter 210 and the numerically-controlled oscillator 230 of Fig. 2 A of the present invention, 2B embodiment are the technology that those skilled in the art were familiar with, and therefore repeat no more its details.And if be unfamiliar with time-to-digital converter, can be with reference to No. 7205924, US Patent No..Can be with reference to United States Patent (USP) US7183860 number if be unfamiliar with numerically-controlled oscillator.

Digital loop filter 220 can be selected by the required filter response of circuit designers judgment basis.In an exemplary embodiment, digital loop filter 220 can be carried out following discrete-time system response type:

H(z)＝K _Pz ^-1+K ₁z ^-1/(1-z ^-1) (14)

Wherein, K _PWith K ₁Two parameters can be specified by circuit designers.

Double modulus divider 250 can be a counter divider (counter-based divider), and its divider value that adopts can be N _Int(when CARRY is 1) or N _Int+ 1 (when CARRY is 0).Wherein, N _IntRemove the integer part of calculation ratio (fractioral division ratio) for the numerical fraction of numerical fraction N-type phase-locked loop (200A or 200B).Therefore those skilled in the art repeat no more its details as long as be familiar with the execution mode that counter double modulus division circuit just can be familiar with in the phase-locked loop.

Fig. 3 shows the schematic diagram of the triangular integration modulator 300 of one embodiment of the invention.Triangular integration modulator 300 is applicable to implement the triangular integration modulator 260 among Fig. 2 A or the 2B.Modulator 300 is and feedback clock FB synchronous operation.Modulator 300 includes first and adds way circuit 310, integrator 320, the arithmetic unit that rounds off (Rounding operator) 330, second and add way circuit 340 and gain/postpone (gain/delay) element 350.Modulator 300 is essentially accumulator (accumulator), and it utilizes integrator 320 cumulative mark α (wherein 0＜α＜1).Round off arithmetic unit 330 with the accumulation amount computing of rounding off, to produce delivery signal CARRY.When accumulation amount surpasses 0.5, delivery signal CARRY is 1, and first adds way circuit 310 with the numerical value-1 of accumulator; Do not surpass 0.5 and work as accumulation amount, delivery signal CARRY is 0, and must not deduct the numerical value of accumulator any numerical value this moment.Mode according to this, accumulation amount can be controlled in interval [0.5,0.5], and delivery signal CARRY only can be 0 or 1.

Moment, error signal was to utilize second to add the input and output time difference that way circuit 340 calculates the arithmetic unit 330 that rounds off, and postponed and/or the convergent-divergent generation by 350 pairs of these time differences of gain/delay element.As shown in Figure 3, the factor (factor) z-1 of gain/delay element 350 marks represents a unit delay, and whether the factor 2 is fallen within the interval [1,1] by standardization in order to the result who confirms moment error ε for gain factor.

Only otherwise break away from spirit of the present invention and scope, the embodiment that technology of the present invention can various replacements realizes.For example, the triangular integration modulator of higher-order (DSM) also can be used in the present invention.Mode according to this, delivery signal CARRY is not binary signal, and can become multistage integer signal (Multi-levelinteger signal), and the double modulus divider need be replaced with multi-modulus divider.

In addition, various types of series expansion also can be used to replace Legnedre polynomial progression.For example, can utilize Taylor series (Taylor series), Fourier series (Fourier series) ... replace.Those skilled in the art are not breaking away under spirit of the present invention and the category, can judge voluntarily according to its demand, use to select suitable mathematics series expansion.For example, when selecting Taylor series to replace, need only respectively the equation Pn (x) that is defined in the Legnedre polynomial of equation (1)～(6) (n=0～5) be replaced with P ' _n(x)=x ⁿ(n=0～5).Yet, must notice that equational power (power functions) is not quadrature each other.That is to say P ' _n(x)=x ⁿNot with P ' _m(x)=x ^mQuadrature supposes that n is not equal to m.(two equation quadratures are not have statistic correlation (zero statisticalcorrelation) just to set up between two equations.Mode according to this, the embodiment 200B of Fig. 2 B and equation (12) merge makes to carry out adaptability computing (adaptation) and inappropriate, because equation (12) is take orthogonal property as the basis, the merging of equation (12) only use fundamental equation expand into quadrature the time just suitably.Yet the embodiment 200B of Fig. 2 B still can use, as long as the adaptability computing of replacing includes Gram-Schmidt process (Gram-Schmidt orthgonalization).Gram-Schmidt process is familiar with by those skilled in the art, repeats no more its details; If the person of being unfamiliar with, but the mathematics textbook of normative reference.In any case, when the embodiment 200B of choice for use Fig. 2 B, can adopt those quadrature equations as series expansion.

Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, those skilled in the art can carry out various distortion or change, all fall into the category of claim scope of the present invention.

Claims (19)

1. A fractional-N phase-locking device for eliminating phase noise, the fractional-N phase-locking device comprises: a time-to-digital converter for converting the time difference between the reference clock and the feedback clock into a time difference signal; a canceling circuit for receiving the time difference signal, and generating a residual error signal according to the time difference signal and the instantaneous error signal; a digital loop filter, configured to filter the residual error signal to generate a handle; a numerically controlled oscillator for generating an output clock in accordance with the control of the handle; and a dividing circuit for receiving a fractional value between 0 and 1 to generate the instantaneous error signal; and dividing the output clock by a divisor value according to the control of the fractional value to generate the feedback clock, Wherein the elimination circuit includes: a series expansion unit for matching the instantaneous error signal to a preset error signal; and The summing circuit subtracts the preset error signal from the time difference to generate the residual error signal. 2. The fractional-N phase locking device according to claim 1, wherein the series expansion unit is adapted to minimize the correlation of the instantaneous error signal and the residual signal. 3. The fractional-N phase-locking device according to claim 1, wherein the series expansion unit is adapted to calculate the correlation between the time difference signal and the instantaneous error signal. 4. The fractional-N phase locking device according to claim 1, wherein the series expansion unit has a power series of adaptive coefficients. 5. The fractional-N phase locking device according to claim 4, wherein the adaptive coefficient is based on a least mean square algorithm. 6. The fractional-N phase locking device according to claim 1, wherein the series expansion unit is a Legendre polynomial series with adaptive coefficients. 7. The fractional-N phase locking device according to claim 6, wherein the adaptive coefficient is based on a least mean square algorithm. 8. The fractional-N phase-locked device according to claim 1, wherein the dividing circuit comprises: a delta-sigma modulator for receiving the fractional value to generate a carrying signal and the instantaneous error signal; and The divider is used for dividing the output clock by a divisor according to the control of the carrying signal. 9. The fractional-N phase-locked device as claimed in claim 8, wherein the delta-sigma modulator operates synchronously with the feedback clock. 10. The fractional-N phase-locking device according to claim 8, wherein when the carrying signal is logic 1, the divisor value is a first integer; when the carrying signal is logic 0, the divisor value is a second integer . 11. The fractional-N phase-locked device according to claim 8, wherein the delta-sigma modulator comprises at least one integrator. 12. The fractional-N phase-locked device according to claim 11, wherein the delta-sigma modulator comprises a rounding circuit. 13. A method for reducing phase noise of a fractional-N phase-locked loop, comprising: Quantizing the time difference between the reference clock and the feedback clock to generate a time difference signal; generating a residual value error signal according to the time difference signal and the instantaneous error signal; filtering the residual error signal to generate a handle; Use this handle to control the oscillator to generate the output clock; receiving a fractional value to generate the instantaneous error signal; and The output clock is divided by a divisor value according to the fractional value. 14. The method of claim 13, further comprising: performing delta-sigma modulation with the fractional value to generate the carrier signal and the instantaneous error signal; Wherein, the divisor value should correspond to the carrying signal. 15. The method according to claim 13, wherein the step of generating the residual error signal comprises: using a series expansion to map the instantaneous error signal to a preset error signal; Wherein, the series expansion formula includes a linear combination of a plurality of basic equations with respective coefficients. 16. The method according to claim 15, wherein the step of generating the residual error signal further comprises: Using one of the coefficients is selected according to the correlation between an individual basic equation and the residual error signal, or the correlation between the individual basic equation and the time difference signal. 17. The method of claim 15, wherein the series expansion is a power series. 18. The method of claim 15, wherein the series expansion is a Legendre polynomial series. 19. The method of claim 13, wherein the score value is between 0 and 1.

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