CN101667556A - A kind of through-hole etching method - Google Patents

Abstract

A through hole etching method comprises the following steps: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a dielectric layer; forming a sacrificial layer on the surface of the dielectric layer; patterning the sacrificial layer and forming openings in the sacrificial layer to define via locations; performing a first anisotropic dry etching process by using the patterned sacrificial layer as a mask, etching the dielectric layer until the dielectric layer is exposed or close to the surface of the substrate, and etching a through hole in the dielectric layer; executing an isotropic dry etching process to enlarge the size of the opening in the sacrificial layer; taking the sacrificial layer with the enlarged opening as a mask, executing a second anisotropic dry etching process, and over-etching to form a through hole with a goblet-shaped outline; and removing the sacrificial layer. The invention has the advantages that the control of the size of the bottom of the prepared through hole is more accurate; only a dry etching method is used, only one program is needed, and the forming can be carried out in one machine at one time, so that the production efficiency is greatly improved.

Description

A kind of through-hole etching method

technical field

The invention belongs to the technical field of integrated circuit manufacturing and relates to a through hole etching method.

Background technique

With the rapid development of semiconductor technology, the feature size of semiconductor devices is significantly reduced, and the size of the through hole is also significantly reduced. However, the thickness of the dielectric layer that needs to be opened cannot be reduced in proportion to the size of the through hole, so the aspect ratio of the through hole The larger and larger, it is easy to generate a "bottleneck" 100 (as shown in FIG. 1 ) in the via hole during the subsequent high-temperature reflow process, so that the subsequent filling of metals such as tungsten or aluminum in the via hole fails.

The usual method to solve this problem is to change the structure of the through hole so that the opening of the through hole has a certain slope. There are many ways to prepare such through-holes with openings having a certain slope. 2A-C are schematic flow charts of a typical via hole etching method. First, as shown in FIG. 2A, using the patterned sacrificial layer 200 as a mask, a through-hole opening 211 with a circular arc profile is etched in the dielectric layer 210 by an isotropic etching method; then, as shown in FIG. As shown in FIG. 2B , an anisotropic etching method is used to etch a via hole at the bottom of the via hole opening 211 with a circular arc profile to the surface of the substrate 220 . After removing the sacrificial layer, a via hole 212 as shown in FIG. 2C is obtained. The through hole 212 etched by this method has the characteristics of a small bottom and a large opening, and no "bottleneck" will be generated during the high temperature reflow process. However, this method first uses the isotropic etching method, and the opening size of the isotropic etching is not easy to control, which will cause the bottom size to be difficult to control; in addition, this method uses isotropic etching and anisotropic etching Two different methods, the former often uses wet etching, and the latter often uses dry etching, which needs to be carried out in different machines, and the production efficiency is very low.

Contents of the invention

The technical problem to be solved by the present invention is that the size of the bottom of the through-hole prepared by the through-hole etching method in the prior art is difficult to control, and the production efficiency is very low.

In order to solve the above technical problems, the present invention provides a method for etching through holes, comprising:

providing a semiconductor substrate having a dielectric layer;

forming a sacrificial layer on the dielectric layer;

patterning the sacrificial layer and forming openings in the sacrificial layer to define via locations;

Using the patterned sacrificial layer as a mask, perform a first anisotropic dry etching process, etch the dielectric layer until the surface of the substrate is exposed, and etch through holes in the dielectric layer ;

performing an isotropic dry etching process to enlarge the size of the opening in the sacrificial layer;

Using the sacrificial layer with the enlarged opening as a mask, performing a second anisotropic dry etching process, and overetching to form a wine glass-shaped via hole;

The sacrificial layer is removed.

所述第一各向异性干法刻蚀的气体为C_xF_y、O2、Ar和CO。所述各向同性干法刻蚀的气体为O₂。所述第二各向异性干法刻蚀的气体为C_xF_y、O₂、Ar和CO。Wherein, the sacrificial layer is a uniformly coated photoresist layer with a thickness greater than

The gas used for the first anisotropic dry etching is C _x F _y , O2, Ar and CO. The gas used for the isotropic dry etching is O ₂ . The gases used for the second anisotropic dry etching are C _x F _y , O ₂ , Ar and CO.

The present invention provides another through hole etching method, comprising:

providing a semiconductor substrate having a dielectric layer;

forming a sacrificial layer on the dielectric layer;

patterning the sacrificial layer and forming openings in the sacrificial layer to define via locations;

Using the patterned sacrificial layer as a mask, performing a first anisotropic dry etching process, etching the dielectric layer close to the surface of the substrate, and etching primary via holes in the dielectric layer ;

performing an isotropic dry etching process to enlarge the size of the opening in the sacrificial layer;

Using the enlarged sacrificial layer as a mask, perform a second anisotropic dry etching process, etch the dielectric layer below the bottom of the primary via hole to expose the substrate surface, and over-etch A through hole forming a wine glass-like profile;

The sacrificial layer is removed.

所述第一各向异性干法刻蚀的气体为C_xF_y、O₂、Ar和CO。所述各向同性干法刻蚀的气体为O₂。所述第二各向异性干法刻蚀的气体为C_xF_y、O₂、Ar和CO。Wherein, the sacrificial layer is a uniformly coated photoresist layer with a thickness greater than

The gas used for the first anisotropic dry etching is C _x F _y , O ₂ , Ar and CO. The gas used for the isotropic dry etching is O ₂ . The gases used for the second anisotropic dry etching are C _x F _y , O ₂ , Ar and CO.

Compared with the prior art, the present invention has the following advantages and positive effects due to the adoption of the above-mentioned technical solution:

1. First use anisotropic etching to contact the bottom of the through hole, define the size of the bottom, and then expand the opening of the through hole, so that the control of the bottom size will be more accurate;

2. Only dry etching method is used, and there is only one program, which can be formed in one machine at one time, and the production efficiency is greatly improved.

Description of drawings

Figure 1 is a schematic diagram of a via with a "bottleneck".

2A to 2C are schematic flow charts of a conventional method for etching through holes.

3A to 3G are schematic flowcharts of a method for etching via holes according to Embodiment 1 of the present invention.

3A, 3B, 3H, 3I, 3E, 3F, and 3G are schematic flow charts of a via hole etching method according to Embodiment 2 of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

3A to 3G are schematic flow diagrams of a through hole etching method according to an embodiment of the present invention. The schematic diagrams are only examples, and the protection scope of the present invention should not be excessively limited here. In the via hole etching method of the embodiment of the present invention, the via hole is formed in the dielectric layer on the surface of the semiconductor substrate. The semiconductor substrate can be single crystal silicon or germanium, which can also include electronic devices such as MOS-FET (metal oxide semiconductor field effect transistor), bipolar (bipolar transistor) formed in the semiconductor material (also other?) and electrode contact area. The dielectric layer may be a pre-metal dielectric layer (PMD) or an interlayer dielectric layer (ILD). The via holes in the PMD layer are used to connect the electrodes of the electronic devices in the semiconductor substrate and the metal wires in the upper interconnection layer. Vias in the ILD layer are used to connect wires in adjacent metal interconnect layers. The dielectric layer may include one ILD layer, or multiple ILD layers, such as 2, 3 or 4 layers. The present invention takes etching via holes in the PMD layer as an example.

At first, as shown in Figure 3A, semiconductor substrate 310 is a silicon substrate, and the dielectric layer on the surface of this semiconductor substrate 310 is a PMD layer 320, and the material of this PMD layer 320 is oxide and nitride of silicon, with chemical vapor phase The deposition method deposits onto the surface of the semiconductor substrate 310 .

本实施例中选用光致抗蚀剂层为牺牲层，也可以采用其他材料作为牺牲层，不限于本实施例。用传统的光刻工艺图案化该光致抗蚀剂层330，形成开口331以界定通孔位置。Then, as shown in Figure 3B, one layer of photoresist layer 330 is coated on the surface of PMD layer 320 as a sacrificial layer, and the thickness of this photoresist layer 330 is greater than

In this embodiment, the photoresist layer is selected as the sacrificial layer, and other materials may also be used as the sacrificial layer, which is not limited to this embodiment. The photoresist layer 330 is patterned using a conventional photolithography process to form openings 331 to define via locations.

Next, as shown in FIG. 3C, using the photoresist layer 330 formed with the opening 331 as a mask, a first anisotropic dry etching process is used to etch the PMD layer 320 to expose the substrate 310 On the surface, a through hole 321 is etched in the dielectric layer 320 . The power of the first anisotropic dry etching process is 1500-1700W, the gas pressure is 45-55mT, the etching gases used are C _x F _y , O ₂ , Ar and CO, and the corresponding gas flow rates are 9 ~14 sccm, 5-10 sccm, 180-240 sccm, 45-60 sccm.

若开口331为矩形，则开口331的长和宽各自扩大少于

该各向同性干法刻蚀的工艺，功率为200～400W，气压为100mT～200mT，采用的刻蚀气体为O₂，流量为300～500sccm。开口331的尺寸扩大后，通孔321的开口边缘322就暴露出来。Next, as shown in FIG. 3D , the opening 331 is etched by an isotropic dry etching process to enlarge the size of the opening 331 to control the size of the top of the via hole 321 . For example, if the opening 331 is circular, the diameter of the opening 331 expands less than

If the opening 331 is a rectangle, then the length and width of the opening 331 are enlarged by less than

In the isotropic dry etching process, the power is 200-400W, the gas pressure is 100mT-200mT, the etching gas used is O ₂ , and the flow rate is 300-500 sccm. After the size of the opening 331 is enlarged, the opening edge 322 of the through hole 321 is exposed.

Then, as shown in FIG. 3E , using the photoresist layer 330 with the enlarged opening 331 as a mask, the top of the via hole 321 is etched by a second anisotropic dry etching process to form a The via hole 325 is shown in FIG. 3E with a wine glass profile; meanwhile, the over-etching fully exposes the surface of the substrate 310 . The second anisotropic dry etching process has two effects. One is to etch the top of the via hole 321. Since the opening edge 322 of the via hole 321 protrudes at a sharp angle, the second anisotropic dry etching process The etching rate of the etching process gradually slows down from the opening edge 322 to the plane area away from the opening edge 322 , so an arc-shaped sidewall 323 is formed under the through hole 321 , and finally a wine glass-shaped through hole 325 is formed. At the same time, because the anisotropic etching process is adopted, the size of the bottom of the through hole 321 hardly changes, thus ensuring the precise control of the bottom of the through hole. The second is to over-etch the exposed surface of the substrate 310 so that the surface of the substrate 310 is fully exposed.

Finally, as shown in FIG. 3F , the photoresist layer 330 is removed by conventional methods.

The through hole formed after the wine glass profile shown in FIG. 3F undergoes a high temperature reflow process is shown in FIG. 3G .

Another embodiment of etching via holes in the PMD layer of the present invention is as follows.

At first, as shown in Figure 3A, semiconductor substrate 310 is a silicon substrate, and the dielectric layer on the surface of this semiconductor substrate 310 is a PMD layer 320, and the material of this PMD layer 320 is oxide and nitride of silicon, with chemical vapor phase The deposition method deposits onto the surface of the semiconductor substrate 310 .

本实施例中选用光致抗蚀剂层为牺牲层，也可以采用其他材料作为牺牲层，不限于本实施例。用传统的光刻工艺图案化该光致抗蚀剂层330，形成开口331以界定通孔位置。Then, as shown in Figure 3B, one layer of photoresist layer 330 is coated on the surface of PMD layer 320 as a sacrificial layer, and the thickness of this photoresist layer 330 is greater than

In this embodiment, the photoresist layer is selected as the sacrificial layer, and other materials may also be used as the sacrificial layer, which is not limited to this embodiment. The photoresist layer 330 is patterned using a conventional photolithography process to form openings 331 to define via locations.

Next, as shown in FIG. 3H, using the photoresist layer 330 formed with the opening 331 as a mask, a first anisotropic dry etching process is used to etch the PMD layer 320 to the surface close to the substrate 310 , etching a primary via hole 324 in the dielectric layer 320 . The power of the first anisotropic dry etching process is 1500-1700W, the gas pressure is 45-55mT, the etching gases used are C _x F _y , O ₂ , Ar and CO, and the corresponding gas flow rates are 9 ~14 sccm, 5-10 sccm, 180-240 sccm, 45-60 sccm.

若开口331为矩形，则开口331的长和宽各自扩大少于

该各向同性干法刻蚀的工艺，功率为200～400W，气压为100mT～200mT，采用的刻蚀气体为O₂，流量为300～500sccm。开口331的尺寸扩大后，初级通孔324的开口边缘322就暴露出来。Next, as shown in FIG. 3I , the opening 331 is etched by an isotropic dry etching process to enlarge the size of the opening 331 to control the size of the top of the primary through hole 324 . For example, if the opening 331 is circular, the diameter of the opening 331 expands less than

If the opening 331 is a rectangle, then the length and width of the opening 331 are enlarged by less than

In the isotropic dry etching process, the power is 200-400W, the gas pressure is 100mT-200mT, the etching gas used is O ₂ , and the flow rate is 300-500 sccm. After the size of the opening 331 is enlarged, the opening edge 322 of the primary through hole 324 is exposed.

Later, as shown in FIG. 3E , using the photoresist layer 330 with the enlarged opening 331 as a mask, the top of the primary via hole 324 is etched by a second anisotropic dry etching process to form A through hole 325 with a wine glass-shaped profile as shown in FIG. 3E; at the same time, etch the dielectric layer below the bottom of the primary through hole 324 to expose the surface of the substrate 310, and over-etch to fully expose the substrate 310, finally forming a wine glass The through hole 325 of the shape profile. The second anisotropic dry etching process has two functions, one is to etch the top of the primary through hole 324, since the opening edge 322 of the primary through hole 324 protrudes at a sharp angle, the second anisotropic dry etching process The etching rate of the conventional etching process gradually slows down from the edge of the opening 322 to a plane area away from the edge of the opening 322 , so that an arc-shaped sidewall 323 is formed under the primary through hole 324 . At the same time, because the anisotropic etching process is adopted, the size of the bottom of the through hole 321 hardly changes, thus ensuring the precise control of the bottom of the through hole. The second is to etch the dielectric layer below the bottom of the primary through hole 324 to expose the surface of the substrate 310 , and over-etch to fully expose the substrate 310 .

Finally, as shown in FIG. 3F , the photoresist layer 330 is removed by conventional methods.

The through hole formed after the wine glass profile shown in FIG. 3F undergoes a high temperature reflow process is shown in FIG. 3G .

Many widely different embodiments may also be constructed without departing from the spirit and scope of the invention. It should be understood that the invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

Claims (12)

1. etching method for forming through hole comprises:

Semi-conductive substrate is provided, and described Semiconductor substrate has dielectric layer;

Form sacrifice layer at described dielectric layer;

The described sacrifice layer of patterning also forms opening to define lead to the hole site in described sacrifice layer;

With described patterned sacrificial layers is mask, carries out the first anisotropic dry etch processing procedure, and the described dielectric layer of etching goes out etching through hole to exposing described substrate surface in described dielectric layer;

Carry out an isotropic dry etch processing procedure, enlarge the size of described sacrifice layer split shed;

With the sacrifice layer after the described opening expansion is mask, carry out the second anisotropic dry etch processing procedure, and over etching forms the through hole of goblet shape profile;

Remove described sacrifice layer.

2. etching method for forming through hole according to claim 1 is characterized in that: the photoresist layer of described sacrifice layer for evenly being coated with.

3. etching method for forming through hole according to claim 2 is characterized in that: the thickness of described photoresist layer greater than

4. etching method for forming through hole according to claim 1 is characterized in that: the gas of described first anisotropic dry etch is C _xF _y, O ₂, Ar and CO.

5. etching method for forming through hole according to claim 1 is characterized in that: the gas of described isotropic dry etch is O ₂

6. etching method for forming through hole according to claim 1 is characterized in that: the gas of described second anisotropic dry etch is C _xF _y, O ₂, Ar and CO.

7. etching method for forming through hole comprises:

Semi-conductive substrate is provided, and described Semiconductor substrate has dielectric layer;

Form sacrifice layer at described dielectric layer;

The described sacrifice layer of patterning also forms opening to define lead to the hole site in described sacrifice layer;

With described patterned sacrificial layers is mask, carries out the first anisotropic dry etch processing procedure, and the described dielectric layer of etching etches elementary through hole near described substrate surface in described dielectric layer;

Carry out an isotropic dry etch processing procedure, enlarge the size of described sacrifice layer split shed;

Sacrifice layer after enlarging with described opening is a mask, carries out the second anisotropic dry etch processing procedure, and the following dielectric layer of the described elementary via bottoms of etching is to exposing described substrate surface, and over etching forms the through hole of goblet shape profile;

Remove described sacrifice layer.

8. etching method for forming through hole according to claim 7 is characterized in that: the photoresist layer of described sacrifice layer for evenly being coated with.

9. etching method for forming through hole according to claim 8 is characterized in that: the thickness of described photoresist layer greater than

10. etching method for forming through hole according to claim 7 is characterized in that: the gas of described first anisotropic dry etch is C _xF _y, O ₂, Ar and CO.

11. etching method for forming through hole according to claim 7 is characterized in that: the gas of described isotropic dry etch is O ₂

12. etching method for forming through hole according to claim 7 is characterized in that: the gas of described second anisotropic dry etch is C _xF _y, O ₂, Ar and CO.

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