CN101655825A - Device for achieving LPC-USB two-way communication by using FPGA and data conversion method of LPC-US and USB-LPC - Google Patents
Device for achieving LPC-USB two-way communication by using FPGA and data conversion method of LPC-US and USB-LPC Download PDFInfo
- Publication number
- CN101655825A CN101655825A CN200810142483A CN200810142483A CN101655825A CN 101655825 A CN101655825 A CN 101655825A CN 200810142483 A CN200810142483 A CN 200810142483A CN 200810142483 A CN200810142483 A CN 200810142483A CN 101655825 A CN101655825 A CN 101655825A
- Authority
- CN
- China
- Prior art keywords
- lpc
- usb
- data
- bus
- buffer zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 52
- 230000006854 communication Effects 0.000 title claims abstract description 44
- 238000004891 communication Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000005540 biological transmission Effects 0.000 claims abstract description 25
- 239000000872 buffer Substances 0.000 claims description 101
- 238000012546 transfer Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 11
- 101000890887 Homo sapiens Trace amine-associated receptor 1 Proteins 0.000 claims description 9
- 102100040114 Trace amine-associated receptor 1 Human genes 0.000 claims description 9
- 230000010354 integration Effects 0.000 abstract 1
- 101100424383 Rattus norvegicus Taar4 gene Proteins 0.000 description 8
- 101150084220 TAR2 gene Proteins 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 101100372898 Caenorhabditis elegans vha-5 gene Proteins 0.000 description 1
- 102100031699 Choline transporter-like protein 1 Human genes 0.000 description 1
- 102100035954 Choline transporter-like protein 2 Human genes 0.000 description 1
- 241000218691 Cupressaceae Species 0.000 description 1
- 101000940912 Homo sapiens Choline transporter-like protein 1 Proteins 0.000 description 1
- 101000948115 Homo sapiens Choline transporter-like protein 2 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Information Transfer Systems (AREA)
Abstract
The invention relates to a device for achieving LPC-USB two-way communication by using an FPGA and a data conversion method. The device comprises an LPC bus, a USB bus, a field programmable logic device and a USB module, wherein the field programmable logic device finishes the protocol conversion and transmission from LPC data to USB data from the LPC bus to the USB bus, and finishes the protocolconversion and transmission from the USB data to the LPC data from the USB bus to the LPC bus. The device achieves the full-duplex communication of the LPC bus and the USB bus by using the FPGA so asto satisfy certain special application occasions and solve the problems of the short-range communication of two or more computers without the help of other media. The device adopts a scheme with the FPGA and a USB control chip, and two FIFOs are arranged in the FPGA to replace an external FIFO so as to achieve high integration, and an integrated circuit board is manufactured to have the minimum area, the lowest power consumption and the least cost. Besides, the device uses the characteristic of occupying fewer ports of the FIFO to ensure that FIFO only occupies an address space of less than 2bits in a PC, thereby greatly saving the address space. Simultaneously, the device uses the characteristic of parallel high speed of the FPGA so that the scheme can satisfy the high-speed full-duplexcommunication.
Description
Technical field
The present invention relates to the device of two-way communication, more particularly, relate to device and LPC-USB and USB-LPC data transfer device that a kind of FPGA of use realizes the LPC-USB two-way communication.
Background technology
(Low Pin Count, LPC) bus is a data address command multiplex bus of Intel (Intel) company definition to low pin number, is operated in 33MHz (megahertz).In computer realm, lpc bus replaced gradually industrial standard architectures (Industry Standard Architecture, ISA), X-bus (X bus) etc. and become new interface.
Lpc bus has string characteristic also, and some characteristics of existing universal serial bus have some characteristics of parallel bus again simultaneously.In communication process, have frame signal, synchronizing signal, answer signal in the conventional serial communication protocol, but be again parallel data transmission in whole communication process with 4.
Yet, still have at present a lot of peripherals that the bus interface of other types only is provided, as USB interface etc.Because the frequency of operation of these buses, data address bus width and read-write sequence or the like are different with lpc bus, and the certain operation of needs could realize the communication between them.Communication between them need be resolved the agreement of lpc bus, carries out the conversion of agreement.
At industrial control field, at present a lot of industrial control computer mainboards can provide a plurality of USB interface, but can not realize the direct communication with lpc bus.Industry is devoted to develop adapter in the hope of realizing communicating by letter between lpc bus and the USB easily.
Can realize that the technical scheme of communicating by letter between the LPC-USB has:
1, with CPLD or FPGA, the external dual port RAM+USB chip of arranging in pairs or groups carries out full-duplex communication; Its shortcoming: dual port RAM independently, price is high; The operation dual port RAM, the easy problem that competition occurs, in the time of just same, write operation is carried out to same address simultaneously in the RAM both sides, and data will be lost; The address space of RAM must all be mapped to the addressing space of computing machine, and the capacity of RAM is big more, and the address space that takies is also big more; The data-moving of RAM needs software to do complicated space management, realize that the data of different addresses are had different operations, complicated technology realization.
2, use CPLD or FPGA separately, external 2 fifo chips+USB chip of arranging in pairs or groups carries out full-duplex communication; Its shortcoming: need simultaneously with 2 fifo chips, expensive; Need be with FPGA or CPLD, the interface routine and the FIFO that write FIFO carry out data communication; Need use 4 IC, increase the integrated circuit board area, also increase power consumption simultaneously.
3, FPGA embedded processor, as (NIOS II, Microblaze), plug-in single port RAM+USB chip communicates; Its shortcoming: embedded processor at first needs the FPGA of larger capacity, the bad grasp of cost; Because be embedded processor, thus in the single time, be merely able to a port is operated, so can only be semiduplex mode; Because message transmission rate is up to 10MB/S, if use embedded processor, with regard to necessary plug-in speed buffering module, and the not high soft processor of performance will be the bottleneck place of data channel.
Summary of the invention
The technical problem to be solved in the present invention is, at the above-mentioned defective of prior art, provides a kind of FPGA of use to realize device and the LPC-USB and the USB-LPC data transfer device of LPC-USB two-way communication.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of device that uses FPGA to realize the LPC-USB two-way communication, comprise lpc bus, usb bus, field programmable logic device and USB module; The control of described field programmable logic device is finished by protocol conversion and the transmission of lpc bus to the LPC data of usb bus to usb data, and finishes by protocol conversion and the transmission of usb bus to the usb data of lpc bus to the LPC data; Described USB module is used to realize the exchanges data of described field programmable logic device and usb bus;
Described field programmable logic device comprises: LPC-USB protocol conversion module, USB-LPC protocol conversion module, first buffer zone and second buffer zone;
Wherein, the LPC-USB protocol conversion module is used to receive the LPC data that lpc bus sends, and it is carried out sending to first buffer zone after the protocol conversion;
First buffer zone is used for by the buffer memory of LPC data to usb data protocol conversion and transport process data, and has played a good clock zone buffer action;
Second buffer zone is used to receive the usb data that the USB module sends, and is used for by the buffer memory of usb data to conversion of LPC data protocol and transport process data, and has played a good clock zone buffer action;
The USB-LPC protocol conversion module is used to receive the usb data of second buffer zone output, and it is carried out sending lpc bus after the protocol conversion.
Realize that at use FPGA of the present invention described first buffer zone and second buffer zone all are the fifo buffers that can carry out 16K byte reading and writing data in the device of LPC-USB two-way communication.
Realize in the device of LPC-USB two-way communication that at use of the present invention FPGA the enable signal of writing of described first buffer zone links to each other, reads that enable signal links to each other with the control end of described USB module, clock signal links to each other with the control end of described lpc bus with the USB module respectively with the control end of described lpc bus.
Realize in the device of LPC-USB two-way communication that at use of the present invention FPGA the enable signal of reading of described second buffer zone links to each other, writes that enable signal links to each other with the control end of described USB module, clock signal links to each other with the control end of described lpc bus with the USB module respectively with the control end of described lpc bus.
Realize in the device of LPC-USB two-way communication at use FPGA of the present invention, described field programmable logic device also comprises: the clock control administration module, it comprises input end, first output terminal and second output terminal, wherein, input end links to each other with outside global clock pin, the clock same-phase of the output of first output terminal and input end, the clock antiphase of the output of second output terminal and input end.
According to another aspect of the present invention, provide a kind of at using FPGA to realize the LPC-USB data transfer device of the device of LPC-USB two-way communication, it may further comprise the steps:
S11, current state is set is initial state;
S12, when the Senior Three position of described lpc bus is 011 and frame signal when being 1, it is address state that current state is set;
S13, reception 32 bit address, it is data mode that current state is set;
S14, reception 8 bit data, it is the TAR1 state that current state is set;
S15, when described lpc bus is 1111 and frame signal when being 1, judge whether low 20 of described 32 bit address are 0XD0000, if it is sync state that current state is set, otherwise, enter step S1;
S16, described 8 bit data are sent to first buffer zone;
S17, end LPC-USB data-switching.
In LPC-USB data transfer device of the present invention, also comprise between step S11 and S12: it is high-impedance state that described lpc bus is set, and the enable signal of writing of first buffer zone puts 0;
In LPC-USB data transfer device of the present invention, in step S13, receive 4 bit address in each LPC_CLK clock period, through 8 LPC_CLK clock period, receive described 32 bit address.
In LPC-USB data transfer device of the present invention, in step S14, receive 4 bit data in each LPC_CLK clock period, through 2 LPC_CLK clock period, receive described 8 bit data.
In LPC-USB data transfer device of the present invention, in step S16, before sending described 8 bit data, comprise that also the enable signal of writing that first buffer zone is set is 1, and described lpc bus is set is 0000.
According to a further aspect of the invention, provide a kind of at using FPGA to realize the USB-LPC data transfer device of the device of LPC-USB two-way communication, it may further comprise the steps:
S21, current state is set is initial state;
S22, when the Senior Three position of described lpc bus is 010 and frame signal when being 1, it is address state that current state is set;
S23, reception 32 bit address, it is the TAR1 state that current state is set;
S24, when described lpc bus is 1111 and frame signal when being 1, judge whether low 20 of described 32 bit address are 0XD0001 or 0XD0002, if it is sync state that current state is set, and described lpc bus is set is 0101, otherwise, enter step S21;
S25, judge whether low 20 of described 32 bit address are 0XD0001, if enter step S26; Otherwise, enter step S27;
S26, the data of described second buffer zone output are sent in 8 the data register;
S27, current state is set is data mode, be provided with described lpc bus be 0000 and the enable signal of reading that described second buffer zone is set be 0;
S28, judge whether low 20 of described 32 bit address are 0XD0001, if enter step S29; Otherwise, enter step S210;
S29, the data that will be stored in described 8 data register send to described USB-LPC protocol conversion module;
S210, the 1st LPC_CLK clock period, high 2 positions 11 of described lpc bus, the empty marking signal assignment of described second buffer zone is given described lpc bus the 1st, the full scale will signal assignment of described first buffer zone is given described lpc bus the 0th, the 2nd LPC_CLK clock period, it is 1111 that described lpc bus is set;
S211, end USB-LPC data-switching.
In USB-LPC data transfer device of the present invention, also comprise between described step S21 and S22: it is high-impedance state that described lpc bus is set, and the enable signal of reading of second buffer zone puts 0.
In USB-LPC data transfer device of the present invention, in step S23, receive 4 bit address in each LPC_CLK clock period, through 8 LPC_CLK clock period, receive described 32 bit address.
In USB-LPC data transfer device of the present invention, in step S29, the 1st LPC_CLK clock period, low 4 of being stored in data in described 8 data register are sent to described USB-LPC protocol conversion module, the 2nd LPC_CLK clock period, high 4 of being stored in data in described 8 data register are sent to described USB-LPC protocol conversion module
Implement device and LPC-USB and USB-LPC data transfer device that use FPGA of the present invention realizes the LPC-USB two-way communication, has following beneficial effect: utilize FPGA to realize the full-duplex communication of lpc bus and usb bus, satisfy some particular application, two or many computing machine short-range communication problems, and do not need by realizing by other media.This device is set up two FIFO by FPGA and USB control chip scheme in FPGA inside, substitute plug-in FIFO, and reached high integrated, therefore the integrated circuit board area is accomplished minimum, and the while power consumption is accomplished minimum, and cost is accomplished minimum.In addition, utilize FIFO to have and take the few characteristic of port, make it in PC, only need take address space, thereby save address space greatly less than 2 bytes.Simultaneously, utilized the characteristic of FPGA parallel high-speed, made this programme can satisfy the high speed full-duplex communication.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is that the present invention uses FPGA to realize the system chart of the device of LPC-USB two-way communication;
Fig. 2 is the process flow diagram that device shown in Figure 1 is realized the LPC-USB data transfer device;
Fig. 3 is the state transition diagram of the state machine of Fig. 2;
Fig. 4 is the process flow diagram that device shown in Figure 1 is realized the USB-LPC data transfer device;
Fig. 5 is the state transition diagram of the state machine of Fig. 4;
Fig. 6 is first buffer zone shown in Figure 1 and the arrangement plan of second buffer zone;
Fig. 7 is the system chart of USB module shown in Figure 1;
Fig. 8 is the FPGA shown in Figure 1 and the interface connection diagram of USB module.
Embodiment
Realize device one application-specific of LPC-USB two-way communication for use FPGA of the present invention, mainly be between device A and equipment B, to carry out exchanges data, wherein device A is carried out the transmitting-receiving of data by lpc bus, and equipment B is carried out the transmitting-receiving of data by usb bus.As shown in Figure 1, use FPGA to realize comprising lpc bus, usb bus, field programmable logic device and USB module among this embodiment of device of LPC-USB two-way communication in the present invention; The control of this field programmable logic device is finished by protocol conversion and the transmission of lpc bus to the LPC data of usb bus to usb data, and finishes by protocol conversion and the transmission of usb bus to the usb data of lpc bus to the LPC data; The USB module is used to realize the exchanges data of field programmable logic device and usb bus; Comprise for this field programmable logic device: LPC-USB protocol conversion module, USB-LPC protocol conversion module, first buffer zone (FIFO1) and second buffer zone (FIFO2); Wherein, the LPC-USB protocol conversion module is used to receive the LPC data that lpc bus sends, and it is carried out sending to first buffer zone after the protocol conversion; First buffer zone is used for by the buffer memory of LPC data to usb data protocol conversion and transport process data, and has played a good clock zone buffer action; Second buffer zone is used to receive the usb data that the USB module sends, and is used for by the buffer memory of usb data to conversion of LPC data protocol and transport process data, and has played a good clock zone buffer action; The USB-LPC protocol conversion module is used to receive the usb data of second buffer zone output, and it is carried out sending lpc bus after the protocol conversion.As shown in Figure 6, first buffer zone and second buffer zone all are the fifo buffers that can carry out the 16K reading and writing data.In addition, this field programmable logic device also comprises CLKV module (clock control administration module), and this CLKV module mainly realizes the control and management to clock.The outside is sent to the clock of FPGA by the global clock pin, divides two-way output, the one tunnel with the clock same-phase of input, the one tunnel with the clock antiphase of input, as the reference clock of FPGA program design.In specific design, the device of the present patent application is also to claim the TOP module by utilization top layer software, IO interface with the definition whole procedure, and the input and output of external interface and each realized that the sub-module of concrete function is connected, realizing the logical relation between them, and realized mutual with the USB module simultaneously.
In concrete work, device A is sent to FPGA to data by lpc bus, and produces check code simultaneously, through the processing of FPGA, protocol conversion, give USB module data,, give USB interface data by the processing of USB module, this moment the equipment B reading of data, and check its correctness, to determine whether to need to start retransmission mechanism, this process realizes the communication of lpc bus data to USB.Reverse direction, equipment B is given USB module data by USB interface, through the processing of USB module, carries out transmitted in packets, be sent to FPGA and generate check code, through the processing of FPGA module, protocol conversion is given lpc bus data, the device A reading of data, and check its correctness, to determine whether to need to start retransmission mechanism, this process realizes the communication of usb data to lpc bus.Thereby realized the full-duplex communication between lpc bus and the USB.
After system powers on, lpc bus sends data to USB if desired, then device A sends data to FPGA by lpc bus, produces check code simultaneously, through the processing of FPGA, carry out protocol conversion, data are sent to the USB module, and through the processing of USB module, equipment B is by the USB interface sense data, and check its correctness, to determine whether to need to start retransmission mechanism; USB sends data to lpc bus if desired, equipment B is given USB module data by USB interface, produces check code simultaneously, after the processing through the USB module, send data to FPGA,, carry out protocol conversion through the processing of FPGA module, data are sent to lpc bus, again by the device A sense data, and check its correctness, to determine whether to need to start retransmission mechanism.Lpc bus and USB be transceive data simultaneously, to realize the full-duplex communication between them.Whole data exchange process is the transmission data of a frame one frame, and receiving data also is the reception of a frame one frame; Some information that include this frame in each frame data simultaneously comprise the information of verification and error correction aspect; After reading of data, also read simultaneously the information aspect the verification,, then sent an information, started retransmission mechanism, allowed transmit leg resend this frame data, till transmission is correct if find in this frame that certain or some data are wrong.
In concrete the enforcement, fpga chip adopts the chip of the SPARTAN3A series of XILINX company, and concrete model is XC3S200A-4FT256C, and development platform is ISE9.2.It mainly contains three groups of signals: the lpc bus desired signal of communicating by letter with FPGA, the USB module desired signal of communicating by letter with FPGA, shared data line; The definition of concrete interface signal, as following table 1:
| Signal name | Direction | Describe |
| ??LPC_FRAME_IO | ??IN | The FRAME pin position of LPC |
| ??LPC_RST_N_IO | ??IN | The LPC reset signal |
| ??LPC_CLK_IO | ??IN | The LPC clock signal |
| ??LPC_LAD_IO | ??INOUT | LPC data and address shared bus |
| ??USB_CLK | ??IN | The USB clock signal |
| ??F_FLAGA | ??IN | USB writes marking signal |
| ??F_FLAGB | ??IN | USB reads marking signal |
| ??F_SLOE | ??OUT | |
| ??F_SLRD | ??OUT | |
| ??F_SLWR | ??OUT | |
| ??UD_D | ??INOUT | The shared data line |
Table 1
For the LPC-USB protocol conversion module, it is mainly according to the LPC standard, and the lpc bus write data is come, and in FPGA inside, by protocol conversion, the data that recognize is sent into first buffer zone of FPGA inside.There are various modes, this modular design mainly to utilize Memory Target WriteMode transmission data during lpc bus transmission data.Lpc bus has multiple different state when the transmission data, this module mainly realizes the conversion of different conditions with state machine, to realize that terminal computer is write FIFO1 by the data that lpc bus sends through after the protocol conversion.
Shown in Fig. 2 and 3, behind electrification reset, state machine enters initial state, and promptly current state is an initial state;
When each LPC_CLK rising edge clock comes to begin the judgement to current state temporarily;
When current state is initial state, at first make the data line of lpc bus place high-impedance state, the enable signal of writing of first buffer zone puts 0, when the data line that determines lpc bus is 0000 and frame signal when being 0, state machine is transferred to the DIR state, be that current state changes to the DIR state, otherwise allow current state be in initial state;
When current state is the DIR state, at first make the data line of lpc bus place high-impedance state, the enable signal of writing of first buffer zone puts 0, when the data line signal that determines lpc bus is 011 and frame signal when being 1, state machine is transferred to address state, be that current state changes to address state, otherwise allow its current state be in initial state;
When current state is address state, at first make the data line of lpc bus place high-impedance state, the enable signal of writing of first buffer zone puts 0, and each LPC_CLK clock period is transmitted 4 bit address, through 8 LPC_CLK clock period, the data line of 32 addresses by lpc bus sent, wherein high 12 ignore need not, low 20 effectively, state machine is transferred to data mode afterwards, be that current state changes to data mode, otherwise allow its current state be in address state;
When current state is data mode, at first make the data line of lpc bus place high-impedance state, the enable signal of writing of first buffer zone puts 0, each LPC_CLK clock period is transmitted 4 bit data, through 2 LPC_CLK clock period, the data line of 8 data by lpc bus sent, and state machine is transferred to the TAR1 state afterwards, and promptly current state changes to the TAR1 state;
When current state is the TAR1 state, the enable signal of writing of first buffer zone puts 0, when the data line that determines lpc bus is 1111 and frame signal when being 1, wait for 4 LPC_CLK clock period,, begin 20 bit address that address state sends are judged as the 5th LPC_CLK during the clock period, when being 0XD0000, state machine is transferred to sync state, and promptly current state changes to sync state, otherwise allows its current state be in initial state;
When current state is sync state, 8 bit data that send during data mode write the data input pin of FIFO1, and the enable signal of writing of first buffer zone is put 1, and the data line of lpc bus puts 0000, state machine is transferred to the TAR2 state afterwards, and promptly current state changes to the TAR2 state;
When current state is the TAR2 state, the enable signal of writing of first buffer zone is put 0, the data line of lpc bus puts 1111, and state machine is transferred to the END state afterwards, and promptly current state changes to the END state;
When current state is the END state, the enable signal of writing of first buffer zone is put 0, the data line of lpc bus is put high-impedance state, and state machine is transferred to initial state afterwards, and promptly current state changes to initial state;
When other situations, the current state of state machine remains initial state.
For the USB-LPC protocol conversion module, this module is mainly according to the lpc bus standard, and in FPGA inside, through protocol conversion, the lpc bus reading of data is to terminal computer the data in second buffer zone.Various modes is arranged during the LPC reading of data, and what this design mainly utilized is Memory Target reading mode transmission data.Lpc bus has multiple different state when the transmission data, this module mainly realizes the conversion of different conditions with state machine, to realize the data read in second buffer zone to terminal computer.
Shown in Figure 4 and 5, behind electrification reset, state machine enters initial state, and promptly current state is an initial state;
When each LPC_CLK rising edge clock comes to begin the judgement to current state temporarily;
When current state is initial state, at first make the data line of lpc bus place high-impedance state, the enable signal of reading of second buffer zone puts 0, when the data line that determines lpc bus is 0000 and FRAME signal when being 0, state machine is transferred to the DIR state, be that current state changes to the DIR state, otherwise allow current state be in initial state;
When current state is the DIR state, the enable signal of reading of second buffer zone puts 0, and when the Senior Three position of the data line line that determines lpc bus is 010 and frame signal when being 1, state machine is transferred to address state, be that current state changes to address state, otherwise allow its current state be in initial state;
When current state is address state, at first make the data line line of lpc bus place high-impedance state, the enable signal of reading of second buffer zone puts 0, and each LPC_CLK clock period is transmitted 4 bit address, through 8 LPC_CLK clock period, the data line of 32 addresses by lpc bus transmitted, wherein high 12 ignore need not, low 20 effectively, state machine is transferred to the TAR1 state afterwards, be that current state changes to data mode, otherwise allow its current state be in address state;
When current state is the TAR1 state, the enable signal of reading of second buffer zone puts 0, when the bidirectional data line that determines lpc bus is 1111 and frame signal when being 1, wait for 1 LPC_CLK clock period, as the 2nd LPC_CLK during the clock period, begin 20 bit address that address state transmits are judged, when being 0XD0001 or when the 0XD0002, state machine is transferred to sync state and the data line of lpc bus is changed to 0101, be that current state changes to sync state and the data line of lpc bus is changed to 0101, otherwise allow its current state be in initial state;
When current state is sync state, operate as follows: when the address that determines the address state transmission is 0XD0001, preceding 2 LPC_CLK clock period, the enable signal of reading of second buffer zone puts 0, current state remains on sync state, the data line of lpc bus puts 0101, as the 3rd LPC_CLK during the clock period, the enable signal of reading of second buffer zone puts 1, the state machine current state remains on sync state, the data line of lpc bus is changed to 0101, the 4 LPC_CLK during the clock period, the data storage of the data output end of FIFO2 output in 8 data register, the enable signal of reading of second buffer zone puts 0, state machine is transferred to data mode, and promptly current state changes to data mode, and the data line of lpc bus is changed to 0000; When the address that determines the address state transmission is 0XD0002, at first the enable signal of reading of second buffer zone puts 0, preceding 3 LPC_CLK clock period, current state remains sync state, the data line signal of lpc bus is changed to 0101, the 4 LPC_CLK in the clock period, and state machine is transferred to data mode, be that current state is changed into data mode, the data line of lpc bus is changed to 0000; When the address that determines the address state transmission was other situations, the data line of lpc bus was changed to high-impedance state, and the enable signal of reading of second buffer zone puts 0, and state machine is transferred to initial state, and promptly current state is changed into initial state;
When current state is data mode, the enable signal of reading of second buffer zone puts 0, when the address that determines the address state transmission is 0XD0001, the 1st LPC_CLK clock period, low 4 bidirectional data lines that send lpc bus to that are stored in the data in 8 bit data register when the sync state, current state remains data mode simultaneously, the 2nd LPC_CLK clock period, high 4 data lines that send lpc bus to that are stored in the data in 8 bit data register when the sync state, state machine is transferred to the TAR2 state, and promptly current state is changed into the TAR2 state; When the address that determines the address state transmission is 0XD0002, the 1st LPC_CLK clock period, high 2 positions 11 of the data line of lpc bus, the empty marking signal assignment of FIFO2 is given bidirectional data line the 1st, the full scale will signal assignment of FIFO1 is given the 0th of data line of lpc bus, current state remains data mode simultaneously, the 2nd LPC_CLK clock period, the data line of lpc bus is changed to 1111, state machine is transferred to the TAR2 state, and promptly current state is changed into the TAR2 state; When the address that determines the address state transmission was other situations, state machine was transferred to initial state, and promptly current state is changed into initial state;
When current state was the TAR2 state, the enable signal of reading of second buffer zone put 0, and the bidirectional data line of lpc bus is changed to 1111, and state machine is transferred to the END state, and promptly current state is changed into the END state;
When current state is the END state, the enable signal of reading of second buffer zone is put 0, the data line of lpc bus is put high-impedance state, and state machine is transferred to initial state afterwards, and promptly current state changes to initial state;
When other situations, the current state of state machine remains initial state.
In force, first buffer zone, second buffer zone, CLKV module are mainly with utilizing Xilinx developing instrument ISE9.2 to generate IP CORE, wherein first buffer zone and second buffer zone are the FIFO of degree of depth 16K, utilize FPGA clock internal manager DCM to realize the CLKV module.First buffer zone is mainly realized the buffering of lpc bus write data, USB module read data.Lpc bus transmits data to first buffer zone by data input pin, the USB module is by data output end reading of data in first buffer zone, the enable signal of writing of first buffer zone links to each other with the lpc bus control end with clock signal, the enable signal of reading of first buffer zone links to each other with USB module controls end with clock signal, when first buffer zone is full, send FULL to indicate lpc bus, when first buffer empty, send EMPTY to indicate the USB module, when first buffer zone has 510 data empty again, send the PROG_EMPTY signal to the USB module.Second buffer zone is mainly realized the buffering of lpc bus read data, USB module write data.The USB module transmits data to second buffer zone by data input pin, lpc bus is by data output end reading of data in second buffer zone, the enable signal of reading of second buffer zone links to each other with the lpc bus control end with clock signal, the enable signal of writing of second buffer zone links to each other with the USB control end with clock signal, when second buffer zone is full, send FULL to indicate the USB module, when second buffer empty, send EMPTY to indicate lpc bus.
As shown in Figure 7, the USB module uses Cypress 68013A to change the controller of local bus as USB, and its is inner integrated enhancement mode 51 kernels can be done a lot of configurations to the related register in the usb communication, equally also can be used as standard 51 and call.Far Left is the USB transceiver, on transceiver the right is SIE (Serial Interface Engine), it also is in the communication of USB, the main unit of being responsible for, its inner integrated USB packing, give out a contract for a project, and packet receiving, the hardware circuit that unpacks, and stayed a large amount of registers, can allow 51 kernels dispose.SIE the right, and coupled be the configurable FIFO of 4KB, data enter FIFO from SIE, under the control of GPIF module or 51 kernels, outwards transmit in the mode of 8bit/16bit, just arrive Local bus, enter FPGA then.In the USB host-host protocol, our demand is: data volume want big and data transmission reliable, adopt the bulk transmission mode, it is to support wrong retransmission mechanism, in the configuration of FIFO, we have adopted 2 FIFO, a turnover, each 2Kbyte.
Be illustrated in figure 8 as the interface connection diagram of FPGA and USB module, and the physical interface definition, as shown in table 2 below:
| Signal name | Bit wide | Direction | Describe |
| ??RDY0 | ??1 | ??IN | The empty zone bit that FPGA sends, sky is read in expression |
| ??RDY1 | ??1 | ??IN | The full zone bit that FPGA sends, expression is write full |
| ??CTL0 | ??1 | ??OUT | The WEN# enable signal, FIFO's writes among the control FPGA |
| ??CTL1 | ??1 | ??OUT | The REN# enable signal, FIFO's reads among the control FPGA |
| ??CTL2 | ??1 | ??OUT | The OE# enable signal is chosen FIFO among the FPGA |
| ??USB_CLK | ??1 | ??OUT | USB is the synchronous clock of interface, 48MHz to FPGA |
| ??Data | ??8 | ??INOUT | Bi-directional data |
Table 2
The present invention describes by several specific embodiments, it will be appreciated by those skilled in the art that, without departing from the present invention, can also carry out various conversion and be equal to alternative the present invention.In addition, at particular condition or concrete condition, can make various modifications to the present invention, and not depart from the scope of the present invention.Therefore, the present invention is not limited to disclosed specific embodiment, and should comprise the whole embodiments that fall in the claim scope of the present invention.
Claims (12)
1, a kind of device that uses FPGA to realize the LPC-USB two-way communication comprises lpc bus and usb bus, it is characterized in that this device also comprises: field programmable logic device and USB module; The control of described field programmable logic device is finished by protocol conversion and the transmission of lpc bus to the LPC data of usb bus to usb data, and finishes by protocol conversion and the transmission of usb bus to the usb data of lpc bus to the LPC data; Described USB module is used to realize the exchanges data of described field programmable logic device and usb bus;
Described field programmable logic device comprises: LPC-USB protocol conversion module, USB-LPC protocol conversion module, first buffer zone and second buffer zone;
Wherein, the LPC-USB protocol conversion module is used to receive the LPC data that lpc bus sends, and it is carried out sending to first buffer zone after the protocol conversion;
First buffer zone is used for by the buffer memory of LPC data to usb data protocol conversion and transport process data;
Second buffer zone is used to receive the usb data that the USB module sends, and is used for by the buffer memory of usb data to conversion of LPC data protocol and transport process data;
The USB-LPC protocol conversion module is used to receive the usb data of second buffer zone output, and it is carried out sending lpc bus after the protocol conversion.
2, use FPGA according to claim 1 realizes the device of LPC-USB two-way communication, it is characterized in that described first buffer zone and second buffer zone all are the fifo buffers that can carry out 16K byte reading and writing data.
3, use FPGA according to claim 2 realizes the device of LPC-USB two-way communication, it is characterized in that the enable signal of writing of described first buffer zone links to each other, reads that enable signal links to each other with the control end of described USB module, clock signal links to each other with the control end of described lpc bus with the USB module respectively with the control end of described lpc bus.
4, use FPGA according to claim 2 realizes the device of LPC-USB two-way communication, it is characterized in that the enable signal of reading of described second buffer zone links to each other, writes that enable signal links to each other with the control end of described USB module, clock signal links to each other with the control end of described lpc bus with the USB module respectively with the control end of described lpc bus.
5, use FPGA according to claim 2 realizes the device of LPC-USB two-way communication, it is characterized in that, described field programmable logic device also comprises: the clock control administration module, it comprises input end, first output terminal and second output terminal, wherein, input end links to each other with outside global clock pin, the clock same-phase of the output of first output terminal and input end, the clock antiphase of the output of second output terminal and input end.
6, a kind ofly realize it is characterized in that the LPC-USB data transfer device of the device of LPC-USB two-way communication, may further comprise the steps at the arbitrary described use FPGA of claim 1～5:
S11, current state is set is initial state;
S12, when the Senior Three position of described lpc bus is 011 and frame signal when being 1, it is address state that current state is set;
S13, reception 32 bit address, it is data mode that current state is set;
S14, reception 8 bit data, it is the TAR1 state that current state is set;
S15, when described lpc bus is 1111 and frame signal when being 1, judge whether low 20 of described 32 bit address are 0XD0000, if it is sync state that current state is set, otherwise, enter step S1;
S16, described 8 bit data are sent to first buffer zone;
S17, end LPC-USB data-switching.
7, method according to claim 6 is characterized in that, also comprises between step S11 and S12: it is high-impedance state that described lpc bus is set, and the enable signal of writing of first buffer zone puts 0;
8, method according to claim 6 is characterized in that, in step S13, receives 4 bit address in each LPC_CLK clock period, through 8 LPC_CLK clock period, receives described 32 bit address; In step S14, receive 4 bit data in each LPC_CLK clock period, through 2 LPC_CLK clock period, receive described 8 bit data.
9, method according to claim 6 is characterized in that, in step S16, before sending described 8 bit data, comprises that also the enable signal of writing that first buffer zone is set is 1, and described lpc bus is set is 0000.
10, a kind ofly realize it is characterized in that the USB-LPC data transfer device of the device of LPC-USB two-way communication, may further comprise the steps at the arbitrary described use FPGA of claim 1～5:
S21, current state is set is initial state;
S22, when the Senior Three position of described lpc bus is 010 and frame signal when being 1, it is address state that current state is set;
S23, reception 32 bit address, it is the TAR1 state that current state is set;
S24, when described lpc bus is 1111 and frame signal when being 1, judge whether low 20 of described 32 bit address are 0XD0001 or 0XD0002, if it is sync state that current state is set, and described lpc bus is set is 0101, otherwise, enter step S21;
S25, judge whether low 20 of described 32 bit address are 0XD0001, if enter step S26; Otherwise, enter step S27;
S26, the data of described second buffer zone output are sent in 8 the data register;
S27, current state is set is data mode, be provided with described lpc bus be 0000 and the enable signal of reading that described second buffer zone is set be 0;
S28, judge whether low 20 of described 32 bit address are 0XD0001, if enter step S29; Otherwise, enter step S210;
S29, the data that will be stored in described 8 data register send to described USB-LPC protocol conversion module;
S210, the 1st LPC_CLK clock period, high 2 positions 11 of described lpc bus, the empty marking signal assignment of described second buffer zone is given described lpc bus the 1st, the full scale will signal assignment of described first buffer zone is given described lpc bus the 0th, the 2nd LPC_CLK clock period, it is 1111 that described lpc bus is set;
S211, end USB-LPC data-switching.
11, method according to claim 11 is characterized in that, also comprises between described step S21 and S22: it is high-impedance state that described lpc bus is set, and the enable signal of reading of second buffer zone puts 0; In step S23, receive 4 bit address in each LPC_CLK clock period, through 8 LPC_CLK clock period, receive described 32 bit address.
12, method according to claim 11, it is characterized in that, in step S29, the 1st LPC_CLK clock period, low 4 of being stored in data in described 8 data register are sent to described USB-LPC protocol conversion module, the 2nd LPC_CLK clock period, high 4 of being stored in data in described 8 data register are sent to described USB-LPC protocol conversion module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101424833A CN101655825B (en) | 2008-08-19 | 2008-08-19 | A device using FPGA to realize LPC-USB bidirectional communication and LPC-USB and USB-LPC data conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101424833A CN101655825B (en) | 2008-08-19 | 2008-08-19 | A device using FPGA to realize LPC-USB bidirectional communication and LPC-USB and USB-LPC data conversion method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101655825A true CN101655825A (en) | 2010-02-24 |
| CN101655825B CN101655825B (en) | 2011-01-19 |
Family
ID=41710119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101424833A Active CN101655825B (en) | 2008-08-19 | 2008-08-19 | A device using FPGA to realize LPC-USB bidirectional communication and LPC-USB and USB-LPC data conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101655825B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169470A (en) * | 2010-02-27 | 2011-08-31 | 比亚迪股份有限公司 | Conversion bridge from advanced high performance bus (AHB) to basic virtual component interface (BVCI) |
| CN102207920A (en) * | 2010-03-30 | 2011-10-05 | 比亚迪股份有限公司 | Conversion bridge for conversion from BVCI (basic virtual component interface) bus to AHB (advanced high performance bus) |
| CN104052456B (en) * | 2014-06-23 | 2017-02-15 | 青岛海信电器股份有限公司 | Circuit for two-way communication |
| CN106598901A (en) * | 2016-12-08 | 2017-04-26 | 邦彦技术股份有限公司 | System and chip for converting Local Bus into USB based on FPGA |
| CN113868179A (en) * | 2021-09-10 | 2021-12-31 | 中国航空工业集团公司西安航空计算技术研究所 | LPC _ DPRam communication device and data conversion method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6370603B1 (en) * | 1997-12-31 | 2002-04-09 | Kawasaki Microelectronics, Inc. | Configurable universal serial bus (USB) controller implemented on a single integrated circuit (IC) chip with media access control (MAC) |
| US6742076B2 (en) * | 2000-01-03 | 2004-05-25 | Transdimension, Inc. | USB host controller for systems employing batched data transfer |
| US20030229738A1 (en) * | 2002-06-05 | 2003-12-11 | Dactron | Controller interface |
| JP2004110409A (en) * | 2002-09-18 | 2004-04-08 | Hirotekku Kk | Bus monitoring device |
| KR100647370B1 (en) * | 2004-04-20 | 2006-11-23 | 주식회사 하이닉스반도체 | Multiprotocol Serial Interface System |
| CN100388255C (en) * | 2004-10-10 | 2008-05-14 | 中兴通讯股份有限公司 | An interface conversion module and method for configuring FPGA |
-
2008
- 2008-08-19 CN CN2008101424833A patent/CN101655825B/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169470A (en) * | 2010-02-27 | 2011-08-31 | 比亚迪股份有限公司 | Conversion bridge from advanced high performance bus (AHB) to basic virtual component interface (BVCI) |
| CN102169470B (en) * | 2010-02-27 | 2014-01-29 | 比亚迪股份有限公司 | A conversion bridge from AHB bus to BVCI bus |
| CN102207920A (en) * | 2010-03-30 | 2011-10-05 | 比亚迪股份有限公司 | Conversion bridge for conversion from BVCI (basic virtual component interface) bus to AHB (advanced high performance bus) |
| CN102207920B (en) * | 2010-03-30 | 2013-12-04 | 比亚迪股份有限公司 | Conversion bridge for conversion from BVCI (basic virtual component interface) bus to AHB (advanced high performance bus) |
| CN104052456B (en) * | 2014-06-23 | 2017-02-15 | 青岛海信电器股份有限公司 | Circuit for two-way communication |
| US9846671B2 (en) | 2014-06-23 | 2017-12-19 | Qingdao Hisense Electronics Co., Ltd. | Bidirectional data transmission system |
| CN106598901A (en) * | 2016-12-08 | 2017-04-26 | 邦彦技术股份有限公司 | System and chip for converting Local Bus into USB based on FPGA |
| CN113868179A (en) * | 2021-09-10 | 2021-12-31 | 中国航空工业集团公司西安航空计算技术研究所 | LPC _ DPRam communication device and data conversion method |
| CN113868179B (en) * | 2021-09-10 | 2024-04-02 | 中国航空工业集团公司西安航空计算技术研究所 | Communication device of LPC-DPRam and data conversion method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101655825B (en) | 2011-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101477504B (en) | System and method for transmission of data | |
| CN101208678B (en) | Software layer for communication between RS-232 to I2C translation IC and a host | |
| CN109411007B (en) | Universal flash memory test system based on FPGA | |
| CN101087235A (en) | A FPGA-based multi-functional communication interface conversion device and method | |
| CN106815157A (en) | A kind of data acquisition module and data collecting system | |
| JP2006500672A (en) | Bus connection system | |
| CN102023956A (en) | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method | |
| CN203812236U (en) | Data exchange system based on processor and field programmable gate array | |
| CN101655825B (en) | A device using FPGA to realize LPC-USB bidirectional communication and LPC-USB and USB-LPC data conversion method | |
| CN101436171B (en) | Modular communication control system | |
| EP1535169B1 (en) | Improved inter-processor communication system for communication between processors | |
| CN112395230A (en) | UART interface extension circuit based on programmable logic device | |
| WO2009000794A1 (en) | Data modification module in a microcontroller | |
| CN101221550A (en) | Method and chip for serial communication | |
| CN101452430A (en) | Communication method between multi-processors and communication device comprising multi-processors | |
| CN101004674A (en) | Processor architecture | |
| CN201336032Y (en) | Software simulation serial data transmission device | |
| CN107436857A (en) | A kind of Enhanced SPI device and the method carried out data transmission using the device | |
| CN204390227U (en) | Computing equipment expanding unit and extendible computing system | |
| CN101534259B (en) | An asynchronous communication controller and its control method | |
| CN113609067B (en) | System for realizing 32-channel RS485 interface card | |
| CN117435538A (en) | Bridging system for converting PCIe (peripheral component interconnect express) into SRIO (serial peripheral component interconnect express) | |
| CN103488601A (en) | Clock delay method, clock delay system, clock delay equipment, data access method, data access system and data access equipment | |
| CN100462952C (en) | Universal Serial Bus controller with configurable interface | |
| CN105262659A (en) | HDLC protocol controller based on FPGA chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Xi'an EVOC Intelligent Technology Co.,Ltd. Assignor: EVOC INTELLIGENT TECHNOLOGY Co.,Ltd. Contract record no.: 2012610000049 Denomination of invention: Device for achieving LPC-USB two-way communication by using FPGA and data conversion method of LPC-US and USB-LPC Granted publication date: 20110119 License type: Exclusive License Open date: 20100224 Record date: 20120425 |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20230725 Address after: 518000 B2, 20/F, Yanxiang Science and Technology Building, No. 31, High-tech Fourth Road, Maling Community, Yuehai Street, Nanshan District, Shenzhen, Guangdong Province Patentee after: Shenzhen Jiuniuyimao Intelligent Internet of Things Technology Co.,Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high in the four EVOC Technology Building No. 31 Patentee before: EVOC INTELLIGENT TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right |