CN101644744A - Adjustment comparison method of test vectors - Google Patents
Adjustment comparison method of test vectors Download PDFInfo
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- CN101644744A CN101644744A CN200910060234A CN200910060234A CN101644744A CN 101644744 A CN101644744 A CN 101644744A CN 200910060234 A CN200910060234 A CN 200910060234A CN 200910060234 A CN200910060234 A CN 200910060234A CN 101644744 A CN101644744 A CN 101644744A
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Abstract
The invention discloses an adjustment comparison method of test vectors. In the method, the test vectors of data in a memory are input to a system to be tested, the system to be tested outputs the test vectors of returning data, the test vectors of standard data is judged to whether contain ignored data in the process of comparing the test vectors of the standard data and the test vectors of the returning data, when the test vectors of standard data contain the ignored data, the ignored data is decoded and the position of the ignored data is shielded, the test vectors of shielding data is generated, the same position of the test vectors of the returning data is also shielded at the same time, and then the test vectors of the shielding data and the test vectors of the returning data are compared to determine whether the test vectors of the shielding data and the test vectors of the returning data are the same; and when the test vectors of standard data does not contain the ignored data,the test vectors of the standard data is directly compared with the test vectors of the returning data. The method adopts hardware for real-time comparison, the returning data does not need to be placed in the memory, therefore, the memory space can be greatly saved. Because the method is the hardware real-time comparison method, the ignored data is compared after specific treatment, and the testtime is shorter.
Description
Technical field
Present technique is mainly used in the adjusting control methods of logic chip IC field tests, particularly a kind of test vector.
Background technology
As everyone knows, the key of raising testing efficiency is to shorten the test duration.The correctness that ensures the chip logic function just must improve fault coverage, must create test vector and tests in order to reach this purpose.Because the capacity of test vector causes the test duration long greatly, is the main cause that current testing efficiency is low, cost is high.
The IC functional test is used to guarantee that measured device can correctly finish expectation function.Must set up test vector earlier in order to reach this purpose, just can detect the mistake of generation survey device.Test vector is also referred to as figure or truth table----to be made up of the input and output state, has following three kinds of states:
1, logical zero, input and output 0 state;
2, logical one, input and output 1 state;
3, ignore (X), input or output do not need the comparison state.
Test vector is divided into:
1, input data test vector----need be sent into the data for the treatment of examining system;
2, the data of normal data test vector----expectation IC backflow;
3, the data of backflow data test vector----IC finite reflux.
As shown in Figure 1, be that backflow data test vector is all deposited in the storer in existing test platform, from storer, take out backflow data test vector by the backstage again and compare with the normal data test vector.
This is well-known to data volume greatly in the test of scan chain, and data volume directly influences the test duration greatly.Be that the backflow data are placed on earlier in the storer in existing method of testing, handle by daemon software again, so not only the storage space that test speed is slow but also needs are bigger.
Simultaneously, the processing speed of daemon software is far away less than the speed of hardware handles.And prior art is to adopt daemon software that the information of ignoring in the normal data test vector is extracted to the processing of ignoring data bit, when detecting to control after being to ignore data it is ignored, and makes it not participate in comparison.Such disposal route make normal data test vector and backflow data test vector relatively want a slow joint, and this part time mostly consume daemon software to ignoring the processing of data bit.Increased the time of test so again greatly.
Summary of the invention
The present invention provides a kind of adjusting control methods of test vector for addressing the above problem, and the backflow data do not need to put back to storer, ignores data bit and participates in relatively can save storage space greatly, and the test duration being shorter.
Technical scheme of the present invention is as follows:
A kind of adjusting control methods of test vector, data test vector in the storer inputed to treat examining system, treat examining system output backflow data test vector, in the process that normal data test vector in storer and backflow data test vector compare, it is characterized in that: at first whether criterion data test vector contains and ignores data, when containing when ignoring data, decode to ignoring data, and the position that will ignore data shields, generate the shadow data test vector, simultaneously the identical position of backflow data test vector is also shielded, then shadow data test vector and backflow data test vector are compared judge whether identical; When not containing when ignoring data, normal data test vector and backflow data test vector directly compare judge whether identical.
Bit wides such as described shadow data test vector and normal data test vector.
Realize the adjusting contrast circuit of said method, it is characterized in that:
Be provided with one and ignore the data bit adjustment module, be used for judging and ignore data, decode, and will ignore the position shielding of data, generate the shadow data test vector ignoring data;
Be provided with a comparison module, be used for the normal data test vector and backflow data test vector compares;
The described data bit adjustment module of ignoring is judged the normal data test vector, when containing when ignoring data, decode to ignoring data, and the position that will ignore data shields, generate the shadow data test vector, judge whether identical to the shadow data test vector with backflow data test vector by comparison module then; When not containing when ignoring data, directly by comparison module to normal data test vector and backflow data test vector compare judge whether identical.
The described data bit adjustment module of ignoring comprises normal data test vector data channel.
The described data bit adjustment module of ignoring is a logical circuit, is in state of activation forever.
When the position of ignoring data of normal data test vector was shielded, this position was set to logical zero, and other positions are set to logical one; Simultaneously, the identical position of backflow data test vector also is set to logical zero, and other positions are set to logical one.
Described comparison module is formed with door by two, shadow data test vector and normal data test vector, backflow data test vector input to two and door respectively, by xor operation, draw comparative result then, if the identical surveys output 0 of two data differently then is output as 1.
Beneficial effect of the present invention is as follows:
This method adopts hardware to compare in real time, and the backflow data do not need to put back to storer, thereby can save storage space greatly; Owing to be the hardware method of contrast in real time, ignore data bit relatively through participation after the special processing, the test duration is shorter like this.
Description of drawings
Fig. 1 is traditional test vector control methods synoptic diagram
Fig. 2 is a contrast synoptic diagram of the present invention
Fig. 3 is the data bit adjustment module realization flow figure that ignores of the present invention
Fig. 4 is the decoding processing synoptic diagram of the present invention to normal data test vector ignore bit
Fig. 5 is the data bit treatment scheme synoptic diagram of ignoring of the present invention
Embodiment
Shown in Fig. 2-3, a kind of adjusting control methods of test vector, data test vector in the storer inputed to treat examining system, treat examining system output backflow data test vector, in the process that normal data test vector in storer and backflow data test vector compare, at first whether criterion data test vector contains and ignores data, when containing when ignoring data, decode to ignoring data, and the position that will ignore data shields, generate the shadow data test vector, simultaneously the identical position of backflow data test vector also shielded, then shadow data test vector and backflow data test vector are compared judge whether identical; When not containing when ignoring data, normal data test vector and backflow data test vector directly compare judge whether identical.
Bit wides such as described shadow data test vector and normal data test vector.
As shown in Figure 2, frame of broken lines is for regulating main functional modules, and arrow 1 is a normal data test vector data path.
Realize the adjusting contrast circuit of said method:
Be provided with one and ignore the data bit adjustment module, be used for judging and ignore data, decode, and will ignore the position shielding of data, generate the shadow data test vector ignoring data;
Be provided with a comparison module, be used for the normal data test vector and backflow data test vector compares;
The described data bit adjustment module of ignoring is judged the normal data test vector, when containing when ignoring data, decode to ignoring data, and the position that will ignore data shields, generate the shadow data test vector, judge whether identical to the shadow data test vector with backflow data test vector by comparison module then; When not containing when ignoring data, directly by comparison module to normal data test vector and backflow data test vector compare judge whether identical.
The described data bit adjustment module of ignoring comprises normal data test vector data channel.
The described data bit adjustment module of ignoring is a logical circuit, is in state of activation forever.
When the position of ignoring data of normal data test vector was shielded, this position was set to logical zero, and other positions are set to logical one; Simultaneously, the identical position of backflow data test vector also is set to logical zero, and other positions are set to logical one.
Described comparison module is formed with door by two, shadow data test vector and normal data test vector, backflow data test vector input to two and door respectively, by xor operation, draw comparative result then, if the identical surveys output 0 of two data differently then is output as 1.
The cooperation of ignoring data bit adjustment module and two logical circuits of comparison module has been arranged, backflow data test vector does not compare by daemon software after not needing to put back to storer again, can directly compare in real time, be about to normal data test vector and backflow data test vector and carry out xor operation.Whole process is all finished by logical circuit, so and backflow data test vector do not need to put and can storer ignore data bit and need not judge test duration and the storage space of saving greatly by daemon software.
As shown in Figure 4, the concrete comparison example of this adjusting control methods, the normal data test vector is 32 bit widths, ignore and decode after the data bit adjustment module is read in, when the position of two X in the normal data test vector comprises when ignoring data, this logical circuit will produce the data with bit wides (32 bit width) such as normal data test vectors, and the position of two X is changed to 0.
As shown in Figure 5, left data is the normal data test vector, and intermediate data is the shadow data test vector, and right data is a backflow data test vector.To ignore shadow data test vector that the data bit adjustment module produces by two with door realize respectively with normal data test vector and backflow data test vectorial with, the data bit of ignoring of normal data test vector and backflow data test vector is set to 0.
Claims (7)
1, a kind of adjusting control methods of test vector, data test vector in the storer inputed to treat examining system, treat examining system output backflow data test vector, in the process that normal data test vector in storer and backflow data test vector compare, it is characterized in that: at first whether criterion data test vector contains and ignores data, when containing when ignoring data, decode to ignoring data, and the position that will ignore data shields, generate the shadow data test vector, simultaneously the identical position of backflow data test vector is also shielded, then shadow data test vector and backflow data test vector are compared judge whether identical; When not containing when ignoring data, normal data test vector and backflow data test vector directly compare judge whether identical.
2, according to the adjusting control methods of the described a kind of test vector of claim 1, it is characterized in that: bit wides such as described shadow data test vector and normal data test vector.
3, realize the adjusting contrast circuit of the adjusting control methods of the described a kind of test vector of claim 1, it is characterized in that:
Be provided with one and ignore the data bit adjustment module, be used for judging and ignore data, decode, and will ignore the position shielding of data, generate the shadow data test vector ignoring data;
Be provided with a comparison module, be used for the normal data test vector and backflow data test vector compares;
The described data bit adjustment module of ignoring is judged the normal data test vector, when containing when ignoring data, decode to ignoring data, and the position that will ignore data shields, generate the shadow data test vector, judge whether identical to the shadow data test vector with backflow data test vector by comparison module then; When not containing when ignoring data, directly by comparison module to normal data test vector and backflow data test vector compare judge whether identical.
4, adjusting contrast circuit according to claim 3 is characterized in that: the described data bit adjustment module of ignoring comprises normal data test vector data channel.
5, adjusting contrast circuit according to claim 3 is characterized in that: the described data bit adjustment module of ignoring is a logical circuit, is in state of activation forever.
6, adjusting contrast circuit according to claim 3 is characterized in that: when the position of ignoring data of normal data test vector was shielded, this position was set to logical zero, and other positions are set to logical one; Simultaneously, the identical position of backflow data test vector also is set to logical zero, and other positions are set to logical one.
7, adjusting contrast circuit according to claim 3, it is characterized in that: described comparison module is formed with door by two, shadow data test vector and normal data test vector, backflow data test vector input to two and door respectively, pass through xor operation then, draw comparative result, if the identical surveys output 0 of two data differently then is output as 1.
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| CN2009100602344A CN101644744B (en) | 2009-08-03 | 2009-08-03 | Adjustment comparison method of test vectors |
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| CN2009100602344A CN101644744B (en) | 2009-08-03 | 2009-08-03 | Adjustment comparison method of test vectors |
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| CN101644744B CN101644744B (en) | 2012-06-27 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102262205A (en) * | 2010-05-31 | 2011-11-30 | 无锡中星微电子有限公司 | Method and device for shielding test point of test vector source file |
| CN103344854A (en) * | 2013-06-24 | 2013-10-09 | 国家电网公司 | Automatic test system and method for logical function device |
| CN112363045A (en) * | 2020-10-30 | 2021-02-12 | 海光信息技术股份有限公司 | Chip scanning test method and device, processor chip and server |
| CN113203938A (en) * | 2021-04-15 | 2021-08-03 | 杭州加速科技有限公司 | Test vector storage method, compression method and equipment, and test method and equipment |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246971B1 (en) * | 1999-01-05 | 2001-06-12 | Lucent Technologies Inc. | Testing asynchronous circuits |
| CN100446129C (en) * | 2006-09-07 | 2008-12-24 | 华为技术有限公司 | Method and system for RAM fault testing |
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2009
- 2009-08-03 CN CN2009100602344A patent/CN101644744B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102262205A (en) * | 2010-05-31 | 2011-11-30 | 无锡中星微电子有限公司 | Method and device for shielding test point of test vector source file |
| CN102262205B (en) * | 2010-05-31 | 2015-08-26 | 无锡中星微电子有限公司 | A kind of screen method of test point of test vector source file and shield assembly |
| CN103344854A (en) * | 2013-06-24 | 2013-10-09 | 国家电网公司 | Automatic test system and method for logical function device |
| CN112363045A (en) * | 2020-10-30 | 2021-02-12 | 海光信息技术股份有限公司 | Chip scanning test method and device, processor chip and server |
| CN113203938A (en) * | 2021-04-15 | 2021-08-03 | 杭州加速科技有限公司 | Test vector storage method, compression method and equipment, and test method and equipment |
| CN113203938B (en) * | 2021-04-15 | 2022-08-19 | 杭州加速科技有限公司 | Test vector storage method, compression method and equipment, and test method and equipment |
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| CN101644744B (en) | 2012-06-27 |
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