CN101635292B - Contact pad for measuring electrical thickness of gate dielectric layer and measurement structure thereof - Google Patents
Contact pad for measuring electrical thickness of gate dielectric layer and measurement structure thereof Download PDFInfo
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- CN101635292B CN101635292B CN2009100529705A CN200910052970A CN101635292B CN 101635292 B CN101635292 B CN 101635292B CN 2009100529705 A CN2009100529705 A CN 2009100529705A CN 200910052970 A CN200910052970 A CN 200910052970A CN 101635292 B CN101635292 B CN 101635292B
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- 238000005259 measurement Methods 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 178
- 239000002184 metal Substances 0.000 claims abstract description 178
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 238000000605 extraction Methods 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 208000005189 Embolism Diseases 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 204
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 239000011229 interlayer Substances 0.000 abstract description 6
- 239000000203 mixture Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Abstract
The invention provides a contact pad for measuring electrical thickness of gate dielectric layers and a measurement structure thereof, and belongs to the technical field of semiconductor manufacturing. In the provided contact pad, the area of an underlying pad metal layer in the prior art is reduced by composition to be not larger than the area of a gate electrode; and interlayer pad metal layers are replaced with interconnected metal layers with area smaller than that of a top pad metal layer, thus increasing capacitance gap of parasitic capacitance of the first pad metal layer, and being capable of greatly reducing the parasitic capacitance of the contact pad. Measurement accuracy is high when the measurement structure comprising the contact pad and a contact pad for extracting electrodes from a semiconductor substrate is used for measuring the electrical thickness of gate dielectric layers.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, be specifically related to a kind of contact pad and measurement structure thereof that is used to measure the electrical thickness of gate dielectric layer.
Background technology
For the MOS device, the thickness that is formed at the gate dielectric layer on the Semiconductor substrate is quite crucial, and it can determine the accuracy of the threshold voltage of MOS device.Therefore, need to measure the electrical thickness Tox of gate dielectric layer by WAT (WaferAcceptance Test, wafer is permitted Acceptance Tests).In the prior art, the basic principle of measuring the electrical thickness Tox of gate dielectric layer is: calculate the electrical thickness value Tox of equivalence then according to C meter by gate dielectric layer being carried out CV (capacitance-voltage characteristics curve) test.
CV for WAT test gate dielectric layer generally need draw first electrode and draw second electrode from the gate electrode of gate dielectric layer from substrate.Figure 1 shows that the measurement structure schematic diagram of the gate dielectric layer electrical thickness of prior art.Wherein, 110 is Semiconductor substrate, and 120 for being formed at the gate dielectric layer on the Semiconductor substrate, and 130 are the gate electrode on formation and the gate dielectric layer, form mos gate electric capacity between gate electrode 130 and the Semiconductor substrate 110.The contact pad that is used to measure the electrical thickness of gate dielectric layer 120 comprises and is used for from second contact pad (Pad) 150 of Semiconductor substrate extraction electrode and is used for from first contact pad 140 of the gate electrode extraction electrode of gate dielectric layer.Second contact pad 150 comprises top layer pad metal layer 156, ground floor pad metal layer 152, second layer pad metal layer 154.Wherein, metal plug 151 is used to connect ground floor pad metal layer 152 and Semiconductor substrate, and 111 is the high doping semiconductor area, can make like this between metal plug 151 and the semiconductor substrate region 111 and form ohmic contact; Metal plug 153 is used to connect ground floor pad metal layer 152 and second layer pad metal layer 154; Metal plug 155 is used to connect second layer pad metal layer 154 and top layer pad metal layer 156.Therefore, can produce parasitic capacitance hardly between second contact pad 150 and the Semiconductor substrate.For first contact pad 140, it comprises top layer pad metal layer 146, bottom pad metal layer 142, second layer pad metal layer 144 (also claiming the interlayer pad metal layer) equally.Be ILD (Inter Layer Dielectrics, interlayer dielectric) layer between bottom pad metal layer 142 and the gate electrode 130, metal plug 141 is used to connect bottom pad metal layer 142 and gate electrode 130; Be IMD (Interconnect Metal Dielectric, metal interlayer medium) layer between bottom pad metal layer 142 and the second layer pad metal layer 144, metal plug 143 is used to connect bottom pad metal layer 142 and second layer pad metal layer 144; Be the IMD layer between second layer pad metal layer 144 and the top layer pad metal layer 146, metal plug 145 is used to connect second layer pad metal layer 144 and top layer pad metal layer 146.Wherein top layer pad metal layer 146 is corresponding identical with the pattern of second layer pad metal layer 144.Owing to isolate by gate dielectric layer 120 between first contact pad 140 and the Semiconductor substrate 110, spacing distance between bottom pad metal layer 142 and the Semiconductor substrate 110 is D1, the bottom pad metal layer 142 of first contact pad will inevitably and Semiconductor substrate 110 between form the parasitic capacitance C1 of an equivalence.The electric capacity that forms between gate electrode 130 and the Semiconductor substrate 110 is the target testing capacitor C of CV test.In the CV test process of measuring the gate dielectric layer electrical thickness, parasitic capacitance C1 is in parallel with target testing capacitor C, thereby when utilizing structure measurement gate dielectric layer electrical thickness shown in Figure 1, the parasitic capacitance of its contact pad easily causes the measured value of gate dielectric layer electrical thickness inaccurate.
Summary of the invention
The technical problem to be solved in the present invention is, for the parasitic capacitance that reduces the contact pad structure to the influence of the measurement of gate dielectric layer electrical thickness, improve the measurement accuracy of gate dielectric layer electrical thickness, provide less relatively being used to of a kind of parasitic capacitance to measure the contact pad of gate dielectric layer electrical thickness.
For solving above technical problem, the contact pad that is used to measure the electrical thickness of gate dielectric layer provided by the invention comprises top layer pad metal layer and bottom pad metal layer, and the bottom pad metal layer is connected with gate electrode by first metal plug; The area of described bottom pad metal layer is equal to or less than the area of described gate electrode; Be connected with second metal plug by interconnecting metal layer between top layer pad metal layer and the bottom pad metal layer, the area of described interconnecting metal layer is less than the area of top layer pad metal layer.
According to contact pad provided by the invention, wherein, described Semiconductor substrate is a P type substrate.The area of described interconnecting metal layer is second metal plug two to three times at the sectional area that is parallel to the semiconductor substrate surface direction.Described first contact pad also comprises the interlevel dielectric layer between bottom pad metal layer and the Semiconductor substrate.Described first contact pad also comprises the metal interlamination medium layer between bottom pad metal layer and the top layer pad metal layer.Described gate electrode is polygate electrodes or metal gate electrode.Described interconnecting metal layer be two-layer or two-layer more than, the area of every layer of interconnecting metal layer equates.Described first metal plug is a tungsten plug.
The present invention further improves a kind of measurement structure that comprises the above contact pad, is used to measure the electrical thickness of gate dielectric layer, comprising:
Semiconductor substrate,
Be formed at the gate dielectric layer on the Semiconductor substrate,
Gate electrode on formation and the gate dielectric layer,
Be used for second contact pad from the Semiconductor substrate extraction electrode,
And first contact pad;
Described first contact pad comprises top layer pad metal layer and bottom pad metal layer, and the bottom pad metal layer is connected with gate electrode by first metal plug; The area of described bottom pad metal layer is equal to or less than the area of described gate electrode; Be connected with second metal plug by interconnecting metal layer between top layer pad metal layer and the bottom pad metal layer, the area of described interconnecting metal layer is less than the area of top layer pad metal layer.
According to measurement structure provided by the invention, wherein, described Semiconductor substrate is a P type substrate, forms the MOS active device in described Semiconductor substrate.Described second contact pad forms ohmic contact by the highly doped p type island region territory of metal plug and Semiconductor substrate.
Technique effect of the present invention is, reduce the area of bottom pad metal layer of the prior art by composition, make it be less than or equal to the area of gate electrode, and replace the interlayer pad metal layer less than the interconnecting metal layer of top layer pad metal layer, thereby increase the electric capacity spacing of the parasitic capacitance of first pad metal layer with area.Therefore, the parasitic capacitance that is used to draw the contact pad of gate electrode can reduce greatly.Use comprises the contact pad of this invention and is used for when the measurement structure of the contact pad of Semiconductor substrate extraction electrode is measured the electrical thickness of gate dielectric layer the measurement accuracy height.
Description of drawings
Fig. 1 is the measurement structure schematic diagram of the gate dielectric layer electrical thickness of prior art;
Fig. 2 is the measurement structure schematic diagram of gate dielectric layer electrical thickness provided by the invention;
Fig. 3 is the vertical view of first contact pad.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Figure 2 shows that the measurement structure schematic diagram of gate dielectric layer electrical thickness provided by the invention, comprise contact pad 240 provided by the invention in the figure simultaneously.As shown in Figure 2, in this embodiment, this measurement structure is used to measure the electrical thickness of the gate dielectric layer 220 that forms on the P type semiconductor substrate, and measurement structure comprises Semiconductor substrate 210, gate dielectric layer 220, gate electrode 230, first contact pad 240, second contact pad 250.Composition forms gate dielectric layer 220 on the P type semiconductor substrate 210, and alignment grid dielectric layer 220 compositions form corresponding gate electrode 230, and gate electrode 230 can be highly doped polysilicon or metal electrode.The pattern of gate dielectric layer 220 and area thereof are not limited by the present invention, in this embodiment, gate dielectric layer 220 is for being used to form the gate dielectric layer of high-pressure MOS component, its thickness is 90 nanometers, the area of gate dielectric layer 220 is 7000 square microns (100 microns * 70 microns), and the thickness and the area of concrete gate dielectric layer are not limited by the present invention; Because main flow technology all is to form the gate dielectric layer of metal-oxide-semiconductor on the P type semiconductor substrate, so is example with the P type semiconductor substrate also among this embodiment.
Continue as shown in Figure 2, region doping forms highly doped p type island region territory 211, the second contact pads 250 and draws from highly doped p type island region territory 211 on Semiconductor substrate 210.Second contact pad 250 comprises top layer pad metal layer 256, ground floor pad metal layer 252, second layer pad metal layer 254 and metal plug 251,253,255.Wherein, it is highly doped p type island region territory with Semiconductor substrate 210,211 that metal plug 251 is used to connect ground floor pad metal layer 252, can make like this between metal plug 251 and the highly doped p type island region territory 211 and form ohmic contact; Metal plug 253 is used to connect ground floor pad metal layer 252 and second layer pad metal layer 254; Metal plug 255 is used to connect second layer pad metal layer 254 and top layer pad metal layer 256.Therefore, can produce parasitic capacitance hardly between second contact pad 250 and the Semiconductor substrate.
Continue as shown in Figure 2, first contact pad 240 is formed on the gate electrode 230.First contact pad 240 comprises top layer pad metal layer 246, bottom pad metal layer 242, interconnecting metal layer 244 and metal plug 241,243,245.With the backend interconnect similar, be the ILD layer between bottom pad metal layer 242 and the Semiconductor substrate 210, metal plug 241 is used to connect gate electrode 230 and bottom pad metal layer 242, the concrete quantity of metal plug 241 is not limited by the present invention, be three in this embodiment, metal plug 241 can be tungsten plug.The area of bottom pad metal layer 242 is less than or equal to the area of gate electrode 230, and in this embodiment, on 242 corresponding formation of bottom pad metal layer and the gate electrode 230, bottom pad metal layer 242 all equates with the pattern and the area of gate electrode 230.Interconnecting metal layer 244 is different from the second layer pad metal layer 144 among prior art Fig. 1,244 area is less than the area of top layer pad metal layer 246, metal plug 243 is used to connect interconnecting metal layer 244 and bottom pad metal layer 242, and metal plug 245 is used to connect interconnecting metal layer 244 and top layer pad metal layer 246; Except that interconnecting metal layer and metal plug, all fill the IMD layer between bottom pad metal layer 242 and the top layer pad metal layer 246.In this embodiment, have only a metal plug 245 and metal plug 243, metal plug can 245,243 can be tungsten plug or copper embolism; The area of interconnecting metal layer 244 be metal plug maximum secting area (sectional area that is parallel to the semiconductor substrate surface direction) 2-3 doubly, generally speaking, the sectional area scope of metal plug is about the hundreds of square nanometers, and top layer pad metal layer 246 is owing to need the outside probe of overlap joint, its size range is in hundreds of micron number magnitude, in this embodiment, the area of top layer pad metal layer 246 is 6300 square microns (70 microns * 90 microns).As from the foregoing, in this embodiment, the area of metal plug 244 is far smaller than the area of top layer pad metal layer 246.
For further specifying the area relationship between top layer pad metal layer in the structure shown in Figure 2, bottom pad metal layer, the interconnecting metal layer, provide the vertical view of first contact pad shown in Figure 3.Described " area " all is meant at the area that is parallel to the semiconductor substrate surface direction.As shown in Figure 3, the area of bottom pad metal layer 242 equates with the area of gate electrode, and the area of interconnecting metal layer 244 is greater than the area of metal plug 243 but less than the area of top layer pad metal layer 246.
When carrying out the gate dielectric layer electricity thickness measuring, take the CV curve that probe can be tested gate dielectric layer 220 on the top layer pad metal layer 246 and 256 respectively, thereby calculate gate dielectric layer 220 electrical thickness values with structure shown in Figure 2.By the above as can be known, first contact pad 240 in the described structure of Fig. 2 is compared first contact pad 140 of prior art shown in Figure 1, its bottom pad metal layer area reduces, replaces second pad metal layer with the less interconnecting metal layer of area, thereby make the electric capacity spacing of the parasitic capacitance of first contact pad become D2 shown in Figure 2 by D1, wherein D2 is the thickness sum of the thickness and the IMD layer of ILD layer.According to CALCULATION OF CAPACITANCE as can be known, the size of electric capacity is inversely proportional to the electric capacity space D, and therefore, the parasitic capacitance of first contact pad 240 of structure shown in Figure 2 will reduce greatly.When adopting the measurement structure of first contact pad shown in Figure 2 and second contact pad to measure the electrical thickness of gate dielectric layer, measurement accuracy increases greatly.
Need further be pointed out that, only provided one deck interconnecting metal 244 in embodiment illustrated in fig. 2, interconnecting metal layer also can be for more than two-layer or two-layer, but the area of every layer of interconnecting metal layer is all less than the top layer pad metal layer, the area of every layer of interconnecting metal layer equates, can connect by metal plug is corresponding each other.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (12)
1. contact pad is used to measure the electrical thickness of the gate dielectric layer that forms on the Semiconductor substrate, comprises top layer pad metal layer and bottom pad metal layer, and the bottom pad metal layer is connected with gate electrode by first metal plug; It is characterized in that the area of described bottom pad metal layer is equal to or less than the area of described gate electrode; Be connected with second metal plug by interconnecting metal layer between top layer pad metal layer and the bottom pad metal layer, the area of described interconnecting metal layer is less than the area of top layer pad metal layer.
2. contact pad according to claim 1 is characterized in that, described Semiconductor substrate is a P type substrate.
3. contact pad according to claim 1 is characterized in that, the area of described interconnecting metal layer is second metal plug two to three times at the sectional area that is parallel to the semiconductor substrate surface direction.
4. contact pad according to claim 1 is characterized in that described contact pad also comprises the interlevel dielectric layer between bottom pad metal layer and the Semiconductor substrate.
5. contact pad according to claim 1 is characterized in that, described contact pad also comprises the metal interlamination medium layer between bottom pad metal layer and the top layer pad metal layer.
6. contact pad according to claim 1 is characterized in that, described gate electrode is polygate electrodes or metal gate electrode.
7. contact pad according to claim 1 is characterized in that, described interconnecting metal layer be two-layer or two-layer more than, the area of every layer of interconnecting metal layer equates.
8. contact pad according to claim 1 is characterized in that, described first metal plug is a tungsten plug.
9. contact pad according to claim 1 is characterized in that, described second metal plug is tungsten plug or copper embolism.
10. measurement structure is used to measure the electrical thickness of gate dielectric layer, comprising:
Semiconductor substrate,
Be formed at the gate dielectric layer on the Semiconductor substrate,
Gate electrode on formation and the gate dielectric layer,
Be used for second contact pad from the Semiconductor substrate extraction electrode,
And first contact pad;
Described first contact pad comprises top layer pad metal layer and bottom pad metal layer, and the bottom pad metal layer is connected with gate electrode by first metal plug; It is characterized in that the area of described bottom pad metal layer is equal to or less than the area of described gate electrode; Be connected with second metal plug by interconnecting metal layer between top layer pad metal layer and the bottom pad metal layer, the area of described interconnecting metal layer is less than the area of top layer pad metal layer.
11. measurement structure according to claim 10 is characterized in that, described Semiconductor substrate is a P type substrate, forms the MOS active device in described Semiconductor substrate.
12. measurement structure according to claim 10 is characterized in that, described second contact pad forms ohmic contact by the highly doped p type island region territory of metal plug and Semiconductor substrate.
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| CN102854398B (en) * | 2012-08-23 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | The measuring method of parasitic capacitance and the computational methods of gate dielectric layer thickness |
| US8890339B1 (en) * | 2013-04-30 | 2014-11-18 | Freescale Semiconductor, Inc. | Self-defining, low capacitance wire bond pad |
| CN104344981B (en) * | 2013-08-05 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of TEM sample |
| CN112885728B (en) * | 2019-11-29 | 2025-07-04 | 长鑫存储技术有限公司 | Semiconductor test structures |
| CN110931463B (en) * | 2019-12-06 | 2021-02-19 | 长江存储科技有限责任公司 | Semiconductor device test structure and manufacturing method thereof |
| CN114664797B (en) * | 2022-03-24 | 2024-03-12 | 苏州英嘉通半导体有限公司 | Passivation layer measuring structure and measuring method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140509 |
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Effective date of registration: 20140509 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |