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CN101626359A - Frequency-domain synchronous circuit structure applicable to CMMB and DVB-H - Google Patents

Frequency-domain synchronous circuit structure applicable to CMMB and DVB-H Download PDF

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CN101626359A
CN101626359A CN200910056140A CN200910056140A CN101626359A CN 101626359 A CN101626359 A CN 101626359A CN 200910056140 A CN200910056140 A CN 200910056140A CN 200910056140 A CN200910056140 A CN 200910056140A CN 101626359 A CN101626359 A CN 101626359A
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CN101626359B (en
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邵楠
李斯梦
陈赟
曾晓洋
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Fudan University
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Abstract

本发明属于无线数字通信技术领域,具体为一种能够同时支持中国移动多媒体标准CMMB及欧洲移动多媒体标准DVB-H的频域同步电路结构。主要包括整数倍载波频偏估计模块,解扰码模块,残余载波频偏及采样频偏估计模块,控制模块等部分。整数倍载波频偏估计模块,支持CMMB和DVB-H两种标准的整数倍载波频偏估计;解扰码模块,应用于CMMB模式下扰码模式识别及解扰码的运算;残余载波频偏及采样频偏估计模块,支持两种标准的残余载波频偏及采样频偏估计。本发明根据两种标准频域结构的相似性,提出一种结构以最低的硬件代价实现最大程度的复用,从而以一套硬件结构支持两种标准的频域同步。

The invention belongs to the technical field of wireless digital communication, and specifically relates to a frequency domain synchronous circuit structure capable of simultaneously supporting the Chinese mobile multimedia standard CMMB and the European mobile multimedia standard DVB-H. It mainly includes an integer multiple carrier frequency offset estimation module, a descrambling code module, a residual carrier frequency offset and sampling frequency offset estimation module, a control module and other parts. Integer multiple carrier frequency offset estimation module, supports integer multiple carrier frequency offset estimation of CMMB and DVB-H two standards; descrambling code module, applied to scrambling code pattern identification and descrambling code operation in CMMB mode; residual carrier frequency offset And the sampling frequency offset estimation module supports two standard residual carrier frequency offset and sampling frequency offset estimation. According to the similarity of the frequency domain structures of the two standards, the present invention proposes a structure to realize maximum multiplexing at the lowest hardware cost, thereby supporting the frequency domain synchronization of the two standards with a set of hardware structures.

Description

一种适用于CMMB和DVB-H的频域同步电路结构 A Frequency Domain Synchronization Circuit Structure Suitable for CMMB and DVB-H

技术领域 technical field

本发明属于无线数字通信技术领域,具体涉及一种同时支持CMMB和DVB-H两种移动多媒体标准的频域同步电路结构。The invention belongs to the technical field of wireless digital communication, in particular to a frequency domain synchronous circuit structure supporting two mobile multimedia standards of CMMB and DVB-H.

背景技术 Background technique

移动多媒体技术如今已经得以越来越广泛的应用。随着中国移动多媒体标准CMMB的颁布实施,移动多媒体得到了进一步的普及。多模多标准是当今移动多媒体技术发展的趋势,以同一套终端在不同地域实现对不同标准下节目的接收也是多模多标准发展的要求。同步技术作为接收终端中一个重要的部分,其在多模接收终端中的研究应用也具有非常重要的意义。Mobile multimedia technology has now been more and more widely used. With the promulgation and implementation of China's mobile multimedia standard CMMB, mobile multimedia has been further popularized. Multi-mode and multi-standard is the development trend of mobile multimedia technology today. It is also a requirement for the development of multi-mode and multi-standard to realize the reception of programs under different standards with the same set of terminals in different regions. Synchronization technology is an important part of the receiving terminal, and its research and application in the multi-mode receiving terminal is also of great significance.

研究目前主要的移动多媒体标准如欧洲标准DVB-H,中国标准CMMB,发现它们在帧结构上具有一定的共性。即都采用了多载波OFDM(正交频分复用)调制方式,都是基于导频的传输系统,都采用了循环前缀+数据体的时域符号结构等等。而同步算法的选取则是根据帧结构的特征,因此这些共性决定了可以寻求到一种融合的同步方案来支持各个标准。Study the main mobile multimedia standards such as the European standard DVB-H and the Chinese standard CMMB, and find that they have certain commonality in the frame structure. That is to say, they all adopt multi-carrier OFDM (orthogonal frequency division multiplexing) modulation, are all pilot-based transmission systems, and all use the time-domain symbol structure of cyclic prefix + data body and so on. The selection of the synchronization algorithm is based on the characteristics of the frame structure, so these commonalities determine that an integrated synchronization solution can be found to support each standard.

基于多模多标准的需求以及各个移动多媒体标准在帧结构上的共性,本发明提出了一种融合的硬件结构,能够同时支持目前两种主流的移动多媒体标准CMMB和DVB-H,实现最大程度的硬件复用。Based on the requirement of multi-mode and multi-standard and the commonality of each mobile multimedia standard in the frame structure, the present invention proposes a kind of integrated hardware structure, which can support the current two mainstream mobile multimedia standards CMMB and DVB-H at the same time, and realize maximum hardware multiplexing.

发明内容 Contents of the invention

本发明目的在于提供一种同时支持CMMB和DVB-H两种标准的频域同步电路结构,实现最大程度的硬件复用。The purpose of the present invention is to provide a frequency domain synchronous circuit structure supporting both CMMB and DVB-H standards, so as to realize maximum hardware multiplexing.

本发明根据CMMB和DVB-H两种标准在帧结构上的共性,提出了一种融合的硬件结构,实现同时对两种标准频域同步的支持,主要由整数倍载波频偏估计模块,解扰码模块,残余载波频偏及采样频偏估计模块构成,每一个模块都考虑了两种标准在同步方案上的共性从而实现硬件融合,并且通过选通信号控制不同模块的工作,从而实现不同模块对相似功能子模块的分时复用,进一步提高了硬件利用率。具体结构如图1所示,输入输出说明如表1所示。模式选择信号MODE_SEL控制当前工作模式(是CMMB还是DVB-H),并为整数倍载波频偏估计模块,解扰码模块,残余载波频偏和采样频偏估计模块送入不同的参数值。首先进行整数倍载波频偏的估计,估计并补偿完成后给出完成信号IFO_DONE,若当前模式为CMMB模式则启动解扰码模块;若当前模式为DVB-H模块则启动残余载波频偏和采样频偏估计模块。对于CMMB模式在解扰码完成之后启动余载波频偏和采样频偏估计模块。According to the commonality of the frame structure of the two standards of CMMB and DVB-H, the present invention proposes a fusion hardware structure to realize the simultaneous support of the frequency domain synchronization of the two standards. Scrambling code module, residual carrier frequency offset and sampling frequency offset estimation module, each module considers the commonality of the two standards in the synchronization scheme to achieve hardware integration, and controls the work of different modules through strobe signals to achieve different The time-division multiplexing of modules to sub-modules with similar functions further improves the utilization rate of hardware. The specific structure is shown in Figure 1, and the input and output descriptions are shown in Table 1. The mode selection signal MODE_SEL controls the current working mode (CMMB or DVB-H), and inputs different parameter values for the integer times carrier frequency offset estimation module, descrambling code module, residual carrier frequency offset and sampling frequency offset estimation module. First, estimate the carrier frequency offset of integer multiples. After the estimation and compensation are completed, the completion signal IFO_DONE will be given. If the current mode is CMMB mode, the descrambling module will be started; if the current mode is DVB-H module, the residual carrier frequency offset and sampling will be started. Frequency offset estimation module. For the CMMB mode, the remaining carrier frequency offset and sampling frequency offset estimation modules are started after the descrambling code is completed.

整数倍载波频偏估计模块,用以实现整数倍载波频偏的估计。具体结构如图2所示,输入输出说明如表2所示。由数据缓存单元,导频位置存储单元,相关模块,控制模块及伪随机序列生成模块(应用于CMMB标准)组成。模式选择信号MODE_SEL决定电路工作的当前模式(是CMMB还是DVB-H),送入MUX(多路选择器)模块进行选择,选择内容有:(1)数据缓存单元的缓存内容,若是CMMB模式,则缓存一个同步信号;若是DVB-H模式,则缓存两个连续的OFDM符号。(2)数据缓存单元的读地址控制,若是CMMB模式,则读地址控制信号为PN(伪随机)序列的位置+数据偏移ifo;若是DVB-H模式,则读地址控制信号为连续导频的位置+数据偏移。模式选择信号还通过组合逻辑门选择伪随机序列生成模块的工作模式,使该模块仅在CMMB模式下工作。数据缓存单元通过模式选择信号写入完毕后进行读取,并将读取出的结果送入相关模块进行相关运算。此时若当前模式为CMMB模式,相关运算的结果还需同伪随机序列生成模块的输出进行相关;若当前模式为DVB-H模式,则相关运算的结果直接送入下级运算,是否同伪随机序列生成模块的输出进行相关由模式选择信号控制MUX实现。该MUX的输出送入累加-绝对值模块进行累加并求绝对值。接着送入比较器,比较器的初值设为0。当输入值大于比较器初值时,则替换当前初值成为新的初值;若小于比较器初值则保留原有初值。当预设的所有数据偏移情况遍历完毕之后,得到的比较器最大值对应的数据偏移ifo就是估计的整数倍载波频偏。整数倍载波频偏估计并补偿后送出完成信号,驱动下一级模块。若是CMMB模式,则驱动解扰码模块;若是DVB-H模式,则驱动残余载波频偏及采样频偏估计模块。The integer multiple carrier frequency offset estimation module is used to realize the integer multiple carrier frequency offset estimation. The specific structure is shown in Figure 2, and the input and output descriptions are shown in Table 2. It is composed of a data cache unit, a pilot position storage unit, a correlation module, a control module and a pseudo-random sequence generation module (applied to CMMB standard). The mode selection signal MODE_SEL determines the current mode of circuit work (CMMB or DVB-H), and sends it to the MUX (multiplexer) module for selection. One synchronization signal is buffered; in DVB-H mode, two consecutive OFDM symbols are buffered. (2) The read address control of the data cache unit, if the CMMB mode, then the read address control signal is the position+data offset ifo of the PN (pseudo-random) sequence; if the DVB-H mode, then the read address control signal is a continuous pilot The position + data offset. The mode selection signal also selects the working mode of the pseudo-random sequence generation module through the combinational logic gate, so that the module only works in CMMB mode. The data buffer unit reads after writing through the mode selection signal, and sends the read result to the related module for related calculation. At this time, if the current mode is CMMB mode, the result of the correlation operation needs to be correlated with the output of the pseudo-random sequence generation module; if the current mode is DVB-H mode, the result of the correlation operation is directly sent to the lower-level operation. The output of the sequence generation module is correlated and realized by controlling the MUX with the mode selection signal. The output of the MUX is sent to the accumulation-absolute value module for accumulation and absolute value. Then it is sent to the comparator, and the initial value of the comparator is set to 0. When the input value is greater than the initial value of the comparator, the current initial value will be replaced as the new initial value; if it is less than the initial value of the comparator, the original initial value will be retained. After all the preset data offset situations have been traversed, the obtained data offset ifo corresponding to the maximum value of the comparator is the estimated integer multiple carrier frequency offset. Integer carrier frequency offset is estimated and compensated, and then a completion signal is sent to drive the next-level module. If it is in CMMB mode, it will drive the descrambling code module; if it is in DVB-H mode, it will drive the residual carrier frequency offset and sampling frequency offset estimation module.

解扰码模块,为CMMB标准特有,只需在CMMB模式下选通工作,用以扰码模式的识别以及对频域数据的正确解扰。具体结构如图3所示,输入输出说明如表3所示。由伪随机序列生成模块,相关模块,控制模块及导频位置存储单元组成。伪随机序列生成模块通过输入端的控制SRAM_MODE分别产生6种不同初值的扰码。导频位置存储单元存储导频的位置,通过读取该单元来判断当前输入是不是导频,若是导频则进行延迟直到下一个符号的相同位置导频到来。两个符号的导频分别用伪随机序列生成模块产生的6种扰码解扰后再进行相关累加,产生六种相关累加和。由于正确解扰后两个连续符号中的导频具有相关性,因此得到最大值所采取的扰码方式就是扰码模式。扰码模式确定之后即可对之后的符号进行解扰,通过共轭-相乘模块实现。The descrambling code module is unique to the CMMB standard, and only needs to be selected to work in the CMMB mode to identify the scrambling code mode and correctly descramble the frequency domain data. The specific structure is shown in Figure 3, and the input and output descriptions are shown in Table 3. It is composed of a pseudo-random sequence generation module, a correlation module, a control module and a pilot location storage unit. The pseudo-random sequence generation module generates scrambling codes with 6 different initial values through the control SRAM_MODE of the input terminal. The pilot position storage unit stores the position of the pilot, and judges whether the current input is a pilot by reading the unit, and if it is a pilot, delays until the arrival of the pilot at the same position of the next symbol. The pilots of the two symbols are respectively descrambled by six kinds of scrambling codes generated by the pseudo-random sequence generation module, and then correlated and accumulated to generate six kinds of correlated accumulated sums. Since the pilots in two consecutive symbols are correlated after correct descrambling, the scrambling mode used to obtain the maximum value is the scrambling mode. After the scrambling mode is determined, the following symbols can be descrambled, which is realized by the conjugate-multiplication module.

残余载波频偏及采样频偏估计模块,用以估计残余载波频偏及采样频偏。具体结构如图4所示,输入输出说明如表4所示。由相关模块,幅角计算模块,导频缓存单元及导频位置存储单元组成。模式选择信号MODE_SEL选择当前工作的模式,通过MUX控制导频位置的判断,从而进行导频缓存,缓存的连续两个符号的导频进行相关,然后送入幅角计算模块进行求幅角运算,然后进行一些常系数运算后得到最终的估计结果。常系数在CMMB和DVB-H下有所不同,事先存储然后通过模式选择信号进行选择。The residual carrier frequency offset and sampling frequency offset estimation module is used to estimate the residual carrier frequency offset and sampling frequency offset. The specific structure is shown in Figure 4, and the input and output descriptions are shown in Table 4. It is composed of a correlation module, an argument calculation module, a pilot buffer unit and a pilot position storage unit. The mode selection signal MODE_SEL selects the current working mode, and controls the judgment of the pilot position through the MUX, so as to perform pilot caching. The cached pilots of two consecutive symbols are correlated, and then sent to the argument calculation module to calculate the argument. Then some constant coefficient operations are performed to get the final estimation result. The constant coefficients are different under CMMB and DVB-H, they are stored in advance and then selected through the mode selection signal.

整数倍载波频偏估计模块和解扰码模块中都用到了伪随机序列生成模块,只是生成序列的初值,移位寄存器个数和反馈信号不同,并且不同时工作,因此可以对一个移位寄存器组附加控制信号进行复用。具体结构如图5所示,输入输出说明如表5所示。它可由控制模块和移位寄存器组(序列)组成,控制模块改变初值、移位寄存器个数、反馈信号,从而应用于不同的模块。模式选择信号MODE_SEL控制伪随机序列生成模块的工作模式(生成同步信号序列还是扰码),通过选择器MUX选择,选择内容有:(1)移位寄存器组的初值,若是生成同步信号则选择同步信号的初值;若是生成扰码则选择具体6种模式中的某一种。(2)移位寄存器组的个数,若是生成同步信号则为11个;若是生成扰码则为12个。(3)移位寄存器组的反馈信号,若是生成同步信号则选通第9个和第11个移位寄存器进行模二相加反馈给第1个寄存器;若是生成扰码则选通第6,8,11,12个移位寄存器进行模二相加反馈给第1个寄存器。(4)输出值,生成同步信号则设第11个移位寄存器的输出为有效;若是生成扰码则设第9和第12个移位寄存器的输出为有效。以上步骤完成所选模式下伪随机序列生成模块的工作。Both the integer carrier frequency offset estimation module and the descrambling module use the pseudo-random sequence generation module, which only generates the initial value of the sequence. The number of shift registers is different from the feedback signal, and they do not work at the same time. Therefore, a shift register can be Group additional control signals for multiplexing. The specific structure is shown in Figure 5, and the input and output descriptions are shown in Table 5. It can be composed of a control module and a shift register group (sequence). The control module changes the initial value, the number of shift registers, and the feedback signal, so as to be applied to different modules. The mode selection signal MODE_SEL controls the working mode of the pseudo-random sequence generation module (generates a synchronization signal sequence or a scrambling code), and is selected by the selector MUX. The selection content includes: (1) The initial value of the shift register group, if the synchronization signal is generated, select The initial value of the synchronization signal; if a scrambling code is generated, select one of the 6 specific modes. (2) The number of shift register groups is 11 if synchronous signals are generated, and 12 if scrambling codes are generated. (3) The feedback signal of the shift register group, if a synchronous signal is generated, the 9th and the 11th shift registers are selected for modulo two addition and fed back to the first register; if a scrambling code is generated, the 6th is selected, 8, 11, and 12 shift registers perform modulo two addition and feed back to the first register. (4) output value, if a synchronization signal is generated, the output of the eleventh shift register is set to be valid; if a scrambling code is generated, the outputs of the ninth and twelfth shift registers are set to be valid. The above steps complete the work of the pseudo-random sequence generation module in the selected mode.

上述发明内容,能够很好地满足对CMMB及DVB-H两种标准下频域同步的支持,以一套硬件结构实现了两种标准频域同步的融合,同时提高硬件利用率,实现最大程度的硬件复用。The content of the above invention can well meet the support of frequency domain synchronization under the two standards of CMMB and DVB-H, realize the integration of frequency domain synchronization of the two standards with a set of hardware structure, improve the utilization rate of hardware at the same time, and realize maximum hardware multiplexing.

附图说明 Description of drawings

图1适用于CMMB及DVB-H的频域同步整体硬件结构图Figure 1 is suitable for the overall hardware structure of frequency domain synchronization for CMMB and DVB-H

图2整数倍载波频偏估计模块结构图Figure 2 The structure diagram of the integer times carrier frequency offset estimation module

图3解扰码模块结构图Figure 3 Descrambling module structure diagram

图4残余载波频偏及采样频偏估计模块结构图Figure 4 Structure diagram of residual carrier frequency offset and sampling frequency offset estimation module

图5伪随机序列生成模块结构图Figure 5 Pseudo-random sequence generation module structure diagram

具体实施方式 Detailed ways

根据发明内容中的方案,适用于CMMB及DVB-H的频域同步电路的具体实施方式如下:According to the scheme in the summary of the invention, the specific implementation of the frequency domain synchronization circuit applicable to CMMB and DVB-H is as follows:

(1)首先进行整数倍载波频偏的估计。(1) Firstly, estimate the carrier frequency offset of integer times.

对于CMMB标准,整数倍载波频偏估计算法如下:For the CMMB standard, the integer carrier frequency offset estimation algorithm is as follows:

C(k)=R(k)·R*(k+D)·PN(k-m)C(k)=R(k)·R * (k+D)·PN(km)

ifoifo ^^ == argarg maxmax || ΣΣ kk ∈∈ Mm ++ ifoifo CC (( kk )) || ,, ifoifo ∈∈ [[ -- ii maxmax ,, ii maxmax ]]

其中R(k),R(k+D)表示FFT(快速傅立叶变换)解调后的同步信号的第k个和第k+D个符号,“*”表示共轭运算,PN(k-m)表示本地PN序列的移位。表示估计的整数倍载波频偏,集合M表示所选取的PN序列的集合,集合[-imax,imax]表示算法能检测的最大整数倍频偏。Among them, R(k), R(k+D) represent the kth and k+D symbols of the synchronous signal demodulated by FFT (Fast Fourier Transform), " * " represents the conjugate operation, PN(km) represents Shift of the local PN sequence. Indicates the estimated integer multiple carrier frequency offset, the set M indicates the set of selected PN sequences, and the set [-i max , i max ] indicates the maximum integer multiple frequency offset that the algorithm can detect.

对于DVB-H标准,整数倍载波频偏估计算法如下:For the DVB-H standard, the integer carrier frequency offset estimation algorithm is as follows:

CC (( kk )) == ZZ nno (( kk )) ·&Center Dot; ZZ nno -- 11 ** (( kk ))

ifoifo ^^ == argarg maxmax || ΣΣ kk ∈∈ PP ++ ifoifo CC (( kk )) || ,, ifoifo ∈∈ [[ -- ii maxmax ,, ii maxmax ]]

其中Zn(k),Zn-1(k)分别表示FFT后第n个和第n-1个OFDM信号中第k个符号,集合P表示连续导频的集合,集合[-imax,imax]表示算法能检测的最大整数倍频偏。Among them, Z n (k), Z n-1 (k) respectively represent the k-th symbol in the nth and n-1th OFDM signals after FFT, and the set P represents the set of continuous pilots, and the set [-i max , i max ] represents the maximum integer multiple frequency offset that the algorithm can detect.

可以发现两种算法都是基于相关-寻找最大值的方法,只是需要缓存的数据以及相关的方式不相同。因此可以如下处理:It can be found that both algorithms are based on correlation-finding the maximum value, but the data to be cached and the correlation methods are different. So it can be handled as follows:

对于数据缓存单元,当前模式为CMMB时,缓存一个同步信号;当前模式为DVB-H时,缓存两个连续的OFDM符号。For the data buffer unit, when the current mode is CMMB, one synchronization signal is buffered; when the current mode is DVB-H, two consecutive OFDM symbols are buffered.

当前模式为CMMB时,连续读取数据缓存单元中的符号进行延迟相关;当前模式为DVB-H时,通过读取导频位置存储单元中导频的位置来读取数据缓存单元中的符号进行相关。When the current mode is CMMB, read the symbols in the data buffer unit continuously for delay correlation; when the current mode is DVB-H, read the symbols in the data buffer unit by reading the position of the pilot in the pilot position storage unit for delay correlation. relevant.

当前模式为CMMB时,相关后的结果需乘以PN(k-m),PN(k-m)由伪随机序列生成模块产生。但由于PN(k-m)的取值为1和-1,因此相乘只需用对被乘数取反或者取原值来实现即可。When the current mode is CMMB, the result after correlation needs to be multiplied by PN(k-m), and PN(k-m) is generated by the pseudo-random sequence generation module. However, since the values of PN(k-m) are 1 and -1, the multiplication only needs to be realized by inverting the multiplicand or taking the original value.

相关累加的结果送入控制模块,判断最大值,当集合[-imax,imax]遍历完毕时,所取得的最大值的ifo值即是所估计的整数倍频偏。The result of correlation accumulation is sent to the control module to determine the maximum value. When the set [-i max , i max ] is traversed, the ifo value of the maximum value obtained is the estimated integer multiple frequency offset.

整数倍频偏估计模块只需工作一次,整数倍载波频偏估计并校正之后给出完成信号,对于DVB-H系统,启动残余载波频偏和采样频偏估计模块;对于CMMB系统,启动解扰码模块,此模块为CMMB系统特有。The integer multiple frequency offset estimation module only needs to work once, and the integer multiple carrier frequency offset estimation and correction will give a completion signal. For DVB-H system, start the residual carrier frequency offset and sampling frequency offset estimation module; for CMMB system, start descrambling Code module, this module is unique to CMMB system.

(2)解扰码模块的算法如下:(2) The algorithm of the descrambling module is as follows:

根据”正确解扰的相邻两个OFDM符号的连续导频具有相关性”,扰码模式识别算法如下所示:According to "The continuous pilots of two adjacent OFDM symbols that are correctly descrambled are correlated", the scrambling code pattern recognition algorithm is as follows:

sthe s cramcram == argarg maxmax ii ∈∈ [[ 0,50,5 ]] || ΣΣ kk ∈∈ PP [[ (( ZZ nno (( kk )) ·&Center Dot; PP cc ,, ii ** (( nno ×× NN VV ++ kk )) )) ·· (( ZZ nno -- 11 (( kk )) ·&Center Dot; PP cc ,, ii ** (( (( nno -- 11 )) ×× NN VV ++ kk )) )) ** ]] ||

其中Pc,i(k),i∈[0,5]表示不同的扰码模式下的扰码值,NV表示每一个OFDM符号中有效子载波(包括数据子载波和导频)个数。Pc,i(k)共有六种取值,由伪随机序列生成模块产生。where P c, i (k), i∈[0,5] represent the scrambling code values in different scrambling modes, and N V represents the number of valid subcarriers (including data subcarriers and pilots) in each OFDM symbol . P c, i (k) has six values in total, which are generated by the pseudo-random sequence generation module.

扰码模式判定之后即可进行解扰,解扰由FFT后的OFDM符号同Pc,i(k)相乘完成。由于Pc,i(k)的取值为

Figure G200910056140XD00052
可以看作同±1±i相乘,因此相乘只需对被乘数取反或者取原值实现。Descrambling can be performed after the scrambling mode is determined, and the descrambling is completed by multiplying the OFDM symbol after FFT by P c,i (k). Since P c, the value of i (k) is
Figure G200910056140XD00052
It can be regarded as multiplication with ±1±i, so the multiplication only needs to invert the multiplicand or take the original value to realize.

解扰码模块需要一直工作。对于CMMB模式,每个OFDM符号解扰码后给出完成信号,即可启动残余载波频偏和采样频偏估计模块。The descrambling module needs to work all the time. For the CMMB mode, after each OFDM symbol is descrambled and a completion signal is given, the residual carrier frequency offset and sampling frequency offset estimation modules can be started.

(3)残余载波频偏和采样频偏估计模块的算法如下:(3) The algorithm of residual carrier frequency offset and sampling frequency offset estimation module is as follows:

对于两种标准,残余载波频偏和采样频偏估计的算法都可用下式表示:For both standards, the algorithms for residual carrier frequency offset and sampling frequency offset estimation can be expressed as follows:

DD. (( kk )) == ZZ nno (( kk )) ·&Center Dot; ZZ nno -- 11 ** (( kk )) ,, kk ∈∈ PP

ββ == ΣΣ kk ∈∈ PP 11 argarg (( DD. (( kk )) )) -- ΣΣ kk ∈∈ PP 22 argarg (( DD. (( kk )) )) 22 ππ (( NN sthe s // NN )) (( ΣΣ kk ∈∈ PP 11 kk -- ΣΣ kk ∈∈ PP 22 kk )) ,, ϵϵ == ΣΣ argarg (( DD. (( kk )) )) 22 ππ (( NN sthe s // NN )) ·· Mm -- ΣΣ PP 22 kk ++ ΣΣ PP 22 kk Mm -- 11 ββ

其中集合P表示连续导频的集合,集合P1,P2分别表示连续导频的前一半和后一半,M表示选取的连续导频个数,Ns,N分别表示含有循环前缀和不含循环前缀OFDM符号长度,在CMMB和DVB-H标准中都有不同取值。β为估计的采样频偏,ε为估计的残余载波频偏。Among them, the set P represents the set of continuous pilots, the sets P1 and P2 respectively represent the first half and the second half of the continuous pilots, M represents the number of selected continuous pilots, N s , and N represent the cyclic prefix and non-cyclic prefix respectively OFDM symbol length has different values in both CMMB and DVB-H standards. β is the estimated sampling frequency offset and ε is the estimated residual carrier frequency offset.

可以看出该模块的基本运算相同,只是对应不同标准集合P不同。因此只需将两种标准下连续导频的位置存储于不同的导频位置存储单元,根据当前模式选择读取不同的导频位置存储单元,从而在导频缓存单元中缓存不同的信号。缓存的信号进行相关,幅角计算,然后根据不同的模式选取不同的Ns,N,M值完成残余频偏和采样频偏的计算。It can be seen that the basic operations of this module are the same, but the sets P corresponding to different standards are different. Therefore, it is only necessary to store the positions of continuous pilots under the two standards in different pilot position storage units, and select and read different pilot position storage units according to the current mode, thereby buffering different signals in the pilot buffer unit. The cached signal is correlated, the argument is calculated, and then different N s , N, M values are selected according to different modes to complete the calculation of the residual frequency offset and sampling frequency offset.

(4)相同硬件在不同模块之间的复用:(4) Multiplexing of the same hardware among different modules:

在整数倍载波频偏估计,解扰码,残余载波频偏和采样频偏估计三个模块中都用到了相关模块。相关的本质为复数相乘及求和。由于三个模块并不同时工作,因此相关模块可以在三个主模块中分时复用。由于相关对时序的要求并不严格,不需要进行并行相乘和求和,因此可以仅使用一个复数乘法器和一个累加器,大大降低硬件代价。Correlation modules are used in the three modules of integer carrier frequency offset estimation, descrambling code, residual carrier frequency offset and sampling frequency offset estimation. The essence of the correlation is the multiplication and summation of complex numbers. Since the three modules do not work at the same time, the related modules can be time-division multiplexed among the three main modules. Since the relevant timing requirements are not strict, there is no need for parallel multiplication and summation, so only one complex multiplier and one accumulator can be used, which greatly reduces the hardware cost.

CMMB模式下,整数倍载波频偏估计及解扰码模块都用到了伪随机序列生成模块,并且此两个模块并不同时工作。因此可以共用一个伪随机序列生成模块,将该模块的初始值,移位寄存器个数,反馈信号做成可配置,即可应用于上述两个模块,具体结构如图5所示,输入输出说明如表5所示。In CMMB mode, both the integer carrier frequency offset estimation and descrambling modules use the pseudo-random sequence generation module, and the two modules do not work at the same time. Therefore, a pseudo-random sequence generation module can be shared, and the initial value of the module, the number of shift registers, and the feedback signal can be made configurable, which can be applied to the above two modules. The specific structure is shown in Figure 5, and the input and output description As shown in Table 5.

在上述方案中,使用了本发明提出的硬件融合复用,同单模式的频域同步方案相比,仅仅附加了一些控制电路及小的存储单元,能够实现对两种标准下频域同步的支持,以一套硬件结构实现了CMMB和DVB-H两种标准频域同步的融合。In the above scheme, the hardware fusion multiplexing proposed by the present invention is used. Compared with the single-mode frequency domain synchronization scheme, only some control circuits and small storage units are added, which can realize frequency domain synchronization under the two standards. Support, with a set of hardware structure to realize the fusion of CMMB and DVB-H two standard frequency domain synchronization.

Figure G200910056140XD00061
Figure G200910056140XD00061

表1.整体硬件结构图输入输出说明Table 1. Input and output description of the overall hardware structure diagram

Figure G200910056140XD00071
Figure G200910056140XD00071

表2.整数倍载波频偏估计模块输入输出说明Table 2. Integer times carrier frequency offset estimation module input and output description

Figure G200910056140XD00072
Figure G200910056140XD00072

表3.解扰码解扰码模块输入输出说明Table 3. Descrambling code descrambling module input and output description

Figure G200910056140XD00073
Figure G200910056140XD00073

表4.残余载波频偏及采样频偏估计模块输入输出说明Table 4. Residual carrier frequency offset and sampling frequency offset estimation module input and output description

Figure G200910056140XD00081
Figure G200910056140XD00081

表5.伪随机序列生成模块输入输出说明Table 5. Description of the input and output of the pseudo-random sequence generation module

Claims (6)

1. a frequency-domain synchronous circuit structure that is applicable to CMMB and DVB-H is characterized in that, by integral multiple carrier deviation estimation module, and the descrambling code module, residual carrier frequency deviation and sampling frequency offset estimation module constitute;
Integral multiple carrier deviation estimation module, the integral multiple carrier deviation estimation of support CMMB and two kinds of standards of DVB-H;
The descrambling code module is applied to the computing of scrambler pattern recognition and descrambling code under the CMMB pattern;
Residual carrier frequency deviation and sampling frequency offset estimation module support the residual carrier frequency deviation of two kinds of standards and sampling frequency offset to estimate;
Mode select signal MODE_SEL control work at present pattern is CMMB or DVB-H, and is integral multiple carrier deviation estimation module, the descrambling code module, and the residual carrier frequency deviation is sent into different parameter values with the sampling frequency offset estimation module; At first carry out the estimation of integer-time carrier wave frequency deviation, provide after estimation and compensation are finished and finish signal IFO_DONE,, after descrambling code is finished, start over-carriage ripple frequency deviation and sampling frequency offset estimation module if present mode is that the CMMB pattern then starts the descrambling code module; If present mode is that the DVB-H module then starts residual carrier frequency deviation and sampling frequency offset estimation module.
2. circuit structure according to claim 1, it is characterized in that in two kinds of standards, the estimation of integral multiple carrier deviation estimation module all is based on the relevant of frequency domain signal specific, it is by data buffer storage unit, the pilot frequency locations memory cell, correlation module, control module and pseudo random sequence generation module are formed;
The present mode of mode select signal MODE_SEL decision-making circuit work is CMMB or DVB-H, sending into MUX MUX module selects, chosen content has: the cache contents of (1) data buffer storage unit, if CMMB pattern, then synchronizing signal of buffer memory; If DVB-H pattern, then two continuous OFDM symbols of buffer memory; (2) address of reading of data buffer storage unit is controlled, if the CMMB pattern, then reading address control signal is the position+data-bias ifo of PN sequence; If the DVB-H pattern is then read position+data-bias that address control signal is a continuous pilot; Mode select signal is also selected the mode of operation of pseudo random sequence generation module by combinational logic gate, this module is only worked under the CMMB pattern; Data buffer storage unit writes by mode select signal and reads after finishing, and the result that will read out sends into correlation module and carries out related operation; This moment, the result of related operation also needed to be correlated with the output of pseudo random sequence generation module if present mode is the CMMB pattern; Whether if present mode is the DVB-H pattern, then the result of related operation directly sends into subordinate's computing, be correlated with by mode select signal control MUX realization with the output of pseudo random sequence generation module; The output of this MUX sends into and adds up-and absolute value block adds up and asks absolute value; Then send into comparator, the initial value of comparator is made as 0; When input value during greater than the comparator initial value, then replacing current initial value becomes new initial value; If input value then keeps original initial value less than the comparator initial value; After all default data-bias situation traversals finished, the data-bias ifo of the comparator maximum correspondence that obtains was exactly the integer-time carrier wave frequency deviation of estimating; Send after integral multiple carrier deviation estimation and the compensation and finish signal, drive the next stage module; If the CMMB pattern then drives the descrambling code module; If the DVB-H pattern then drives residual carrier frequency deviation and sampling frequency offset estimation module.
3. circuit structure according to claim 1 is characterized in that, the descrambling code module is finished the pattern recognition and the descrambling code of scrambler, by the pseudo random sequence generation module, and correlation module, control module and pilot frequency locations memory cell are formed;
The pseudo random sequence generation module produces the scrambler of 6 kinds of different initial values respectively by input control SRAM_MODE; The position of pilot frequency locations cell stores pilot tone judges that by reading this unit current input is a pilot tone, if pilot tone then postpones to arrive up to the same position pilot tone of next symbol; Be correlated with again behind 6 kinds of scrambler descramblings that the pilot tone of two symbols produces with the pseudo random sequence generation module respectively and add up, produces six kinds be correlated with add up with; Obtaining the scrambler mode that maximum takes is exactly the scrambler pattern; Can carry out descrambling to symbol afterwards after the scrambler pattern is determined, realize by the conjugation-module that multiplies each other.
4. circuit structure according to claim 1, it is characterized in that, in two kinds of standards, residual carrier frequency deviation and sampling frequency offset are estimated by the relevant of continuous pilot in the adjacent two symbols and are got argument and finish, residual carrier frequency deviation and sampling frequency offset estimation module are by correlation module, the argument computing module, pilot tone buffer unit and pilot frequency locations memory cell are formed;
Mode select signal MODE_SEL selects the pattern of work at present, judgement by MUX control pilot frequency locations, thereby carry out the pilot tone buffer memory, the pilot tone of continuous two symbols of buffer memory is correlated with, send into the argument computing module then and ask the argument computing, carry out then obtaining final estimated result after some constant coefficient computings.
5. according to claim 2,3 or 4 described circuit structures; It is characterized in that correlation module is the Multiplexing module of integral multiple carrier deviation estimation module, descrambling code module, residual carrier frequency deviation and sampling frequency offset estimation module, and not in synchronization work, correlation module adopts serial relevant, and only uses a complex multiplier.
6. according to claim 2 or 3 described circuit structures, it is characterized in that the pseudo random sequence generation module is the Multiplexing module of integral multiple carrier deviation estimation module and descrambling code module, it is made of control module and shift-register sequence; Control module changes initial value, shift register number, feedback signal, thereby is applied to disparate modules.
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