CN101625836A - Pixel circuit and driving method thereof - Google Patents

Abstract

The invention discloses a pixel circuit and a driving method thereof, wherein the pixel circuit comprises a pixel capacitor, a storage capacitor, a first transistor and a second transistor, wherein the storage capacitor and the pixel capacitor are provided with a shared end, the first transistor is electrically connected between a data line and the shared end, the grid electrode of the first transistor is electrically connected with a first grid line, the second transistor is electrically connected between the shared end and a gray scale voltage, the grid electrode of the second transistor is electrically connected with a second grid line, and the first grid line is adjacent to the second grid line.

Description

Pixel circuit and driving method thereof

technical field

The present invention relates to a black frame insertion (Black Frame Insertion) technology, and in particular to a pixel circuit applied to black/gray insertion in a frame and its driving method.

Background technique

In recent years, the demand for liquid crystal displays (Liquid Crystal Display, LCD) has greatly increased, and there is a trend of developing towards larger sizes. When the size of the liquid crystal display panel increases, not only its resolution increases, but also the demand for TV dynamic image display increases greatly, because the driving method of the liquid crystal display is a hold-type (Hold-type) rather than a cathode ray tube (cathode ray tube). Ray Tube (CRT) is Impulse-type, and its liquid crystal response speed is slow, so when displaying dynamic images, image blurring, dragging or color shifting will occur.

In view of the increasingly stringent requirements of consumers for the quality of moving images, eliminating the blur effect (blur effect) caused by the hold-on display has gradually become an important issue, and Black Frame Insertion Technology is one of the methods. At present, the technology to solve the dynamic image blur is mainly divided into three categories, including frequency doubling, dynamic backlight control (Dynamic Backlight Control1) and inserting black screen data, etc., the purpose of which is to change the driving mode of the liquid crystal display from the maintenance mode to the pulse mode. Drive mode, in order to achieve better dynamic image display quality.

In the US public document US2006/0164380, the black insertion technology provided is to divide the liquid crystal display panel into multiple display areas, and use a multi-tasker and an algorithm to determine the display blocks of the black screen. The more display blocks the panel is divided into, the better the effect of black insertion, but the number of display blocks is limited by the resolution of the panel and has its upper limit, so the higher the resolution of the panel, the better the effect of this technology The better the improvement.

The dynamic image quality improvement technology proposed by U.S. Patent US6819311 is characterized in that two independent transistors are set in the pixel, and independent gate drivers and source drivers are used to write data and insert black pixels, thereby improving the dynamic image quality. The display quality of the image. However, its panel needs twice the number of gate lines and two independent driving chips, so the design of its driving circuit is more complicated and the cost is higher.

Contents of the invention

The present invention provides a pixel circuit. A transistor is added to the pixel electrode, and the bias voltage of the pixel electrode is turned on to the grayscale voltage or common voltage by using the enable signal of the gate line, so as to achieve the effect of black/gray insertion in the picture.

The present invention provides a display panel. With the pixel circuit of the present invention, when a gate line is enabled, data writing and screen black insertion can be performed on pixels in two pixel columns at the same time, so as to improve the display effect of dynamic pictures. .

The invention provides a driving method suitable for the display panel of the invention. Firstly, divide the picture period into the first period and the second period, drive the odd number of gate lines in the first period, and drive the even number of gate lines in the second period, through interlaced driving, in the same picture period At the same time, the effect of data writing and screen black/gray insertion is completed to improve the screen display quality.

Based on the above, the present invention proposes a display panel comprising N pixel columns, N gate lines and a plurality of data lines, wherein each of the pixel columns has a plurality of pixels, and the gate lines correspond to the pixel columns , wherein the (i+1)th gate line is electrically connected to the i-th pixel column and the pixels corresponding to the (i+1)-th pixel column, i is a positive integer, and 1≦i<N. The plurality of data lines correspond to the pixels of the pixel columns, wherein when the i+1th gate line is enabled, the i+1th pixel column is turned on to receive the plurality of pixel drives output by the data lines voltage, and the i-th pixel column receives a gray-scale voltage for image interpolation of black/gray.

In an embodiment of the present invention, in the above display panel, each of the pixel circuits on the i-th pixel column includes a first pixel capacitor, a first storage capacitor, a first transistor and a second transistor. The first pixel capacitor is electrically connected between the first sharing end and the common voltage, one end of the first storage capacitor is electrically connected to the first sharing end, and the first transistor is electrically connected to one of the corresponding data lines and the first sharing end. terminals, and the gate of the first transistor is electrically connected to the i-th gate line, and the second transistor is electrically connected between the first shared terminal and the first grayscale voltage, and the gate of the second transistor electrically connected to the i+1th gate line.

In an embodiment of the present invention, each of the pixel circuits in the i-th pixel column further includes a coupling capacitor, a second pixel capacitor, a second storage capacitor, and a third transistor. The coupling capacitor is electrically connected between the first sharing terminal and the second sharing terminal, and the second pixel capacitor is electrically connected between the second sharing terminal and the common voltage. One end of the second storage capacitor is electrically connected to the second common end; and the third transistor is electrically connected between the second common end and the second grayscale voltage, and the gate of the third transistor is electrically connected to the i+ 1 grid line.

In an embodiment of the present invention, the other end of the first storage capacitor is electrically connected to the first gray scale voltage or the common voltage, and the other end of the second storage capacitor is electrically connected to the second gray scale voltage or the common voltage. .

In an embodiment of the present invention, the above-mentioned first gray-scale voltage and the second gray-scale voltage may be equal to a common voltage or correspond to a voltage value of a gray-scale frame.

In an embodiment of the present invention, each of the pixel circuits in the i-th pixel column includes a first pixel capacitor, a first storage capacitor, a first transistor, a second transistor, a second pixel capacitor, and a second storage capacitor and a third transistor. Wherein, the first pixel capacitor is electrically connected between the first sharing end and the common voltage, and one end of the first storage capacitor is electrically connected to the first common end. The first transistor is electrically connected between one of the corresponding data lines and the first shared terminal, and the gate of the first transistor is electrically connected to the i-th gate line; the second transistor is electrically connected to the first shared terminal. terminal and the second shared terminal, and the gate of the second transistor is electrically connected to the i-th gate line; the second pixel capacitor is electrically connected between the second shared terminal and the common voltage; the second storage capacitor One end is electrically connected to the second common end, and the third transistor is electrically connected between the second common end and the first gray scale voltage, and the gate of the third transistor is electrically connected to the (i+1)th gate line .

In an embodiment of the present invention, the other ends of the first storage capacitor and the second storage capacitor are electrically connected to the first gray scale voltage or the common voltage.

From one point of view, the present invention further proposes a pixel circuit, which can be applied to interpolation of black/gray images. The pixel circuit includes a first pixel capacitor, a first storage capacitor, a first transistor and a second transistor. The first pixel capacitor is electrically connected between the first shared end and the common voltage, and one end of the first storage capacitor is electrically connected to the first shared end. The first transistor is electrically connected between the data line and the first shared end, and the gate of the first transistor is electrically connected to the first gate line, and the second transistor is electrically connected between the first shared end and the first gray end. between the step voltages, and the gate of the second transistor is electrically connected to a second gate line, wherein the first gate line is adjacent to the second gate line.

The present invention further provides a pixel circuit including a first pixel capacitor, a first storage capacitor, a first transistor, a second transistor, a second pixel capacitor, a second storage capacitor and a third transistor. The first pixel capacitor is electrically connected between the first sharing end and the common voltage, and one end of the first storage capacitor is electrically connected to the first common end. The first transistor is electrically connected between the data line and the first sharing end, and the gate of the first transistor is electrically connected to a first gate line, and the second transistor is electrically connected between the first sharing end and the second sharing end. terminals, and the gate of the second transistor is electrically connected to the first gate line. The second pixel capacitor is electrically connected between the second sharing end and the common voltage, and one end of the second storage capacitor is electrically connected to the second common end, and the third transistor is electrically connected between the second sharing end and the first gray between the step voltages, and the gate of the third transistor is electrically connected to the second gate line, wherein the first gate line is adjacent to the second gate line.

Cooperating with the above-mentioned display panel and pixel circuit, the present invention proposes a driving method suitable for driving the above-mentioned display panel. The display panel includes N pixel columns corresponding to N gate lines respectively, wherein when the i+1th gate When the line is enabled, the i+1th pixel column is turned on to receive multiple pixel driving voltages output by these data lines, and the i-th pixel column receives the grayscale voltage to perform black/gray interpolation on the screen, N and i are positive integer, and 1≤i<N, the driving method includes: dividing a frame period into a first period and a second period, and then sequentially scanning the gate lines in the first period of the frame period Odd-numbered gate lines; during the second period of the frame period, even-numbered gate lines of the gate lines are sequentially scanned.

In an embodiment of the present invention, the above-mentioned second period may be after the first period, or the first period may be after the second period.

The present invention utilizes the unique pixel circuit and structure design, integrates it into the display panel, and cooperates with the driving method of interval scanning, so that the pixel circuit of the display panel synchronously performs data processing on the adjacent pixel columns as the gate lines are enabled. Write and screen insert black/gray. In terms of circuit design, the present invention only needs to add transistors for black/gray insertion in the pixel structure, and can be applied to most liquid crystal displays without additional drive circuit design, and can achieve screen insertion in a low-cost manner. Black/gray effect.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments of the present invention, together with the accompanying drawings, are described in detail below.

Description of drawings

FIG. 1 is a circuit diagram of a display according to an embodiment of the present invention.

FIG. 2 is a timing diagram of signals according to this embodiment.

FIG. 3 is a diagram of the driving state of the panel according to the present embodiment.

FIG. 4 is a state diagram of gate line driving according to the first embodiment of the present invention.

FIG. 5A is a circuit diagram of a pixel according to a second embodiment of the present invention.

FIG. 5B is a pixel layout diagram according to FIG. 5A.

FIG. 6A is a circuit diagram of a pixel according to a third embodiment of the present invention.

FIG. 6B is a pixel layout diagram according to FIG. 6A.

FIG. 7A is a circuit diagram of a pixel according to a fourth embodiment of the present invention.

FIG. 7B is a pixel layout diagram according to FIG. 7A.

FIG. 8 is a flowchart of a display driving method according to a fifth embodiment of the present invention.

Detailed ways

first embodiment

FIG. 1 is a circuit diagram of a display according to an embodiment of the present invention. The liquid crystal display 100 includes a display panel 110 , a gate driver 120 and a source driver 130 , wherein the display panel 110 includes pixel columns S ₁ -S _2n , gate lines G ₁ -G _2n , and n is a positive integer. The gate driver 120 is used for outputting gate scanning signals, and the source driver 130 is used for outputting pixel driving signals. In this embodiment, all the pixels corresponding to one gate line are represented by a pixel row, so each pixel row has a plurality of pixels, and the equivalent circuit of its pixel structure is represented by a pixel circuit.

In the display panel 110, each pixel column S ₁ -S _2n includes a plurality of pixel circuits (such as 111-113, 121-123, 131-133), and is electrically connected to the upper and lower adjacent gate lines G correspondingly. ₁ -G _2n , and each gate line G ₁ -G _2n is also electrically connected to the upper and lower adjacent pixel circuits. Taking the gate line G ₂ as an example, the pixel circuits 111 - 113 , 121 - 123 are all electrically connected to the gate line G ₂ . When the gate line _G2 is enabled, the pixel circuits 121-123 corresponding to the pixel column _S2 are turned on and receive the pixel driving voltage output by the data lines D1-D3, while the pixel circuits 111-113 corresponding to the pixel column _S1 Then it is turned on to the grayscale voltage to perform black/gray image insertion. Therefore, when the gate line _G2 is enabled, one of its adjacent pixel columns will write normal data, while the other pixel column will perform black/gray image interpolation. The operation modes of the other gate lines are analogously deduced and will not be repeated here.

Utilizing the above-mentioned characteristics, this embodiment uses an interlaced driving method (scanning method with one gate line apart), divides one frame period into two periods, and scans an odd number of gate lines (such as G ₁ , G ₃ , G ₅ ) first. . . . ), and then scan the even-numbered gate lines (such as G ₂ , G ₄ , G ₆ . Taking the adjacent gate lines _Gn and Gn ₊₁ as an example, when the gate line _Gn is enabled, the gate line Gn ₊₁ will be enabled only after half a frame period. When scanning odd-numbered gate lines, the corresponding odd-numbered pixel columns (such as S ₁ , S ₃ , S ₅ ...) will write normal signals, while the even-numbered pixel columns (such as S ₂ , S ₄ , S ₆ ...) will perform black/gray interpolation on the screen. Conversely, when scanning even numbered gate lines, the corresponding even numbered pixel columns (such as S ₂ , S ₄ , S ₆ . . . ) will write normal signals, while the odd numbered pixel columns (such as S ₁ , S ₃ , S ₅ ...) will interpolate black/gray on the screen. In this way, each pixel column will maintain half a frame period after data writing (receiving pixel driving voltage), and then perform black/gray insertion (receive grayscale voltage of black frame or gray frame) for half frame cycle.

Next, the driving method of this embodiment is further described with reference to the waveform diagram of FIG. 2 . FIG. 2 is a signal timing diagram according to this embodiment. The waveforms W1 and W2 are used to represent the driving timings of different driving polarities. Taking the first frame F1 as an example, the frame period is divided into a first period T1 and a second period T2, and the scanning method is shown in FIG. 2 . In the first period T1, scan the odd-numbered gate lines (G ₁ , G ₃ , G ₅ ... G _2n-1 ) sequentially, and in the second period T2, scan the even-numbered gate lines sequentially Scanning of (G ₂ , G ₄ , G ₆ . . . G _2n ). In this embodiment, different scanning methods (bottom-up, middle-outward, and block scanning) can also be used to scan the gate lines in different orders, as long as the interval scanning method is used.

In addition, with the driving method of this embodiment, the gate driver 120 can drive the gate lines G ₁ -G _2n of the entire display panel 110 only by half of the gate driving signals GP ₁ -GP _n . Since only half of the gate lines (odd or even) need to be driven in the same period (T1 or T2), the gate drive signals GP ₁ to GP _n can scan the odd gate lines in the first period T1 (G ₁ , G ₃ , G ₅ . . . G _2n−1 ), and then switch to an even number of gate lines (G ₂ , G ₄ , G ₆ . . . G _2n ) in the second period T2. In the circuit design, a switch can be designed to switch the output paths of the gate drive signals GP ₁ to GP _n , switch to odd-numbered gate lines in the first period T1, and switch to even-numbered gate lines in the second period T2 polar line. In another embodiment of the present invention, the above-mentioned driving method can also drive the even-numbered gate lines (G ₂ , G ₄ , G ₆ . . . G _2n ) first, and then drive the odd-numbered gate lines (G ₁ , G ₃ , G _{5 .} . . G _2n-1 ).

FIG. 3 is a diagram of the driving state of the panel according to the present embodiment. The diagram on the left side of Figure 3 shows the driving state in the first period T1, and the white part indicates that the pixels of the odd gate lines (G ₁ , G ₃ , G ₅ ...G _2n-1 ) belong to the normal display state, while the diagonal The line part indicates that the pixels of the even numbered gate lines (G ₂ , G ₄ , G ₆ . . . G _2n ) belong to the inserted black/gray state. The diagram on the right side of FIG. 3 shows the driving state in the second period T2, wherein odd-numbered gate lines (G ₁ , G ₃ , G ₅ . . . G _2n-1 ) and even-numbered gate lines (G ₂ , The display states of G ₄ , G ₆ ... G _2n ) are reversed.

FIG. 4 is a state diagram of gate line driving according to the first embodiment of the present invention. In FIG. 4 , only some of the gate lines G ₁ -G ₆ in the display panel 110 are taken as an example. In the first period T1, the gate driver 120 drives the gate lines G ₁ , G ₃ , and G ₅ sequentially, and The pixels corresponding to the gate lines G ₂ and G ₄ (that is, the pixel circuits on the pixel columns S ₂ and S ₄ , such as 121-123, 141-143) are turned on due to the enabling of the gate lines G ₃ and G ₅ . Pass to the gray scale voltage. When entering the second period T2, the gate lines G ₂ , G ₄ , and G ₆ are sequentially driven, which are represented by frames 410 - 430 respectively. In the screen 410, the gate line _G2 is enabled, so the pixel corresponding to the gate line _G1 is turned on to the grayscale voltage to perform black/gray interpolation on the screen, while the gate line _G2 performs normal data writing , the pixels on the gate line _G3 are still in a hold-type state. By analogy, the screen display states when the gate lines G ₄ and G ₆ are enabled are shown in screens 420 and 430 . When entering the first period T1 of the next screen, the odd-numbered gate lines G ₁ , G ₃ , and G ₅ are sequentially enabled, and the screen display status is shown in screens 440-460, and the operation details are analogized, and will not be repeated. Tired.

second embodiment

Next, the pixel circuit of the present invention will be further described. Taking the pixel circuit 111 as an example, FIG. 5A is a diagram of the pixel circuit according to the second embodiment of the present invention. Pixel circuit 500 represents one implementation of pixel circuit 111 . The pixel circuit 500 includes transistors TFT1 , TFT2 , a pixel capacitor CLC and a storage capacitor CST, and is electrically connected between adjacent gate lines G ₁ , G ₂ . The pixel capacitor CLC and the storage capacitor CST have a shared end 510, the other end of the pixel capacitor CLC is electrically connected to a common voltage (common voltage, which can be a ground voltage level or a specific voltage level) VCOM, and the storage capacitor CST is electrically connected to It is connected between the common terminal 510 and the gray scale voltage VCS. The transistor TFT1 is electrically connected between the data line D1 and the sharing terminal 510, and the gate of the transistor TFT1 is electrically connected to the gate line _G1 , and the transistor TFT2 is electrically connected between the sharing terminal 510 and the gray scale voltage VCS, And the gate of the transistor TFT2 is electrically connected to the gate line G ₂ .

The voltage on the sharing terminal 510 is called the pixel driving voltage VP. The pixel driving voltage VP is mainly provided by the data line D1. When the gate line _G1 is enabled, the transistor TFT1 is turned on, and the data line D1 outputs the pixel driving voltage VP to the sharing terminal 510 to charge the pixel capacitor CLC and the storage capacitor CST. When the gate line _G2 is enabled, the transistor TFT2 is turned on, so the voltage level of the common terminal 510 (originally the pixel driving voltage VP) is affected by the gray-scale voltage VCS and changed to the gray-scale voltage VCS. Therefore, the pixel circuit 111 displays a black picture or a gray picture according to the changed pixel driving voltage VP. If the grayscale voltage VCS is equal to the common voltage VCOM, the voltage difference across the pixel capacitor CLC tends to be zero, and the deflection angle of the liquid crystal tends to be closed, and the pixel circuit 111 has the effect of inserting a black screen. If the gray-scale voltage VCS is not equal to the common voltage VCOM, the pixel circuit 111 will display gray images with different gray-scale levels according to the voltage value of the gray-scale voltage VCS. Therefore, the inserted gray can be set only by adjusting the gray-scale voltage VCS. The grayscale value of the image. In another embodiment of the present invention, the transistor TFT2 can also be electrically connected between the shared terminal 510 and the common voltage VCOM or an independently set grayscale voltage (not shared with the storage capacitor CST), which also has pixel insertion black/gray Effect. The equivalent circuits of the remaining pixels in the display panel 110 are the same as the pixel circuit 111 , and will not be described in detail here.

FIG. 5B is a pixel layout diagram according to FIG. 5A, wherein the main difference from the known ones lies in the transistor TFT2, which is located in the lower right corner of the pixel, and is electrically connected in parallel to the storage capacitor. As for the pixel electrode (pixel electrode) layout pattern, it can be different Display requirements vary, and this embodiment is not limited.

third embodiment

Next, the present invention applies the circuit design concept of the second embodiment to different pixel structures. FIG. 6A is a pixel circuit diagram according to the third embodiment of the present invention. Also taking the location of the pixel circuit 111 as an example, the pixel circuit 600 represents another implementation manner of the pixel circuit 111 . The pixel circuit 600 includes transistors TFT1 - TFT3 , pixel capacitors CLC1 , CLC2 , and storage capacitors CST1 , CST2 . In this embodiment, the pixel circuit 600 is mainly formed by two sub-pixel structures, the pixel capacitor CLC1 and the storage capacitor CST1 form a sub-pixel, and the pixel capacitor CLC2 and the storage capacitor CST2 form another sub-pixel. This kind of pixel structure has different application methods, for example, it is applied to a wide view angle (wide view angle) liquid crystal display.

The circuit structure of the pixel capacitor CLC1 , the storage capacitor CST1 , and the transistor TFT1 is similar to the circuit structure of FIG. 5A , and will not be repeated here. Both ends of the pixel capacitor CLC2 and the storage capacitor CST2 are electrically connected to the common terminal 620 , the other end of the pixel capacitor CLC2 is electrically connected to the common voltage VCOM, and the other end of the storage capacitor CST2 is electrically connected to the gray scale voltage VCS. The transistor TFT3 is electrically connected between the sharing terminal 620 and the gray scale voltage VCS, and the gate of the transistor TFT3 is electrically connected to the gate line G ₂ , and the transistor TFT2 is electrically connected between the sharing terminal 620 and the sharing terminal 510 , And the gate of the transistor TFT2 is electrically connected to the gate line G ₁ .

When the gate line _G1 is enabled, the transistors TFT1 and TFT2 are turned on, and the data line D1 writes the pixel driving voltage VP1 and VP2 into the pixel circuit 600, and the pixel driving voltage VP1 and VP2 are equal without considering the path loss . When the gate line _G2 is enabled, the sharing terminal 620 will be turned on to the grayscale voltage VCS through the transistor TFT3, so that the voltage level of the sharing terminal 620 (originally the pixel driving voltage VP2) is equal to the grayscale voltage VCS (if considering the capacitance Influenced by charging and discharging, the voltage level of the sharing terminal 620 will gradually approach the gray scale voltage VCS), at this time, the picture presented by the pixel circuit 111 is a black picture or a gray picture (depending on the voltage value of the gray scale voltage VCS Certainly). In another embodiment of the present invention, the transistor TFT3 can also be arranged between the sharing terminal 510 and the common voltage VCOM, or a transistor can be added between the sharing terminal 510 and the common voltage VCOM, and at the same time controlled by the gate line G ₂ . In this way, the voltage level of the shared terminals 510 and 620 will change faster after the gate line _G2 is enabled, and the effect of black/gray insertion in the picture will be more significant. In addition, the voltage level of the grayscale voltage VCS can be equal to the common voltage VCOM, which also has the effect of black/gray insertion in the picture.

FIG. 6B is a pixel layout diagram according to FIG. 6A , wherein the positions of the transistors TFT1 - TFT3 are as shown in FIG. 6B . The pixel electrode 630 of the pixel capacitor CLC1 and the pixel electrode 640 of the pixel capacitor CLC2 are respectively shown in FIG. 6B . FIG. 6B is only one of the layout modes of the pixel circuit in FIG. 6A , and this embodiment is not limited to this layout mode.

Fourth embodiment

FIG. 7A is a circuit diagram of a pixel according to a fourth embodiment of the present invention. The pixel circuit 700 is another embodiment of the pixel circuit 111 , which is also formed by two sub-pixel structures. The pixel circuit 700 includes transistors TFT1 - TFT3 , pixel capacitors CLC1 , CLC2 , storage capacitors CST1 , CST2 and a coupling capacitor CCP. The coupling capacitor CCP is electrically connected between the sharing terminal 510 and the sharing terminal 720 , and the pixel capacitor CLC2 is electrically connected between the sharing terminal 720 and the common voltage VCOM. The storage capacitor CST2 is electrically connected between the sharing terminal 720 and the gray-scale voltage VCS, the transistor TFT3 is electrically connected between the sharing terminal 720 and the gray-scale voltage VCS, and the gate of the transistor TFT3 is electrically connected to the gate line _G2 , and the circuit structure of the pixel capacitor CL1 , the storage capacitor CST1 , and the transistor TFT1 is similar to the circuit structure of FIG. 5A , and will not be repeated here.

When the gate line _G1 is enabled, the transistor TFT1 is turned on, and the data line D1 outputs the pixel driving voltage VP1 to the sharing terminal 510, and is coupled to the sharing terminal 720 via the coupling capacitor CCP to form the pixel driving voltage VP2. At this time, the pixel circuit 700 is in the normal display state, and when the gate line _G2 is enabled, the transistors TFT2 and TFT3 are turned on, and the shared terminal 510 and the shared terminal 720 are both turned on to the grayscale voltage VCS, so that the original The pixel driving voltages VP1 and VP2 are equal to or close to the gray scale voltage VCS. At this time, the pixel circuit 700 is in a state of black/gray interpolation on the screen.

FIG. 7B is a pixel layout diagram according to FIG. 7A , where the positions of the transistors TFT1 - TFT3 are as shown in FIG. 7B . The layout positions of the pixel electrode 730 of the pixel capacitor CLC1 , the pixel electrode 740 of the pixel capacitor CLC2 and the coupling capacitor CCP are respectively shown in FIG. 7B . FIG. 7B is only one layout of the pixel circuit in FIG. 7A , and this embodiment is not limited to this layout.

When the pixel circuit 500, 600 or 700 is applied to the pixel design of the display panel 110, in conjunction with the interlaced driving method in the first embodiment, the data writing and screen black/gray insertion operations can be performed simultaneously, and then the results shown in Figure 3 and The picture in Figure 4 inserts the black/gray effect. Since the enable time of adjacent gate lines will be separated by half a frame period, each pixel will maintain half a frame period after data is written, and then the screen will be black/gray due to the enablement of the next gate line. Phenomenon. That is to say, in the second half frame period, the pixels are turned on to the grayscale voltage, so that the driving waveform of the pixel is similar to the pulse driving waveform, so as to improve the display quality of the dynamic picture.

fifth embodiment

Combining the implementation methods and technical means of the above-mentioned embodiments, a display driving method can be summarized, which is suitable for the display panel and pixels of the above-mentioned embodiments. FIG. 8 is a flow chart of the display driving method according to the fifth embodiment of the present invention. In this embodiment, if the display panel includes N pixel columns, they correspond to N gate lines respectively, wherein when the i+1th gate line is enabled, the i+1th pixel column is turned on to receive the A plurality of pixel driving voltages output by the data lines, and the i-th pixel column receives a grayscale voltage, wherein N and i are positive integers, and 1≤i<N. The driving method of this embodiment includes the following steps: First, step S810 divides the frame period into a first period and a second period, and then step S820 sequentially scans odd-numbered gates in the gate line during the first period of the frame period lines; and step S830 scans the even-numbered gate lines sequentially in the second period of the frame period.

In other words, in this embodiment, the gate lines in the display panel are driven in an interlaced driving manner, so that adjacent gate lines can respectively perform data writing and black/gray image insertion at the same time. Half of the gate lines in the display panel are scanned in the first half of the frame period, and the remaining half of the gate lines in the display panel are scanned in the second half of the frame period. In addition, the scanning order of each frame can also be changed accordingly with the change of the driving mode (from bottom to top or from top to bottom) or driving polarity (such as dot inversion or column inversion) of the display panel (such as first scan the even number of gate lines, and then scan the odd number of gate lines), that is, the sequence of the first period and the second period are reversed. The remaining details of the driving method are described in the above-mentioned embodiments in detail, and those who have ordinary knowledge in the technical field can easily deduce it through the disclosure of the present invention, so they are not repeated here.

The present invention uses the timing control signal and is different from the previous pixel circuit design to change the scanning mode of each picture to the interlaced driving mode (scan the odd-numbered bars first and then the even-numbered bars, or scan the even-numbered bars first and then scan the odd-numbered bars). , so that the LCD can write data and insert black/gray on the screen at the same time. Utilizing the pixel circuit design of the present invention, the effect of inserting black/gray on the screen can be achieved without complex circuit design or adding a driver chip, and the effect of inserting black/gray on the screen will not be affected by the resolution of the screen. limit.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims.

Claims (22)

1. display panel comprises:

N bar pixel column, each those pixel column has a plurality of image element circuits;

N bar gate line, corresponding to those pixel columns, wherein i+1 bar gate line is electrically connected at those image element circuits that i bar pixel column and i+1 pixel column are corresponded to, and wherein i, N are positive integer, and 1≤i＜N; And

Many data lines are corresponding to those image element circuits of those pixel columns;

Wherein, when i+1 bar gate line enabled, i+1 bar pixel column was opened to receive a plurality of pixel drive voltage that those data lines are exported, and i bar pixel column then receives one first gray scale voltage to carry out picture black frame insertion/ash.

2. display panel as claimed in claim 1 is characterized in that, each those image element circuit in the i bar pixel column comprise:

One first pixel capacitance is electrically connected at one first and shares between end and the common voltage;

One first storage capacitors, an end of this first storage capacitors are electrically connected at this first shared end;

One the first transistor be electrically connected between one of corresponding those data lines and this first shared end, and the grid of this first transistor is electrically connected at i bar gate line; And

One transistor seconds be electrically connected between this first shared end and this first gray scale voltage, and the grid of this transistor seconds is electrically connected at i+1 bar gate line.

3. display panel as claimed in claim 2 is characterized in that, the other end of this first storage capacitors is electrically connected at this first gray scale voltage or this common voltage.

4. display panel as claimed in claim 2 is characterized in that, this first gray scale voltage equals this common voltage.

5. display panel as claimed in claim 2 is characterized in that, each those image element circuit on the i bar pixel column also comprise:

One coupling capacitance is electrically connected at this first shared end and one second and shares between the end;

One second pixel capacitance is electrically connected between this second shared end and this common voltage;

One second storage capacitors, an end of this second storage capacitors is electrically connected at this second common ends; And

One the 3rd transistor be electrically connected between this second shared end and one second gray scale voltage, and the 3rd transistorized grid is electrically connected at i+1 bar gate line.

6. display panel as claimed in claim 5 is characterized in that, the other end of this second storage capacitors is electrically connected at this second gray scale voltage or this common voltage.

7. display panel as claimed in claim 5 is characterized in that, this second gray scale voltage equals this common voltage.

8. display panel as claimed in claim 1 is characterized in that, each those image element circuit in the i bar pixel column comprise:

One first pixel capacitance is electrically connected at one first and shares between end and the common voltage;

One first storage capacitors, an end of this first storage capacitors is electrically connected at this first common ends;

One the first transistor be electrically connected between one of corresponding those data lines and this first shared end, and the grid of this first transistor is electrically connected at i bar gate line;

One transistor seconds is electrically connected at this first shared end and one second and shares between the end, and the grid of this transistor seconds is electrically connected at i bar gate line;

One second pixel capacitance is electrically connected between this second shared end and this common voltage;

One second storage capacitors, an end of this second storage capacitors is electrically connected at this second common ends; And

One the 3rd transistor be electrically connected between this second shared end and this first gray scale voltage, and the 3rd transistorized grid is electrically connected at i+1 bar gate line.

9. display panel as claimed in claim 8 is characterized in that, the other end of this first storage capacitors and this second storage capacitors is electrically connected at this first gray scale voltage or this common voltage.

10. display panel as claimed in claim 8 is characterized in that, this first gray scale voltage equals this common voltage.

11. an image element circuit comprises:

One first pixel capacitance is electrically connected at one first and shares between end and the common voltage;

One first storage capacitors, an end of this first storage capacitors are electrically connected at this first shared end;

One the first transistor be electrically connected between a data line and this first shared end, and the grid of this first transistor is electrically connected at a first grid polar curve; And

One transistor seconds be electrically connected between this first shared end and one first gray scale voltage, and the grid of this transistor seconds is electrically connected at a second grid line;

Wherein, this first grid polar curve is adjacent with this second grid line.

12. image element circuit as claimed in claim 11 is characterized in that, the other end of this first storage capacitors is electrically connected at this first gray scale voltage or this common voltage.

13. image element circuit as claimed in claim 11 is characterized in that, this first gray scale voltage equals this common voltage.

14. image element circuit as claimed in claim 11 is characterized in that, also comprises:

One coupling capacitance is electrically connected at this first shared end and one second and shares between the end;

One second pixel capacitance is electrically connected between this second shared end and this common voltage;

One second storage capacitors, an end of this second storage capacitors is electrically connected at this second common ends; And

One the 3rd transistor be electrically connected between this second shared end and one second gray scale voltage, and the 3rd transistorized grid is electrically connected at this second grid line.

15. image element circuit as claimed in claim 14 is characterized in that, the other end of this second storage capacitors is electrically connected at this second gray scale voltage or this common voltage.

16. image element circuit as claimed in claim 14 is characterized in that, this second gray scale voltage equals this common voltage.

17. an image element circuit comprises:

One first pixel capacitance is electrically connected at one first and shares between end and the common voltage;

One first storage capacitors, an end of this first storage capacitors is electrically connected at this first common ends;

One the first transistor be electrically connected between a data line and this first shared end, and the grid of this first transistor is electrically connected at a first grid polar curve;

One transistor seconds is electrically connected at this first shared end and one second and shares between the end, and the grid of this transistor seconds is electrically connected at this first grid polar curve;

One second pixel capacitance is electrically connected between this second shared end and this common voltage;

One second storage capacitors, an end of this second storage capacitors is electrically connected at this second common ends; And

One the 3rd transistor be electrically connected between this second shared end and one first gray scale voltage, and the 3rd transistorized grid is electrically connected at this second grid line;

Wherein, this first grid polar curve is adjacent with this second grid line.

18. image element circuit as claimed in claim 17 is characterized in that, the other end of this first storage capacitors and this second storage capacitors is electrically connected at this first gray scale voltage or this common voltage.

19. image element circuit as claimed in claim 17 is characterized in that, this first gray scale voltage equals this common voltage.

20. driving method, be used to drive a display panel, this display panel comprises N bar pixel column, correspond respectively to N bar gate line, wherein when i+1 bar gate line enables, i+1 bar pixel column open with receive those data lines exported more than individual pixel drive voltage, the i pixel column then receives a gray scale voltage to carry out picture black frame insertion/ash, wherein N, i are positive integer, and 1≤i＜N, and this driving method comprises:

One picture cycle is divided between a first phase and a second phase;

Between a first phase of this picture cycle, scan the odd number bar gate line in those gate lines in regular turn; And

In a second phase of this picture cycle, scan the even number bar gate line in those gate lines in regular turn.

21. driving method as claimed in claim 20 is characterized in that, this second phase between this first phase after.

22. driving method as claimed in claim 20 is characterized in that, between this first phase after this second phase.

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