CN101621083A - Semiconductor solar cells having front surface electrodes and method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor solar cell with a front surface electrode and a method for forming the same. A solar cell includes a substrate having a light collecting surface thereon and a PN rectifying junction within the substrate. The PN rectifying junction includes a base region of a first conductivity type (eg, p-type) and a semiconductor layer of a second conductivity type extending between the base region and a light-collecting surface. A trench extending through the semiconductor layer and into the base region is also provided. The first electrode and the second electrode are disposed adjacent to the light collecting surface. The first electrode is electrically coupled to the semiconductor layer, and the second electrode is electrically coupled to the base region at a location adjacent the bottom of the trench.

Description

Semiconductor solar cell with front surface electrode and method of forming same

technical field

The present invention relates to solar cells and methods of forming the same, and more particularly, to semiconductor solar cells and methods of forming the same.

Background technique

A solar cell is a device that converts solar energy, such as sunlight, into electricity. Solar cells have many applications. A single battery can be used to power a small device, while a large array of batteries (for example, a photovoltaic array) can be used to generate a form of renewable energy that is not available from the power grid Especially useful. Solar arrays are now also being developed for grid-based electrical systems.

Solar cells operate by generating electron-hole pairs in a substrate (eg, a semiconductor substrate) in response to the absorption of photons incident on the substrate. When a photon is absorbed, its energy is transferred to electrons in the crystal lattice of the substrate. Typically, this electron is in the valence band of the crystal lattice and tightly bound in covalent bonds between adjacent atoms. The energy imparted to the electron by the photon may be sufficient to excite the electron into the conduction band of the lattice where it then becomes free to move within the substrate. A covalent bond of which an electron was previously a part is now missing an electron, which is called a "hole". The presence of the missing covalent bond allows a bound electron from a neighboring atom to move into this "hole", leaving another hole behind, in this way the hole can move throughout the crystal lattice. This movement of electrons and holes within the substrate can then be used to establish a DC voltage across a load connected to the solar cell.

Specifically, the built-in electric field generated in the p-n junction may be sufficient to induce electrons and holes in electron-hole pairs to move to the n-type semiconductor region and the p-type semiconductor region, respectively. One example of a solar cell using a p-n junction and electrode pairs on opposing surfaces of a semiconductor substrate is disclosed in US Patent Nos. 4,726,850 and 4,748,130. Another example of a solar cell is disclosed in US Patent No. 7,335,555 to Gee et al., entitled "Buried-Contact Solar Cell With Self-Doping Contacts."

Contents of the invention

A solar cell according to an embodiment of the present invention includes a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes: a base region of a first conductivity type (eg, p-type) and a semiconductor layer of a second conductivity type extending between the base region and a light-collecting surface. A trench extending through the semiconductor layer and into the base region is also provided. The first electrode and the second electrode are disposed adjacent to the light collecting surface. The first electrode is electrically coupled to the semiconductor layer, and the second electrode is electrically coupled to the base region at a location adjacent to the bottom of the trench.

According to an additional embodiment of the present invention, the solar cell may further comprise electrically insulating trench sidewall spacers on the trench sidewalls, which extend between the second electrode and the semiconductor layer of the second conductivity type and provide a gap between the two. electrical isolation. In addition, the semiconductor layer of the second conductivity type may be an amorphous silicon layer having a different band gap from that of single crystal silicon. Specifically, the semiconductor layer of the second conductivity type may be an amorphous silicon layer forming a heterojunction in the substrate. The solar cell according to these embodiments may further include a boundary layer of the second conductivity type extending between the semiconductor layer of the second conductivity type and the base region. The boundary layer of the second conductivity type can form a non-rectifying heterojunction with the semiconductor layer of the second conductivity type and form a P-N rectification junction with the base region.

Embodiments of the invention also include an antireflection layer on the light collecting surface. The light collecting surface can be configured to have a non-uniform surface profile with localized peaks and valleys. Specifically, the non-rectifying heterojunction can have a non-planar junction profile and the light collecting surface can have a non-uniform surface profile that approximates the non-planar junction profile of the non-rectifying heterojunction. Furthermore, the non-rectifying heterojunction may have a first non-planar junction profile, and the rectifying junction between the boundary layer and the base region may have a second non-planar junction profile that approximates the shape of the first non-planar junction profile.

Additional embodiments of the invention include methods of forming solar cells. Some of these methods include forming a semiconductor layer of a second conductivity type (eg, n-type) on a semiconductor substrate having a base region of a first conductivity type (eg, p-type) therein. A first trench is also formed extending through the semiconductor layer of the second conductivity type and into the base region. The step of forming the first trench may be followed by the step of forming the anti-reflection layer on the semiconductor layer of the second conductivity type. A trench sidewall spacer is formed on a sidewall of the first trench. A second trench is also formed extending through the bottom of the first trench and further into the base region. The first trench and the second trench may be strip-shaped trenches extending across the substrate. The second trench is filled with a first electrode electrically coupled to the base region. The step of filling the second trench may be after implanting the first conductive type dopant into the bottom and sidewalls of the second trench. The second electrode may also be formed in contact with the semiconductor layer of the second conductivity type. The second electrode may be formed outside and/or inside the first trench.

According to some of these method embodiments, the step of forming the first trench may follow the step of forming a boundary layer of the second conductivity type in the base region. The boundary layer can convert a portion of the base region from the first conductivity type to a net second conductivity type by diffusing a sufficient amount of the second conductivity type dopant from the semiconductor layer into the base region. The boundary layer may form a non-rectifying heterojunction with the semiconductor layer, which may include amorphous silicon. The semiconductor layer can be formed by depositing an in situ doped amorphous silicon layer on the surface of the substrate. The surface may have a non-uniform surface profile with localized peaks and valleys.

A method of forming a solar cell according to additional embodiments of the present invention includes texturizing a surface of a silicon wafer having a base region of a first conductivity type to create localized peaks and valleys in the surface. After the surface has been textured, a layer of in situ doped amorphous silicon of the second conductivity type can be deposited onto the textured surface, thereby defining a textured non-rectifying heterojunction with the surface. The amorphous silicon layer may have a doping concentration therein ranging from about 1×10 ¹⁹ cm ⁻³ to about 1×10 ²¹ cm ⁻³ . A portion of the base region is then converted from a net first conductivity type to a net second conductivity type by diffusing a sufficient amount of a second conductivity type dopant from the amorphous silicon layer into the base region, the second conductivity type A boundary layer forms in the base region. A trench is then formed extending through the amorphous silicon layer and the boundary layer and into the base region. A first electrode and a second electrode are also formed. The first electrode is electrically coupled to the amorphous silicon layer, and the second electrode is electrically coupled to the base region adjacent to the bottom of the trench. In some of these embodiments of the invention, the step of forming the first electrode and the second electrode includes depositing the second electrode at the bottom of the trench and depositing the first electrode adjacent to the top of the trench after covering the second electrode with an electrically insulating spacer layer. electrode.

According to some of these embodiments of the invention, the step of texturing includes etching the surface of the silicon wafer by exposing the surface to an etchant that causes a residue to form on the surface, which serves as a localized etch mask for further etching. mold. In particular, the step of texturing the surface may include exposing the surface to a dry etchant containing chlorine and fluorine. Specifically, the dry etchant may be formed by mixing chlorine (Cl ₂ ), oxygen (O ₂ ), and SF ₆ source gases in a low-pressure process chamber.

到约

范围内的优选厚度的边界层。而且，形成沟槽的步骤可以包括通过在硅晶片的表面中形成多个十字交叉(criss-crossing)凹槽来形成网格状沟槽。网格状沟槽还可以包括邻近硅晶片外围的最外环形沟槽。还可以在形成第一电极的步骤之后，选择性去除环形沟槽中第一电极的一部分和下面的电绝缘间隔层的一部分，从而暴露第二电极。According to an additional embodiment of the present invention, the step of forming the boundary layer comprises forming a boundary layer having a temperature of from about

to appointment

range of preferred thicknesses for the boundary layer. Also, the step of forming the grooves may include forming grid-like grooves by forming a plurality of criss-crossing grooves in the surface of the silicon wafer. The grid-shaped trenches may also include an outermost annular trench adjacent to the periphery of the silicon wafer. It is also possible to selectively remove a portion of the first electrode and a portion of the underlying electrically insulating spacer layer in the annular trench after the step of forming the first electrode, thereby exposing the second electrode.

Description of drawings

1 is a cross-sectional view of an integrated circuit solar cell according to an embodiment of the present invention;

2 is an enlarged cross-sectional view of a protruding portion of the solar cell of FIG. 1;

3-9 are cross-sectional views of intermediate structures which, in conjunction with FIG. 1, illustrate a method of forming an integrated circuit solar cell according to an embodiment of the present invention;

Figure 10A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 10B is a cross-sectional view of the integrated circuit solar cell of Figure 10A taken along line I-I';

11 is an enlarged cross-sectional view of a protruding portion of the solar cell of FIG. 10B;

Figure 12A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 12B is a cross-sectional view of the integrated circuit solar cell of Figure 12A taken along line I-I';

Figure 12C is an alternative cross-sectional view of the integrated circuit solar cell of Figure 12A along line I-I';

Figure 13A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 13B is a cross-sectional view of the integrated circuit solar cell of Figure 13A taken along line I-I';

14A-20A are plan views of intermediate structures illustrating methods of forming integrated circuit solar cells according to embodiments of the invention;

Figures 14B-20B are cross-sectional views taken along line I-I' of the intermediate structure of Figures 14A-20A;

21A-23A are plan views of intermediate structures illustrating various methods of forming integrated circuit solar cells illustrated in FIGS. 12A and 12C in accordance with embodiments of the present invention;

21B-23B are cross-sectional views taken along line I-I' of the intermediate structure of FIGS. 21A-23A;

24A-25A are plan views of intermediate structures illustrating various methods of forming integrated circuit solar cells according to embodiments of the invention;

24B-25B are cross-sectional views taken along line I-I' of the intermediate structure of FIGS. 24A-25A;

26 is a block diagram of a photovoltaic system capable of using integrated circuit solar cells according to embodiments of the invention;

Figure 27A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 27B is a cross-sectional view of the solar cell embodiment of Figure 27A taken along line II'.

28A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 28B is a cross-sectional view taken along line I-I' of the solar cell embodiment of Figure 28A;

29A is a cross-sectional view of an integrated circuit solar cell according to an embodiment of the invention;

Figure 29B is a cross-sectional view taken along line I-I' of the solar cell embodiment of Figure 29A;

Figure 30A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 30B is a cross-sectional view taken along line I-I' of the solar cell embodiment of Figure 30A;

Figure 31A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 31B is a cross-sectional view taken along line I-I' of the solar cell embodiment of Figure 31A;

Figure 32A is a plan view of an integrated circuit solar cell according to an embodiment of the invention;

Figure 32B is a cross-sectional view taken along line I-I' of the solar cell embodiment of Figure 32A;

Figure 33 is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

34A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 34B is a cross-sectional view taken along line I-I' of the solar cell embodiment of Figure 34A;

Figure 34C is a cross-sectional view taken along line II-II' of the solar cell embodiment of Figure 34A;

Figure 35 is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 36A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 36B is a cross-sectional view taken along line I-I' of the solar cell embodiment of Figure 36A;

Figure 37A is a plan view of an integrated circuit solar cell according to an embodiment of the present invention;

Figure 37B is a cross-sectional view of the solar cell embodiment of Figure 37A taken along line II'.

Detailed ways

The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention. communicated to those skilled in the art. The same reference numerals refer to the same elements throughout, and signal lines and signals thereon may be denoted by the same reference symbols.

It will be understood that when a layer (or film) is referred to in the specification as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Also, in the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Also, words like 'first', 'second' and 'third' are used to describe various regions and layers in different embodiments of the present invention, and these regions and layers are not limited by these words. These terms are only used to distinguish one region or layer from another region or layer. Thus, what is referred to as a "first layer" in one embodiment may be referred to as a "second layer" in another embodiment.

Referring now to FIGS. 1-2 , a solar cell according to an embodiment of the present invention may include a substrate having an upper surface representing a light collection surface and a bottom surface extending opposite to the upper surface. The substrate is shown to include a semiconductor substrate region 110, which may be doped with a first conductivity type dopant (eg, a p-type dopant). Specifically, the substrate region 110 may initially be a p-type monocrystalline silicon wafer, which may undergo semiconductor processing steps illustrated by FIGS. 3-9 as will be described below. The substrate may further include a semiconductor layer 120 of a second conductivity type (for example, n-type) extending on the substrate region 110 . The upper surface of the second conductive type semiconductor layer 120 may serve as a light collection surface, and the anti-reflection layer 131 may be formed on the light collection surface. The purpose of the anti-reflection layer 131 may be to provide increased light collection efficiency by reducing reflection of incident light away from the light collection surface, among other things.

As specifically shown in Figure 2 (which highlights the region "A" shown in Figure 1), the substrate region 110 includes a base region 110b of a net first conductivity type (eg, p-type) and a net second conductivity type The boundary layer 110a of the boundary layer 110a forms a P-N rectifying junction with the base region 110b. As described more fully below, the boundary layer 110a may be formed by diffusing a sufficient amount of a dopant (eg, an n-type dopant) from the semiconductor layer 120 of the second conductivity type into the base region 110b so that the base region A portion of 110b transitions from the first conductivity type to the net second conductivity type.

到约范围内的厚度的边界层110a可以通过减少其中的电子-空穴复合来支持高程度的光收集效率。The boundary layer 110 a and the semiconductor layer 120 of the second conductivity type may jointly form a conduction region 122 of the second conductivity type. In addition, the semiconductor layer 120 of the second conductivity type may be formed as an amorphous silicon layer, which forms a non-rectifying heterojunction with the boundary layer 110a. By increasing the wavelength range that can be trapped to generate electron-hole pairs near the PN junction, the heterojunction can advantageously support higher light collection efficiency relative to the homojunction. The semiconductor layer 120 can be a relatively highly doped layer, for example, it can be formed as an in-situ doped semiconductor layer with a second conductivity type (such as phosphorus), wherein the doping concentration is about 10 ¹⁹ cm ⁻³ to about 10 ²¹ cm ^-3 range. The thickness of the boundary layer 110a is selected to increase solar cell efficiency by reducing undesired electron-hole recombination near the PN junction. While not wishing to be bound by any theory, an insufficiently thick boundary layer 110a is associated with a relatively high degree of electron-hole recombination caused by the interaction between the boundary layer 110a and the semiconductor layer 120 of the second conductivity type. caused by interfacial defects at the heterojunction. Alternatively, an excessively thick boundary layer 110a can be confined by relatively high electron-hole recombination caused by excess carrier drift (i.e., migration) through the wide depletion region surrounding the PN junction. cause. Based on these considerations, for a given semiconductor material, with

to appointment A thickness of the boundary layer 110a in the range may support a high degree of light collection efficiency by reducing electron-hole recombination therein.

The anti-emission layer 131 (which may be deposited on the semiconductor layer 120 of the second conductivity type) may have a thickness of about λ/4 in order to increase light absorption efficiency, where λ is the desired light intensity to be incident on the light collecting surface during operation of the solar cell. the wavelength of light. Also, the anti-reflection layer 131 may be formed in a multi-layer structure, for example, a layer including a silicon oxide layer and a silicon nitride layer. In addition to increasing the light collection efficiency of the solar cell, the anti-reflection layer 131 can also serve to protect and provide electrical passivation to the underlying light collection surface of the solar cell.

Referring also to FIG. 2, the light collecting surface (which is shown as the interface between the semiconductor layer 120 of the second conductivity type and the antireflection layer 131) can be configured to have a non-uniform surface profile with localized peaks and valleys. This non-uniform surface profile may be manifested as a plurality of spaced apart pyramid-shaped protrusions shown in the surface of the anti-reflection layer 131 . Specifically, the non-rectifying heterojunction between the semiconductor layer 120 of the second conductivity type and the boundary layer 110a may have a non-planar junction profile, and the light collecting surface may have a non-rectifying heterojunction close to the non-planar junction profile of the non-rectifying heterojunction. Uniform surface profile. Also, the non-rectifying heterojunction may have a first non-planar junction profile, and the rectifying junction between the boundary layer 110a and the base region 110b may have a second non-planar junction profile that approximates the shape of the first non-planar junction profile.

The solar cell of Figure 1 also includes a pair of electrodes disposed on the light collecting surface. The electrode pair is shown as a first electrode 141 (which is electrically coupled to the base region 110b) and a second electrode 143 (which is electrically coupled to the semiconductor layer 120 of the second conductivity type). These electrodes may be strip electrodes with a relatively narrow width, which reduces shading losses at the light collecting surface. The first electrode 141 and the second electrode 143 may be made of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN ) formed from at least one metal of the group consisting of. Electrodes 141 and 143 may also include metal silicide layers and/or multilayer conductors such as Ti/TiN/Al or Ti/TiN/W.

A trench 116 may also be provided, which extends through the semiconductor layer 120 of the second conductivity type and enters the base region 110b. As explained more fully below, the trench 116 may be formed from an upper bar-shaped trench 113 and a lower bar-shaped trench 114 extending through the bottom of the upper trench 113 . The lower trench 114 may have a width, for example, in a range from about 0.3 micron to about 1 micron, and have a stripe or similar shape extending across the substrate. The sidewalls of the upper trench 113 may be lined with electrically insulating sidewall spacers 115 , which may be formed, for example, as oxide and/or nitride insulating layers. The sidewall spacers 115 function to electrically insulate the first electrode 141 from the semiconductor layer 120 of the second conductivity type. Also, a relatively highly doped impurity region 117 of the first conductivity type may be formed in the sidewall and bottom of the lower trench 114 to reduce series resistance between the base region 110 b and the first electrode 141 within the lower trench 114 . Impurity region 117 may, for example, have a thickness of about 0.3 microns. As shown, a relatively shallow trench/groove 118 may also be formed in the semiconductor layer 120 and filled with the second electrode 143 .

3-9 illustrate other embodiments of the invention, including methods of forming the solar cells of FIGS. 1-2. As shown in FIG. 3, these methods may include an optional step of forming a back surface field (BSF) region 111 of a first conductivity type (eg, P-type) in a semiconductor substrate 110 of the first conductivity type (eg, a P-type wafer), The back surface field (BSF) region 111 of the first conductivity type is formed by implanting a dopant of the first conductivity type (such as boron (B)) into the opposite front surface and the back surface of the substrate 110, and then heat-treating the substrate 110 to promote implanted dopants. Thereafter, as shown in FIG. 4, the front surface of the substrate 110 may become uneven by generating a plurality of peaks and valleys therein. These peaks in the front surface are shown as having pyramids or similar structures 112 and can be formed using conventional techniques such as plasma etching, mechanical scribing, photolithography and chemical etching. For example, an oxide layer (not shown) may be formed as a sacrificial layer on the front surface of the substrate 110 and then photolithographically patterned using a patterned photoresist layer (not shown) as an etch mask. The front surface of the substrate 110 may then be etched using the patterned sacrificial layer as an etch mask. During this process, any BSF regions 111 on the front surface of the substrate 110 are typically removed.

范围内的厚度，典型地为约)可以使用各种技术被沉积。这些技术包括使用硅烷和氢气的等离子体增强化学气相沉积(PECVD)或低压CVD。具体地，原位掺杂的非晶半导体层120可以通过化学气相沉积使用硅烷(SiH₄)、磷化氢(PH₃)和氢气形成。Referring now to FIG. 5 , an amorphous semiconductor layer 120 is formed on the uneven front surface of the substrate 110 . The amorphous semiconductor layer 120 may be a net second conductivity type (eg N-type) highly doped (eg in-situ doped) layer. Specifically, the doping concentration of the second conductivity type in the amorphous semiconductor layer 120 may range from about 1×10 ¹⁹ cm ⁻³ to about 1×10 ²¹ cm ⁻³ . Amorphous semiconductor layer 120 (it can have from about hundreds of angstroms to about

range of thicknesses, typically about ) can be deposited using various techniques. These techniques include plasma enhanced chemical vapor deposition (PECVD) or low pressure CVD using silane and hydrogen. Specifically, the in-situ doped amorphous semiconductor layer 120 may be formed by chemical vapor deposition using silane (SiH ₄ ), phosphine (PH ₃ ), and hydrogen.

范围内的厚度的边界层110a。根据本发明的某些实施例，非晶半导体层120的表面的不平坦性还可以通过在非晶半导体层120上生长半球硅晶粒(HSG)层而增大，从而增加太阳能电池的光收集效率。可选地，具有粗糙表面结构的导电透光层(例如ZnO层)可以沉积在非晶半导体层120上。Referring also to FIG. 5, the boundary layer 110a of the second conductivity type is formed by diffusing the second conductivity type dopant from the amorphous semiconductor layer 120 into the substrate 110, thereby defining the boundary layer 110a, which is separated from the first conductivity type The base region 110b forms a PN rectifying junction. Such diffusion of the second conductivity type dopant may be performed by annealing the substrate 110 . In order to increase solar cell efficiency by reducing undesired electron-hole recombination near the PN rectifying junction, the annealing can be performed at a sufficient temperature and for a sufficient duration to produce a to appointment

range in thickness of the boundary layer 110a. According to some embodiments of the present invention, the unevenness of the surface of the amorphous semiconductor layer 120 can also be increased by growing a hemispherical silicon grain (HSG) layer on the amorphous semiconductor layer 120, thereby increasing the light collection of the solar cell. efficiency. Optionally, a conductive light-transmitting layer (such as a ZnO layer) with a rough surface structure may be deposited on the amorphous semiconductor layer 120 .

As shown in FIGS. 6-7 , an anti-reflection layer 131 is then formed on the amorphous semiconductor layer 120 . The anti-reflective layer 131 may be formed by depositing one or more electrically insulating layers (eg, silicon dioxide, silicon nitride) on the upper surface of the amorphous semiconductor layer 120 using a conventional deposition process (eg, plasma chemical vapor deposition (PECVD)). form. In order to increase light absorption efficiency, the anti-reflection layer 131 may have a thickness of about λ/4, where λ is the wavelength of desired light incident on the light collecting surface during operation of the solar cell. A photolithographically defined etching step (eg dry etching) may then be performed to define relatively narrow strip-shaped first trenches 113 extending through the amorphous semiconductor layer 120 and the boundary layer 110a and into the base region 110b. In some of these embodiments according to the present invention, the stripe-shaped first grooves 113 may have a width of about 1 μm or less. For example, the stripe grooves may have a width of about 0.3 μm.

Sidewall insulating spacers 115 are formed on sidewalls of the first trench 113 . These sidewall insulating spacers 115 may be formed as a silicon dioxide layer or a silicon nitride layer or as a composite of a plurality of insulating layers. The sidewall insulating spacers 115 may be formed by conformally depositing an electrically insulating layer into the first trench 113 and then anisotropically etching back the deposited layer until the bottom of the first trench 113 is exposed. This step of conformally depositing the electrically insulating layer may include depositing a protective insulating layer 132 on the bottom surface of the substrate 110 .

Referring now to FIG. 8 , the bottom of the first trench 113 is further etched using a first mask (not shown) and sidewall insulating spacers 115 as an etch mask. This etching step results in the formation of extension trenches 114, which may extend substantially into the base region 110b. The first trench and the extension trench 114 together form a multi-level trench 116 having an upper sidewall covered by a sidewall insulating spacer 115 . The step of forming the extended trench 114 may be followed by the step of forming a relatively highly doped impurity region 117 by selectively implanting a first conductivity type dopant (for example, a P-type dopant) into the bottom and sidewalls of the extended trench 114 . Thereafter, as shown in FIG. 9 , a selective etching step is then performed to etch a relatively shallow second trench 118 extending through the anti-reflection layer 131 and into the amorphous silicon layer 120 . The second trench 118 is formed shallower than the P-N rectifying junction. Then, the multi-level trench 116 and the second trench 118 are filled with the first electrode 141 and the second electrode 143 respectively, as shown in FIG. 1 . These first electrodes 141 and second electrodes 143 may be formed by depositing and then patterning a metal layer. The metal layer can be composed of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and silicides of these metals Formed from at least one metal selected from the group of . Specifically, according to some embodiments of the present invention, the metal layer may be a Ti/TiN/Al or Ti/TiN/W layer. After forming these first electrodes 141 and second electrodes 143, a step of annealing the electrodes in a hydrogen-containing atmosphere may be performed. This hydrogen annealing can act to activate N-type dopants in the substrate, thereby improving electron mobility, and can also eliminate defects in the substrate surface, thereby reducing leakage current during operation.

Referring now to FIGS. 10A-10B and FIG. 11 , solar cells according to additional embodiments of the present invention are shown formed in a semiconductor substrate 1110 , such as a single crystal semiconductor (eg, silicon) wafer, having a first conductivity type therein. (eg P-type) base region 1111 . As highlighted in FIG. 10B and region “A” in FIG. 11 , the substrate 1110 can include a textured surface configured to enhance the light collection efficiency of the solar cell by reducing the reflection of incident light away from the upper light collection surface of the substrate 1110 . A PN rectifying junction with an uneven profile is disposed between the base region 1111 and the boundary layer 1113 of the second conductivity type (for example, N type). Boundary layer 1113 (which may have a net N-type dopant concentration therein ranging from about 1×10 ¹⁹ cm ⁻³ to about 1×10 ²¹ cm ⁻³ ) may be obtained by making A dopant of the second conductivity type (such as phosphorus (P)) is diffused and formed in the base region 1111 , such as an N+ amorphous silicon layer. The thickness of the boundary layer 1113 can be selected to increase solar cell efficiency by reducing undesired electron-hole recombination near the PN junction.

到约2000范围内的厚度的边界层1113可以通过减少其中的电子-空穴复合来支持高程度的光收集效率。While not wishing to be bound by any theory, an insufficiently thick boundary layer 1113 is associated with a relatively high degree of electron-hole recombination caused by the difference between the boundary layer 1113 and the semiconductor layer 1114 of the second conductivity type. Caused by interface defects at the junction. Alternatively, an excessively thick boundary layer 1113 would be confined by relatively high electron-hole recombination caused by excess carrier drift (i.e., migration) through the wide depletion region surrounding the PN junction cause. Based on these considerations, with a range from about 500

to about 2000 A thickness of the boundary layer 1113 in the range can support a high degree of light collection efficiency by reducing electron-hole recombination therein.

Also, by increasing the range of wavelengths that can be trapped to generate electron-hole pairs near the P-N junction, the heterojunction between the boundary layer 1113 and the semiconductor layer 1114 of the second conductivity type can be more effective with respect to the homojunction. It is beneficial to support higher light collection efficiency. FIGS. 10A-10B and FIG. 11 also show that an anti-reflection layer 1141 is included on the semiconductor layer 1114 of the second conductivity type. As explained above, the anti-reflection layer 1141 may have a thickness proportional to the wavelength of incident light. For example, the antireflective layer 1141 may have a thickness of about λ/4, where λ is a wavelength of desired light to be incident on the light collecting surface of the solar cell, in order to increase light absorption efficiency. The anti-reflection layer 1141 (the anti-reflection layer 1141 may be formed as a silicon oxide layer, a silicon nitride layer or multiple layers thereof) may also provide electrical and physical passivation and protection for the solar cell.

Trenches 1120 , which include a two-dimensional array of criss-cross trenches 1121 and 1123 and an outer annular "edge" trench 1125 , are formed in substrate 1110 . As shown in FIG. 10B (which represents a cross-sectional view of the solar cell of FIG. 10A taken along line II'), the trench 1120 extends completely through the anti-reflection layer 1141, the semiconductor layer 1114 of the second conductivity type, and the boundary layer 1113. Grooves 1121 and 1123 may have a width "W" of about 1 μm or less (eg, 0.3 μm) to reduce shadow loss of incident light, but "edge" trench 1125 may be sufficiently wide (eg, "Wa" as shown) > "W") to support low resistance contacts and wire bonds. The trenches 1121 and 1123 should be slightly deeper than the P-N rectifying junction between the boundary layer 1113 and the base region 1111 so that a sufficiently low resistance contact can be made between the trench electrodes 1131, 1131a and the base region 1111.

As best shown in FIG. 10B , the first conductivity type impurity region 1115 may be disposed at the bottom and lower sidewalls of the trench 1120 using a combination of selective implantation and dopant drive-in techniques. The impurity region 1115 typically has a net first conductivity type doping concentration therein that exceeds the first conductivity type doping concentration in the base region 1111 . Those skilled in the art should understand that the impurity region 1115 may function as a back surface field (BSF) region that enhances current collection from the base region 1111 .

10A-10B also illustrate the inclusion of a first electrode and a second electrode on the front surface (ie, the light collecting surface) of the solar cell. The first electrode 1131 , 1131 a is shown extending adjacent to the bottom of the trench 1120 and is in ohmic contact with the impurity region 1115 and/or the base region 1111 . As shown, an electrically insulating layer 1135 (eg, silicon dioxide) is disposed on the first electrodes 1131 , 1131 a within the trench 1120 , and the second electrodes 1133 , 1133 a are disposed on the electrically insulating layer 1135 . The second electrodes 1133 , 1133 a may be formed in ohmic contact with the second conductive type semiconductor layer 1114 , and may extend onto the upper surface of the anti-reflection layer 1141 . The width W2 of the second electrode 1133 may be greater than the width “W” of the trenches 1121 , 1123 . The upper surface of the electrical insulating layer 1135 is below the interface between the boundary layer 1113 and the semiconductor layer 1114 of the second conductivity type, as shown in FIG. 11 .

As shown in FIG. 10A , electrical contact can be made to the first electrode 1131a (e.g., by wire bonding) at the periphery adjacent to the edge opening 1119 of the semiconductor substrate 1110, and can be made to the second electrode 1133a (extending as an arc around the periphery). shape segment) electrical contact. In particular, arcuate openings may be formed in the second electrode 1133a and the underlying electrically insulating layer 1135 , thereby exposing the upper surface of the first electrode 1131a adjacent the bottom of the annular “edge” trench 1125 .

According to some embodiments of the present invention, the first electrodes 1131, 1131a and the second electrodes 1133, 1133a can be made of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), A material selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), and metal silicide, and combinations of these conductive materials is formed. For example, in some embodiments of the present invention, the first electrode 1131, 1131a and the second electrode 1133, 1133a may be formed as a composite of Ti/TiN/Al or Ti/TiN/W. Optionally, the first electrodes 1131, 1131a may be formed as P-type semiconductor electrodes, and the second electrodes 1133, 1133a may be formed as N-type semiconductor electrodes.

A solar cell according to a further embodiment of the present invention is shown in Figures 12A-12C. Specifically, the solar cell embodiment of FIGS. 12A-12B is similar to the solar cell embodiment of FIGS. 10A-10B , but the position of the anti-reflection layer 1141 relative to the second electrode 1133 of FIGS. 10A-10B is modified. Specifically, as shown in FIGS. 12A-12B , the anti-reflection layer 1141 may be formed as a blanket layer to cover the inner portion of the second electrode 1133 (and boundary layer 1113) relative to the peripheral edge of the substrate 1110. Optionally, FIG. 12C shows an embodiment of the present invention, which has a light-transmitting conductive layer 1137 disposed between the anti-reflection layer 1141 and the boundary layer 1113 , and the light-transmitting conductive layer 1137 is disposed on the semiconductor layer 1114 . In this embodiment, the second electrode 1133 is patterned to directly extend on the upper surface of the light-transmitting conductive layer 1137 . In this way, the light-transmitting conductive layer 1137 can serve as a low-resistance layer that facilitates the uniform spread of electric current flowing between the second electrode 1133 and the boundary layer 1113 (via the semiconductor layer 1114 of the second conductivity type, not shown). ). The light-transmitting conductive layer 1137 may be formed as an indium tin oxide (ITO) layer or a zinc oxide (ZnO) layer, however other light-transmitting materials may also be used. The surface texture of the light-transmitting conductive layer 1137 can also be relatively rough, so as to improve the light collection efficiency of the solar cell.

According to other embodiments of the present invention, the solar cell embodiment of FIGS. 10A-10C can be further modified, as shown in the solar cell embodiment of FIGS. 13A-13B . Specifically, the solar cell embodiment of FIGS. 13A-13B includes modifying the patterned second electrode 1133 such that the upper surface of the second electrode 1133 is on the same plane as the anti-reflection layer 1141 . This planar surface profile can be achieved by planarizing the second electrode 1133 so that it is coplanar with the antireflection layer 1141 . Also, an edge portion of the second electrode 1133 is provided as a ring-shaped extension 1133b. The extension 1133b defines a rounded second edge region 1119b at the periphery of the semiconductor substrate 1110, the rounded second edge region 1119b exposing the surface of the underlying first electrode 1131b. The circular second edge region 1119b has a width that is less than the width "Wa". The annular extension 1133b and the exposed surface of the underlying first electrode 1131b provide contact points for external electrodes (such as wire bonds, not shown) that supply the current generated by the sun to a load (not shown) or a photovoltaic system (see , for example Figure 26).

Methods of forming solar cells according to additional embodiments of the invention are illustrated by FIGS. 14A-20A and 14B-20B, which show cross-sectional views of the intermediate structure of FIGS. 14A-20A taken along line I-I'. Specifically, FIGS. 14A-14B show that the boundary layer 1113 is formed on the base region 1111 of the first conductivity type (such as P type) and in some embodiments the boundary layer 1113 of the second conductivity type (such as N type) is connected to the first conductivity type. A combination of a semiconductor layer 1114 of two conductivity types (such as a highly doped amorphous silicon layer, not shown) is formed on the base region 1111 of a first conductivity type (such as a P-type). The boundary layer 1113 and the semiconductor layer 1114 of the second conductivity type may be formed as described above with respect to FIGS. 10A-10B and FIG. 11 , thereby defining a P-N rectifying junction. As shown in FIG. 11 , the major surface of the semiconductor substrate 1110 may have a textured surface profile.

Referring now to FIGS. 15A-15B , an anti-reflection layer 1141 is formed on the boundary layer 1113 to increase the light collection efficiency of the solar cell. The anti-reflection layer 1141 (which may be a silicon oxide layer, a silicon nitride layer, or a combination thereof) may be formed using a process such as plasma enhanced chemical vapor deposition (PECVD). The anti-reflection layer 1141 may also be formed using a conventional anti-reflection coating (ARC) layer. 16A-16B show that a photoresist layer 1143 is deposited on the anti-reflection layer 1141 . Photoresist layer 1143 may be photolithographically patterned to define openings 1143a and 1143b therein. These openings can define a cross grid of intersecting openings, as shown in Figure 16A. Photoresist layer 1143 may also be patterned to define annular edge opening 1119 .

Referring now to FIGS. 17A-17B , a selective etch step is performed using the patterned photoresist layer 1143 as an etch mask to define the array of trenches and the annular edge trenches 1125 within the semiconductor substrate 1110 . These grooves are collectively shown as two-dimensional grid grooves 1120 . Specifically, a plurality of first grooves 1121 and a plurality of second grooves 1123 (which together form a cross array of grooves (that is, a two-dimensional grid)) are formed to completely extend through the antireflection layer 1141 and the boundary layer 1113, And further extend to the base region 1111 of the first conductivity type. According to some embodiments of the present invention, the depth of the trench may be about two thirds of the thickness of the semiconductor substrate 1110 . As described above with respect to FIG. 10B , these trenches 1121 and 1123 may have a maximum width of about 1 μm, but typically have a narrower width of, for example, about 0.3 μm.

18A-18B illustrate the formation of the first conductivity type impurity region 1115 adjacent to the bottom of the trenches 1121, 1123, and 1125. These impurity regions 1115 can be implanted into the lower sidewalls of the grid trenches 1120 by using the anti-reflection layer 1141 and/or the patterned photoresist layer 1143 as an implantation mask to inject a first conductivity type dopant (for example boron). and bottom to form. According to some embodiments of the present invention, the implantation of dopants of the first conductivity type may be performed with sufficient energy and dose to produce a region having a higher concentration of dopants of the first conductivity type relative to the base region 1111 therein. impurity region 1115 . Following this implantation step, a blanket conductive layer (not shown) may be deposited on the anti-reflection layer 1141 and in the mesh trenches 1120 . This blanket conductive layer can be made from aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal silicide And a material selected from the group consisting of combinations of these conductive materials is formed. Specifically, the blanket conductive layer may be formed as a composite of Ti/TiN/Al or Ti/TiN/W. This blanket layer is then patterned to define a first electrode 1131 adjacent the bottom of trenches 1121 , 1123 and 1125 . This patterning of the blanket layer can be done as an anisotropic etch step that acts to selectively etch back portions of the blanket layer. During the anisotropic etching step, the anti-reflection layer 1141 may serve as an etch stop layer. As shown, the first electrode 1131 may have a lower upper surface (in the mesh trench 1120 ) than the P-N junction interface between the base region 1111 and the boundary layer 1113 .

Referring also to FIGS. 18A-18B , a blanket insulating layer (not shown) may be deposited on the anti-reflection layer 1141 and in the mesh trenches 1120 . This blanket insulating layer (which may be formed from an interlayer dielectric material such as silicon dioxide) is then selectively etched back to define the insulating layer 1135 within the grid trenches 1120 . This etch back step can be performed without photolithography. For example, an anisotropic etching step may be performed using the anti-reflection layer 1141 as an etch stop layer. As shown, the top surface of the insulating layer 1135 is lower than the top surface of the boundary layer 1113 after etch back.

Referring now to FIGS. 19A-19B , another conductive layer (not shown) is conformally deposited as a blanket layer on the antireflective layer 1141 and on the insulating layer 1135 . As mentioned above, this conductive layer can be made of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN) and metal A material selected from the group consisting of silicide and combinations of these conductive materials is formed. A photoresist layer (not shown) may be deposited on the conductive layer and then patterned to define a photoresist mask 1144 . A photoresist mask 1144 is then used to define the second electrode 1133 during an etching step. The anti-reflective layer 1141 may again serve as an etch stop layer. During the process of forming the second electrode 1133, at least a portion of the edge region 1119 may be covered with a hard mask 1146 to define the second electrode 1133a adjacent to the periphery of the substrate 1110, as shown in FIG. 10A. As shown in FIG. 19B , portions of insulating layer 1135 within edge region 1119 may be exposed by photoresist mask 1144 and hard mask 1146 .

Referring now to FIGS. 20A-20B , photoresist mask 1144 and hardmask 1146 may be removed and another photoresist layer (not shown) may be formed. This photoresist layer may then be patterned (eg, using a wet etch) to define another photoresist mask 1145, which exposes the first edge region 1119a. Then, a dry etching step may be performed to selectively remove exposed portions of the insulating layer 1135 , thereby exposing a lower portion of the first electrode 1131 a extending adjacent to the periphery of the semiconductor substrate 1110 . These exposed lower portions of the first electrode 1131a may serve as contact points for external wire (eg, wire bonding) connections.

Another method embodiment of the present invention is illustrated in FIGS. 21A-23A and 21B-23B. In particular, FIGS. 21A-21B illustrate the inclusion of a light-transmissive conductive layer 1137 on the boundary layer 1113 . Thereafter, as shown in FIGS. 22A-23A , 22B-23B , 12A and 12C , an anti-reflection layer 1141 may be conformally deposited on the substrate 1110 . As shown in FIGS. 23A-23B , a patterned photoresist layer 1147 is formed on the anti-reflection layer 1141 . Then, the patterned photoresist layer 1147 is used as a mask during the step of selectively etching back the exposed portions of the anti-reflective layer 1141 and the light-transmitting conductive layer 1137, thereby exposing the periphery of the first electrode 1131a and the substrate 1110. adjacent to the corresponding lower part. The patterned photoresist layer 1147 is then removed, as shown in Figure 12C.

According to additional embodiments of the invention, the solar cell embodiments of Figures 13A-13B may be formed using the steps illustrated by Figures 24A-25A, 24B-25B. For example, a method of forming a solar cell may include a modified step of patterning the second electrode 1133 such that the upper surface of the second electrode 1133 is coplanar with the anti-reflection layer 1141 . This planar surface profile can be achieved by planarizing the second electrode 1133 to be coplanar with the anti-reflection layer 1141, as shown in Figure 24B.

An edge portion of the second electrode 1133 is provided as a ring-shaped extension 1133b. The extension 1133b (which is shown in FIG. 13B ) defines a circular second edge region 1119b (which exposes the surface of the underlying first electrode 1131b ) at the periphery of the semiconductor substrate 1110 . The circular second edge region 1119b has a width smaller than the width "Wa" in FIG. 10 . The circular second edge region 1119b may be defined by forming a patterned photoresist layer 1149 on the planarized surface of the second electrode 1133 and the antireflection layer 1141, as shown in FIGS. 25A-25B. Thereafter, as shown in FIGS. 13A-13B , the exposed portion of the second electrode 1133 and the portion of the underlying insulating layer 1135 are selectively removed so that the narrower upper surface of the first electrode 1131b may be exposed. By increasing the total contact area between the second electrodes 1133, 1133b and the boundary layer 1113, the solar cell embodiment of Figures 13A-13B potentially provides higher efficiency (relative to the solar cell embodiment of Figures 10A-10B ).

Referring now to FIG. 26 , the solar cell embodiments of the invention described above may be used in a power control network 4000 that receives power from a solar cell array 3000 . As shown, each solar cell array 3000 may be configured as a plurality of solar cell modules 2000 , each module comprising an array of solar cells 1000 . In this way, the lower voltage and/or current provided by each solar cell 1000 can be combined with voltages and/or currents provided by other solar cells 1000 to produce a relatively large power source. A power control network 4000 is shown to include an output device 4100, a power storage device 4200, a charge/discharge controller 4300, and a system controller 4400 that controls the power storage device 4200, the charge/discharge controller 4300, a power conditioning system ( PCS) 4120 and grid connection system 4140. The output device 4100 may include a power conditioning system (PCS) 4120 and a grid connection system 4140 . The PCS 4120 may be an inverter for converting direct current (DC) from the solar array 3000 to alternating current (AC). Grid connection system 4140 may be connected to external power system 5000. When the output generated by the solar cell array 3000 exceeds the power output to the external power system 5000 , the charge/discharge controller 4300 is used to transfer excess energy to the power storage device 4200 . Optionally, the charge/discharge controller 4300 is used to retrieve energy from the power storage device 4200 when the output produced by the solar array 3000 is insufficient to meet the needs of the external power system 5000 .

The above-described embodiments of the invention can be fabricated with different electrode configurations and patterns that support efficient collection of charge carriers in response to incident light received on the major surface of the solar cell. For example, FIG. 27A is a plan view of an integrated circuit solar cell 2700 according to additional embodiments of the present invention, and FIG. 27B is a cross-sectional view of the solar cell 2700 of FIG. 27A taken along line I-I'. As shown in these figures, solar cell 2700 includes a two-dimensional array of second conductivity type regions 2710 (shown as square regions), which may have N-type conductivity, surrounded by top surface electrodes 2708 . Each second conductivity type region 2710 forms a respective P-N rectifying junction with the substrate region 2702 (which may have P-type conductivity). As shown in FIG. 27B, electrical contact to the P-type substrate region 2702 can be made through the trench base electrode 2704, which is located at the bottom of the trench network. The mesh top surface electrode 2708 is electrically isolated from the underlying trench base electrode 2704 by an interposed trench base electrical insulating layer 2706 (e.g., silicon dioxide), the upper surface of the trench base electrical insulating layer 2706 may be separated from the upper surface of the substrate region 2702. The surfaces are coplanar, top surface electrode 2708 and N-type region 2710 are formed on substrate region 2702 .

28A is a plan view of an integrated circuit solar cell 2800 according to additional embodiments of the present invention, and FIG. 28B is a cross-sectional view of the solar cell 2800 of FIG. 28A taken along line II'. As shown in the plan view of FIG. 28A, solar cell 2800 is similar to solar cell 2700 of FIG. 27A, however, trench base electrode 2804 (see, e.g., FIG. . Specifically, FIG. 28B shows a P-type substrate region 2802 with a plurality of N-type regions 2810 formed thereon, and the plurality of N-type regions 2810 respectively form P-N rectifying junctions with the substrate region 2802 . Electrical contact to the N-type region 2810 is made using a plurality of top surface electrodes 2808 and electrical contact to the P-type substrate region 2802 is made through trench base electrodes 2804, which are shown extending parallel across the sides of the solar cell 2800 Strip electrodes. As further shown in FIG. 28B , trench base electrode 2804 and top surface electrode 2808 are electrically isolated from each other by electrically insulating layer 2806 , which extends adjacent the light receiving surface of solar cell 2800 . The top surface electrode 2808 is also electrically isolated from the underlying substrate region 2802 by an electrically insulating spacer 2809 disposed below the top surface electrode 2808 .

29A is a plan view of an integrated circuit solar cell 2900 according to additional embodiments of the present invention, and FIG. 29B is a cross-sectional view of the solar cell 2900 of FIG. 29A taken along line I-I'. As shown in FIGS. 29A-29B , solar cell 2900 is similar to the solar cell embodiment of FIGS. 28A-28B , however, electrically insulating layer 2906 is moved into substrate region 2902 and on the opposite side of the upper portion of trench base electrode 2904 . Top surface electrode 2908 is disposed on the upper surface of electrically insulating layer 2906, which enables N-type region 2910 in FIG. 29B to be larger than N-type region 2810 in FIG. 28B. Thus, the solar cell embodiments of FIGS. 29A-29B may have greater light collection efficiencies than the solar cell embodiments of FIGS. 28A-28B . As shown, the solar cell embodiments of FIGS. 29A-29B can also include a light transmissive insulating layer 2912 conformally deposited on the N-type region 2910 and in the space between adjacent electrodes 2908 such that the planar surface profile is adjacent The light collecting surface of the solar cell 2900 is provided.

30A is a plan view of an integrated circuit solar cell 3000 according to additional embodiments of the present invention, and FIG. 30B is a cross-sectional view of the solar cell 3000 of FIG. 30A taken along line II'. As shown in FIGS. 30A-30B , the trench base electrodes 3004 extend in parallel stripes across the light receiving surface of the solar cell 3000 . Each of these trench base electrodes 3004 is electrically connected to the substrate region 3002 and is electrically isolated from the N-type region 3010 by a respective insulating spacer 3006 . These N-type regions 3010 respectively form P-N junctions with the underlying substrate region 3002 and electrically contact the top surface electrode 3008 . Electrically insulating spacers 3009 are also disposed below the top surface electrodes 3008 to isolate these electrodes 3008 from the underlying substrate region 3002 .

31A is a plan view of an integrated circuit solar cell 3100 according to additional embodiments of the present invention, and FIG. 31B is a cross-sectional view of the solar cell 3100 of FIG. 31A taken along line II'. A solar cell 3100 is shown comprising a substrate region 3102 having thereon a two-dimensional array of square N-type regions 3110 surrounded by a mesh top surface electrode 3108 . As shown, top surface electrode 3108 is separated and isolated from substrate region 3102 by electrically insulating spacer 3109 . As shown in FIG. 31B, strip-shaped trench base electrodes 3104 are disposed adjacent to the bottom of each trench. These trench base electrodes 3104 are electrically connected to the substrate region 3102 . An electrically insulating spacer 3106 is also disposed between the trench base electrode 3104 and the N-type region 3110 . External controls to the trench base electrode 3104 can be made using wire bonds (not shown in FIGS. 31A-31B ) connected to the periphery of the substrate region 3102 (eg, a silicon wafer).

32A is a plan view of an integrated circuit solar cell 3200 according to additional embodiments of the present invention, and FIG. 32B is a cross-sectional view of the solar cell 3200 of FIG. 32A taken along line II'. A solar cell 3200 is shown comprising a substrate region 3202 having thereon a two-dimensional array of square-shaped N-type regions 3210 forming P-N junctions with the substrate region 3202, respectively. A plurality of parallel strip-shaped trench base electrodes 3208 are disposed in each trench. As shown, these trench base electrodes 3208 are electrically connected to the overlying N-type region 3210, but are electrically isolated from the surrounding substrate region 3202 by an electrically insulating liner 3209 that runs along the bottom and sidewalls of the trenches. extend. As shown, a plurality of parallel strip trench electrodes 3204 (which are electrically coupled to the substrate region 3202) are also disposed in the respective trenches. These electrodes 3204 (which extend adjacent to the light receiving surface of the solar cell 3200) are electrically isolated from the array of N-type regions 3210 by electrically insulating spacers 3206, such as oxide spacers.

Figure 33 is a plan view of an integrated circuit solar cell 3300 according to another embodiment of the present invention, which is similar to the embodiment 3100 of Figures 31A-31B. A solar cell 3300 is shown including thereon a two-dimensional array of square N-type regions 3310 surrounded by a mesh top surface electrode 3308 . Parallel strip trench base electrodes 3304 are also disposed adjacent to the bottom of each trench (not shown in FIG. 33 ). However, in contrast to the solar cell 3100 of FIGS. 31A-31B , the parallel strip trench base electrodes 3304 extend at an angle relative to the electrodes 3104 of FIGS. 31A-31B .

34A is a plan view of an integrated circuit solar cell 3400 according to additional embodiments of the present invention, FIG. 34B is a cross-sectional view taken along line II' of the solar cell embodiment of FIG. 34A , and FIG. 34C is a solar cell embodiment of FIG. 34A A cross-sectional view taken along the line II-II'. In this way, as shown in FIGS. 34B-34C , the trench base electrodes 3404 of the cross grid are buried in the P-type substrate region 3402 . The P-type substrate regions 3402 form P-N rectifying junctions with the array of square N-type regions 3410 respectively. A mesh electrode 3408 is also provided, which is electrically connected to the N-type region 3410 . Mesh electrode 3408 is electrically isolated from substrate region 3402 by electrically insulating spacers 3409, such as silicon dioxide spacers. Figure 35 is a plan view of an integrated circuit solar cell 3500 according to an additional embodiment of the invention, which is similar to the embodiment of Figures 34A-34C. As shown in the figure, trench base electrodes 3504 of inclined cross grid are embedded in the P-type substrate region, and the P-type substrate region and the array of square N-type regions 3510 respectively form P-N rectifying junctions. A mesh electrode 3508 is also provided, which is electrically connected to the N-type region 3510 .

36A is a plan view of a solar cell 3600 according to an additional embodiment of the present invention, and FIG. 36B is a cross-sectional view of the solar cell 3600 of FIG. 36A taken along line I-I'. As shown in FIGS. 36A-36B , a plurality of relatively thin strip-shaped electrodes 3608 are arranged on the light-receiving surface of the solar cell 3600 and are arranged side by side with a plurality of strip-shaped N-type regions 3610 , and the plurality of strip-shaped N-type regions 3610 P-N junctions are respectively formed with the underlying substrate region 3602 (for example, P-type). These electrodes 3608 are electrically isolated from the underlying substrate region 3602 by electrically insulating spacers 3609, such as oxide spacers. 36A-36B also show trench base electrodes 3604 extending parallel to N-type regions 3610 and strip electrodes 3608 . These electrodes 3604 (which are electrically connected to the substrate region 3602 ) are electrically isolated from adjacent N-type regions 3610 by electrically insulating spacers 3606 .

37A is a plan view of a solar cell 3700 according to an additional embodiment of the present invention, and FIG. 37B is a cross-sectional view of the solar cell 3700 of FIG. 37A taken along line I-I'. As shown in Figures 37A-37B, a plurality of relatively thin strip-shaped electrodes 3708 are arranged on the light-receiving surface of the solar cell 3700, and each electrode 3708 is sandwiched between a pair of strip-shaped N-type regions 3710, and the strip-shaped N-type regions 3710 respectively form P-N junctions with the underlying substrate region 3702 (for example, P-type). These electrodes 3708 are electrically isolated from the underlying substrate region 3702 by electrically insulating spacers 3709, such as oxide spacers. 37A-37B also show trench base electrodes 3704 extending parallel to N-type regions 3710 and strip electrodes 3708 . These electrodes 3704 (which are electrically connected to the substrate region 3702 ) are electrically isolated from adjacent N-type regions 3710 by electrically insulating spacers 3706 .

In the drawings and specification, there have been disclosed typical preferred embodiments of the present invention, and although specific terms are used, they are used in a generic and descriptive sense only and not for limitation, the scope of the present invention being defined by the appended claims book elaboration.

This invention claims U.S. Provisional Application No. 61/054,233 filed May 19, 2008, U.S. Provisional Application No. 61/058,322 filed June 3, 2008, Korean Patent filed May 13, 2008 Priority of Application No. 2008-44062 and Korean Patent Application No. 2008-49772 filed on May 28, 2008, the disclosures of which are incorporated herein by reference.

Claims (19)

1. solar cell comprises:

Substrate, have at the light on the described substrate and collect surface and the P-N rectifying junction in described substrate, described P-N rectifying junction is included in the base of first conductivity type in the described substrate and the semiconductor layer of second conductivity type that extends between described base and described light collection surface;

Groove extends through the described semiconductor layer of second conductivity type and enters the described base of first conductivity type;

First electrode, the bottom electrical of contiguous described groove is couple to the described base of first conductivity type;

Light transmission conductive layer is on the described semiconductor layer of second conductivity type; And

Second electrode is conductively coupled to the described semiconductor layer and the described light transmission conductive layer of second conductivity type.

2. solar cell as claimed in claim 1, wherein said light transmission conductive layer comprise the material of selecting from the group of being made of zinc oxide and indium tin oxide and combination thereof.

3. solar cell as claimed in claim 1, wherein said second electrode extend in the described groove and contact the sidewall of described semiconductor layer of second conductivity type and the sidewall of described light transmission conductive layer.

4. solar cell as claimed in claim 1 also is included in the anti-reflecting layer on the described light transmission conductive layer.

5. solar cell as claimed in claim 4, wherein said anti-reflecting layer cover described second electrode.

6. solar cell comprises:

Substrate, have at the light on the described substrate and collect surface and the P-N rectifying junction in described substrate, described P-N rectifying junction is included in the base of first conductivity type in the described substrate and the semiconductor layer of second conductivity type that extends between described base and described light collection surface;

Groove extends through the described semiconductor layer of second conductivity type and enters the described base of first conductivity type;

First electrode, the bottom electrical of contiguous described groove is couple to the described base of first conductivity type;

Anti-reflecting layer is collected on the surface at described light; And

Second electrode is conductively coupled to the described semiconductor layer of second conductivity type, and described second electrode has the upper surface with the coplanar planarization of upper surface of described anti-reflecting layer.

7. method that forms solar cell comprises:

The surface texturizing that makes silicon wafer has the base of first conductivity type to produce the Feng Hegu of localization in described surface in described silicon wafer;

The in-situ doped amorphous silicon layer of deposition second conductivity type on the described surface of veining, thus definition has the non-rectification heterojunction of the veining on described surface;

Be transformed into clean second conductivity type thereby be diffused into a part that makes described base the described base from described amorphous silicon layer from clean first conductivity type, in described base, form the boundary layer of second conductivity type by second type conductivity dopant with q.s;

Formation extends through described amorphous silicon layer and described boundary layer and enters groove in the described base;

Formation is conductively coupled to first electrode of described amorphous silicon layer; And

The bottom electrical that forms contiguous described groove is couple to second electrode of described base.

8. method as claimed in claim 7, wherein veining comprises that being exposed to etchant by the surface with described silicon wafer comes the described surface of etching, described etchant causes forming residue to be used as further etched localization etching mask on described surface.

9. method as claimed in claim 8, wherein veining comprises described surface is exposed to the dry ecthing agent that comprises chlorine and fluorine.

10. method as claimed in claim 7, the boundary layer that wherein in described base, forms second conductivity type comprise form have from

Arrive

Scope in the boundary layer of thickness.

11. the temperature that method as claimed in claim 10, the boundary layer that wherein forms second conductivity type in described base are included in 500 ℃ to 900 ℃ the scope is annealed to described amorphous silicon layer.

12. method as claimed in claim 10 wherein deposits in-situ doped amorphous silicon layer and comprises that deposition has from 1 * 10 ¹⁹Cm ^-3To 1 * 10 ²¹Cm ^-3The in-situ doped amorphous silicon layer of second conductivity type of the doping content in the scope.

13. method as claimed in claim 10 wherein deposits in-situ doped amorphous silicon layer and comprises the in-situ doped amorphous silicon layer that uses low-pressure chemical vapor deposition deposition techniques second conductivity type.

14. method as claimed in claim 7 wherein forms bottom deposit second electrode that second electrode is included in described groove; And wherein form first electrode and comprise that the top that is close to described groove deposits first electrode.

15. method as claimed in claim 14, wherein the electricity consumption dielectric spacer layer covers described second electrode before forming first electrode, and described electric insulation wall extends between the sidewall of described groove.

16. method as claimed in claim 14 wherein forms groove and comprises the latticed groove of formation, has the groove of a plurality of right-angled intersections of the described silicon wafer of extend past in described latticed groove.

17. method as claimed in claim 14, wherein said latticed groove comprise the outermost annular ditch groove of the periphery of contiguous described silicon wafer; And wherein after forming first electrode, carry out described first electrode of selective removal the part of described annular ditch groove and below described electric insulation wall in the part of described annular ditch groove, thereby expose described second electrode.

18. method as claimed in claim 17 also comprises a plurality of wire-bonded of the expose portion that is formed into described second electrode in the described annular ditch groove.

19. method as claimed in claim 17 wherein was injected into first type conductivity dopant described bottom of described groove before described bottom deposit second electrode of described groove.

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