CN101614789B - Test pattern generator of integrated circuit and test method thereof - Google Patents

Abstract

The invention relates to the test field of integrated circuits and discloses a low power consumption test pattern generator of an integrated circuit and a test method thereof. The low power consumption test pattern generator of the integrated circuit is based on a restructurable Johnson counter; compared with a traditional test pattern generator, the low power consumption test pattern generator can ensure that a generated test sequence can simultaneously reduce the test pattern conversion times in a space domain and a time domain, has low test pattern generation frequency in the space domain and generates different single-input changed sequences to each scan chain in the time domain, thereby greatly lowering the power consumption of a combined logic circuit part of a tested integrated circuit and the scan power consumption of the scan chain.

Description

An integrated circuit test pattern generator and its testing method

technical field

The invention relates to the field of integrated circuit testing, in particular to an integrated circuit low-power test pattern generator (Reconfigurable Johnson-Linear Feedback Shift Register TPG, RJ-LFSR type TPG for short) and a testing method thereof. The IC's low-power test pattern generator is based on a Reconfigurable Johnson Counter.

Background technique

The Test Pattern Generator (TPG) in the built-in self-test (Built-in-Self Test, BIST) structure of an integrated circuit is generally implemented by a Linear Feedback Shift Register (LFSR). . The current test method combining BIST structure and scan design can reduce test complexity and test cost. However, this test method will increase the internal node jumps of the circuit under test, thereby increasing the test power consumption. An increase in average power consumption or peak power consumption will lead to a decrease in circuit yield and circuit life, and will also form a hot-spot in the circuit, and increase the difficulty of circuit performance verification. In order to reduce power consumption, extensive research has been conducted and a series of solutions have been proposed. These solutions can be mainly divided into reducing the amount of test data and reducing the power consumption in the test mode of the circuit under test. The latter includes improving TPG and its test timing design, first-level gating, static compression and other technologies.

The Single Input Change (SIC for short) sequence has a good application prospect in reducing test power consumption. The SIC sequence can reduce the input transition to a minimum, thereby reducing the internal circuit transition activity. The disadvantage of the existing method is that the SIC sequence generator will cause an increase in hardware overhead and delay.

Contents of the invention

An object of the present invention is to provide a low-power test pattern generator for integrated circuits, based on the linear feedback shift register of reconfigurable Johnson counters, which can reduce the test power consumption of integrated circuits without increasing hardware overhead .

Another object of the present invention is to provide a test method for the low power consumption test pattern generator of the above-mentioned integrated circuit.

Technical solution 1: a low-power test pattern generator for an integrated circuit, comprising a linear feedback shift register, a linear phase shifter, a Johnson counter, and an XOR gate network; the clock frequency of the linear feedback shift register is f ₁ , generating sequence Q=[Q ₁ Q ₂ ...Q _m ], wherein m is a natural number; the output sequence S=[S ₁ S ₂ ...S _m S _m+1 ... of the linear phase shifter S _N ], which is formed by extending the sequence generated by the linear feedback shift register to N bits, where N is a natural number, and N>m. The clock frequency of the Johnson counter is f ₂ , and the generated sequence J=[J ₁ J ₂ ... J _l ], wherein l is a natural number; N>l; the XOR gate network outputs a test sequence X=[X ₁ X ₂ ...X _m X _m+1 ...X _N ], Where [X ₁ X ₂ ... X _l X _l+1 ... X _N ] is the test sequence of the combinational logic circuit part of the integrated circuit under test, [X ₁ X ₂ ... X _l ] is the test sequence of the integrated circuit under test The scan chain input sequence of the circuit; the linear feedback shift register, linear phase shifter, Johnson counter and XOR gate network satisfy the following logical relationship:

(a) S=VQ Wherein V is the transformation matrix determined according to the original polynomial of the linear feedback shift register;

$<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; J</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="J"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">J</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; J</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \&CirclePlus;</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}<span\; class="notranslate">\; ]</span>$

[X _l+1 X _l+2 ... X _N ] = [S _l+1 S _l+2 ... S _N ];

It is characterized in that,

The Johnson counter is a reconfigurable Johnson counter, and the reconfigurable Johnson counter includes 1 D flip-flops connected in series end to end, a two-input multiplexer, a two-input AND gate logic circuit, and TPG_MOD enabling The control terminal and the Init enable control terminal; the output terminal of the multiplexer is connected to the input terminal of the first D flip-flop, and its input terminal is connected to the input terminal of the lth D flip-flop respectively. The output terminal and the output terminal of the AND gate logic circuit; the Q output terminal of the first D flip-flop and the Init enable control terminal are respectively connected to the two input terminals of the AND gate logic circuit; the TPG_MOD enable control terminal controls the multiplexer The selection output of l; the Q output of l D flip-flops constitutes the generation sequence J=[J ₁ J ₂ ... J _l ] of the reconfigurable Johnson counter.

Technical scheme 2: a kind of test method of the low power consumption test pattern generator of integrated circuit, it is characterized in that, comprises the following steps:

(1) When the TPG_MOD enable control terminal is set to high level, and the Init enable control terminal is set to low level, the multiplexer gates the output terminal of the AND gate logic circuit, and the output of the reconfigurable Johnson counter is set to all zeros State, ie J=[00...0];

(2) The linear feedback shift register operates a CLK1 clock cycle with a clock frequency of f ₁ to generate a sequence Q=[Q ₁ Q ₂ ...Q _m ], and then the linear phase shifter outputs a sequence S=[S ₁ S ₂ ...S _m S _m+1 ...S _N ], where m is a natural number;

(3) The TPG_MOD enable control terminal is set to a low level, and the reconfigurable Johnson counter runs a CLK2 clock cycle with a clock frequency of f ₂ to generate a Johnson sequence J=[J ₁ J ₂ ... J _l ];

(4) Set the TPG_MOD enable control terminal to a high level, and the Init enable control terminal to a high level, and the Johnson counter can be reconfigured to form a circular shift register mode, which corresponds to the CLK2 clock cycle and runs for 21 cycles in sequence to generate 21 Johnson sequence J=[J ₁ J ₂ ...J _l ], corresponding to 2l Johnson sequences J=[J ₁ J ₂ ...J _l ], XOR gate network correspondingly outputs 2l test sequences X=[X ₁ X ₂ ... X _l X _l+1 ... X _N ];

(5) Repeat steps 3 and 4 until the fault coverage or test length meets the requirements.

Compared with the traditional test pattern generator, the low power consumption test pattern generator of the integrated circuit of the present invention can reduce the test pattern conversion times in the space domain and the time domain at the same time in the generated test sequence, and the test pattern generation frequency in the space domain is low , generate different single-input change sequences for each scan chain in the time domain, thereby greatly reducing the power consumption (average and peak value) and scan power consumption (average and peak value) of the combinatorial logic circuit part of the integrated circuit under test. At the same time, the bit width l of the reconfigurable Johnson counter or the bit width m of the seed circuit of the present invention is much smaller than the original input terminal number N of the integrated circuit under test, so the hardware overhead is small, the test length is short, and the fault coverage rate is high. Compared with the traditional pseudo-random test patterner, the amount of test data is small and the test hardware overhead is equivalent, but the test power consumption is greatly reduced, which can effectively improve the test quality and product yield rate.

Description of drawings

Fig. 1 is a schematic structural diagram of RJ-LFSR;

Figure 2 is a schematic diagram of the structure of the reconfigurable Johnson counter in the RJ-LFSR;

Figure 3 is a timing diagram when testing with RJ-LFSR;

Fig. 4 is a schematic diagram of the logic structure of the RJ-LFSR applied to an integrated circuit of 4 original inputs;

Fig. 5 is the comparison diagram of the SIC sequence generated by the seed sequence '0000' in the time direction in the logical structure shown in Fig. 4; among the figure: 1 is the seed sequence generator; 101 is the linear feedback shift register; 102 is the linear phase shifter ; 2 is a reconfigurable Johnson counter; 3 is an XOR gate network.

Detailed ways

Referring to Figure 1, RJ-LFSR mainly includes: Reconfigurable Johnson Counter (ReconfigurableJohnson Counter) 2, Linear Feedback Shift Register (LFSR) 101, Linear Phase Shifter (Linear PhaseShifter) 102 and XOR Gate Network (XOR-Network )3.

A seed sequence generator (Seed Generator) 1 is composed of a linear feedback shift register 101 and a linear phase shifter 102, and is used to generate a seed sequence. Wherein, the clock (CLK1) frequency f ₁ of the linear feedback shift register 101 generates a sequence Q=[Q ₁ Q ₂ ... Q _m ], m is a natural number; in the present invention, the output of the LFSR is allowed to be all 0 states . The linear phase shifter 102 logically expands the sequence Q=[Q ₁ Q ₂ ...Q _m ] into an N-bit output sequence S=[S ₁ S ₂ ...S _m S _m+1 ...S _N ] , that is, the seed sequence, and satisfy N>m.

For a linear phase shifter and a linear feedback shift register with an N-bit width, the following logical relationship is satisfied:

S=VQ (1)

The transformation matrix V is determined according to the primitive polynomial corresponding to the LFSR. Taking the test sequence bit width N=20 as an example, corresponding to the LFSR whose primitive polynomial is 1+x+x ¹⁵ , its sequence Q and sequence S satisfy:

S ₁ =Q ₁

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="Q"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 13</span>}}$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="S"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">S</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="Q"\; filenames="H2009100233960E00013.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="Q"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 7</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 14</span>}}$

${\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 15</span>}}$

S ₅ =Q ₂ , S ₆ =Q ₃ , S ₇ =Q ₄

S ₈ =0, S ₉ =Q ₅ , S ₁₀ =Q ₆

S ₁₆ =0

S ₁₇ =Q ₁₂ , S ₁₈ =Q ₁₃ , S ₁₉ =Q ₁₄ , S ₂₀ =Q ₁₅

Wherein Q _i (i=1, 2, 3, . . . , 15) represents the i-th output of the LFSR. The corresponding transformation matrix V can be determined according to the above logical relationship.

The clock (CLK2) frequency f ₂ of the reconfigurable Johnson counter generates a Johnson sequence J=[J ₁ J ₂ ... J _l ], where l is a natural number; the output sequence of the XOR gate network is the test pattern generation The test sequence X=[X ₁ X ₂ ... X _m X _m+1 ... X _N ] output by the device, where [X ₁ X ₂ ... X _l X _l+1 ... X _N ] is The test sequence of the combinational logic circuit part of the integrated circuit under test, [X ₁ X ₂ ... X _l ] is the scan chain input sequence of the integrated circuit under test. Among them, the linear phase shifter, the reconfigurable Johnson counter and the XOR gate network satisfy the following logical relationship:

$<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; J</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="J"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">J</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; J</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; \&CirclePlus;</span><span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span>{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; l</span>}}<span\; class="notranslate">\; ]</span>$

[Xl _{+1Xl +2} ... _XN ]＝[Sl _{+1Sl +2} ... _SN ] (2)

According to the above logical relationship, the connected circuits form a test pattern generator for integrated circuits.

In the integrated circuit self-test mode, the linear feedback shift register generates the sequence Q=[Q ₁ Q ₂ ... Q _m ] driven by the clock CLK1, and the linear phase shifter expands it into an N-bit seed sequence S= [S ₁ S ₂ ... S _m S _m+1 ... S _N ]. The l-bit reconfigurable Johnson counter generates sequence J=[J ₁ J ₂ . . . J _l ] driven by the clock CLK2. The XOR network includes l two-input XOR gates, which are used for the low-order output S=[S ₁ S ₂ ... S _l ] of the linear phase shifter and the output of the reconfigurable Johnson counter [J ₁ J ₂ .. .J _l ] to obtain the test sequence X=[X ₁ X ₂ . . . X _l X _l+1 . . . X _N ].

The test sequence is added to the original input end and the scan chain input end of the combined logic circuit part (Combinational Logic) of the integrated circuit under test according to different test modes, and then obtained from the original output end of the integrated circuit under test and the output end of the scan chain. Output response, connect the output response to the multiple-input signature register (MISR for short), and finally judge whether the circuit is working normally by the output result of MISR.

In the test-per-clock mode, the test sequence X=[X ₁ X ₂ ... X _l X _l+1 ... X _N ] is added to the combinatorial logic circuit part (Combinational Logic) of the integrated circuit under test Raw input. The bit width N of the seed sequence is equal to the original input number of the integrated circuit under test, and the bit width l of the Johnson counter can be much smaller than N. The clock CLK1 runs for one cycle, and the corresponding clock CLK2 runs for 2N cycles, and an SCI sequence with a length of 2N can be generated within one cycle of the clock CLK1. In the test-per-scan mode, the sequence [X ₁ X ₂ ...X _l ] is respectively added to the input terminals of the scan chain SC1-SCl (Scan Chain, referred to as SC). The bit width N of the seed sequence is equal to the original input number of the circuit under test, and the bit width l of the reconfigurable Johnson counter is equal to the number of scan chains.

输出端和与门逻辑电路的输出端；第l个D触发器的Q输出端和Init使能控制端连接与门逻辑电路的两个输入端；TPG_MOD使能控制端控制多路选择器的选择输出；l个D触发器的Q输出构成可重构Johnson计数器的生成序列J＝[J₁J₂...J_l]。TPG_MOD使能控制端为高电平选通与门逻辑电路的输出端，低电平选通第l个D触发器的输出端。Referring to Fig. 2, the reconfigurable Johnson counter includes l D flip-flops connected in series from end to end, a two-input multiplexer, a two-input AND gate logic circuit, and TPG_MOD enable control terminal and Init enable control terminal; The output terminal of the multiplexer is connected to the input terminal of the first D flip-flop, and its input terminals are respectively connected to the first D flip-flop

The output terminal and the output terminal of the AND gate logic circuit; the Q output terminal of the first D flip-flop and the Init enable control terminal are connected to the two input terminals of the AND gate logic circuit; the TPG_MOD enable control terminal controls the selection of the multiplexer Output; the Q output of l D flip-flops constitutes the generation sequence J=[J ₁ J ₂ ... J _l ] of the reconfigurable Johnson counter. The TPG_MOD enable control terminal is the output terminal of the high-level strobe AND gate logic circuit, and the low-level strobe of the first D flip-flop output.

In the reconfigurable Johnson counter structure, setting the TPG_MOD enable control terminal and the Init enable control terminal can initialize the reconfigurable Johnson counter and set the working mode of the circuit during the test. When TPG_MOD is high level and Init is low level, the circuit works in initialization mode, and the reconfigurable Johnson counter will be set to all zero state, that is, J=[00...0]; when TPG_MOD is low level, The reconfigurable Johnson counter works in normal mode, and the circuit working mode has nothing to do with Init. The corresponding clock CLK2 generates a Johnson sequence every time it runs a cycle; when TPG_MOD is high and Init is high, the reconfigurable Johnson counter The function of it is a circular shift register, and the corresponding clock CLK2 runs l cycle to generate l test sequences.

With reference to Fig. 3, test method of the present invention, based on the low power consumption test pattern generator of above-mentioned integrated circuit, comprises the following steps:

(1) When the TPG_MOD enable control terminal is set to a high level, and the Init enable control terminal is set to a low level, the multiplexer strobe and the output terminal of the logic circuit can be reconfigured. The output of the Johnson counter is set to an all-zero state , namely J=[00...0];

(2) The linear feedback shift register operates a CLK1 clock cycle with a clock frequency of f ₁ to generate a sequence Q=[Q ₁ Q ₂ ...Q _m ], and then the linear phase shifter outputs a sequence S=[S ₁ S ₂ ...S _l S _l+1 ...S _N ];

(3) Set the TPG_MOD enable control terminal to low level, the circuit operation mode has nothing to do with Init, the reconfigurable Johnson counter runs a CLK2 clock cycle with a clock frequency of f ₂ , and generates a Johnson sequence J=[J ₁ J ₂ ... J _l ];

(4) Set the TPG_MOD enable control terminal to a high level, and the Init enable control terminal to a high level, and the Johnson counter can be reconfigured as a circular shift register, which runs for 21 cycles in sequence corresponding to the CLK2 clock cycle, and generates 21 Johnson Sequence J=[J ₁ J ₂ ... J _l ], corresponding to 2l Johnson sequences J = [J ₁ J ₂ ... J _l ] 2l test sequences X = [X ₁ X ₂ ...X _l X _l+1 ...X _N ];

(5) Repeat step (3) and step (4), the output 2Nl test sequences X=[X ₁ X ₂ ... X _l X _l+1 ... X _N ] of the XOR gate network, in test- In per-clock mode, [X ₁ X ₂ ... X _l X _l+1 ... X _N ] is the test sequence of the combinational logic circuit part of the integrated circuit under test; in test-per-scan mode, [ X ₁ X ₂ ... X _l ] is the scan chain input sequence of the integrated circuit under test. Or repeat steps (3) and (4) until the fault coverage or test length meets the requirements.

Referring to FIG. 4 , it is a schematic diagram of a logic structure of an RJ-LFSR type TPG applied to an integrated circuit with a 4-bit width. A 1-bit linear feedback shift register (LFSR) 101 can be used to generate two 1-bit non-repetitive sequences, which are extended by the linear phase shifter 102 into a 4-bit seed sequence.

$\left[\begin{array}{c}{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\\ {\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\\ {\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}\\ {\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}\end{array}\right]\left[\begin{array}{cccc}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right]<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

According to the logical relationship between the sequence Q and the sequence S shown in (3), the linear phase shifter 102 is constructed, and the linear phase shifter 102 expands two 1-bit non-repetitive sequences '0' and '1' into two 4-bit The seed sequences '0000' and '0101'. The seed sequence S and the Johnson sequence output by the reconfigurable Johnson counter 2 are bitwise XORed in an exclusive OR gate network (XOR-Network) 3 to obtain a test sequence X.

In the test-per-clock mode, the LFSR runs for one CLK1 cycle, and the reconfigurable Johnson counter works in the normal mode, which corresponds to running six CLK2 cycles, thereby generating a SIC sequence. The SIC sequence corresponding to the seed sequence '0000' is {0000, 1000, 1100, 1110, 0110, 0010}, and the SIC sequence corresponding to the seed sequence '0101' is {0101, 1101, 1001, 1011, 0011, 0111}. The two seed sequences generated a total of 12 test sequences without repetitions.

In the test-per-scan mode, corresponding to each Johnson sequence, the reconfigurable Johnson counter works as a circular shift register to generate a SIC sequence for the scan chains SC1-SC3 in the time direction. In conjunction with Fig. 5, the SIC sequence generated by the RJ-LFSR type TPG in the time direction with the sequence '0000' as the seed is illustrated. Taking scan chain SC3 as an example, the corresponding SIC sequence is [000_001_011_111_110_100]. Adding these SIC sequences consecutively to the scan chain of the IC under test results in an average input transition density of 1/3.

For a single scan chain, the average input transition density of an l-stage reconfigurable Johnson counter can be approximated as:

$\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="l"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">l</figure-callout></span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; l</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

However, for the original input terminal of the IC under test, the average input transition density is usually 1/2l ² . From this, the average input transition density of the combinational logic circuit part is obtained as:

$\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; l</span>}}{{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; l</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; l</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

From (4) and (5), it can be concluded theoretically that RJ-LFSR can simultaneously reduce the jump density of the original input terminal of the integrated circuit under test and the input terminal of the scan chain.

In this embodiment, the linear feedback shift register (LFSR) is designed according to the original polynomial; at the same time, in order to insert all 0 graphics, a NOR gate is introduced in the feedback circuit of the linear feedback shift register (LFSR), and the input is a linear feedback The output signal of all flip-flops of the shift register (LFSR); the feedback signal of the first-stage flip-flop determined by the primitive polynomial is XORed with the output signal of the NOR gate, and the feedback signal of the LFSR inserted with all 0 graphics can be obtained. To avoid duplication among the generated test patterns, the linear phase shifter is designed according to the primitive polynomial of the specific LFSR.

The inventors applied the RJ-LFSR type TPG of the present invention to experiments on standard test collection circuits ISCAS'85 and ISCAS'89. For the ISCAS'89 test set circuit, the full-scan design is applied and the number of scan chains is designed to be 20, the corresponding LFSR primitive polynomial is 1+x+x ¹⁵ , and the linear phase shifter is implemented as follows:

S ₁ =Q ₁

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="S"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">S</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="Q"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 13</span>}}$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3"\; label="S"\; filenames="H2009100233960E00011.png,H2009100233960E00021.png"\; state="\{\{state\}\}">S</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="Q"\; filenames="H2009100233960E00013.png,H2009100233960E00021.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="Q"\; filenames="H2009100233960E00021.png,H2009100233960E00022.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 7</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 14</span>}}$

${\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 8</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 15</span>}}$

S ₅ =Q ₂ , S ₆ =Q ₃ , S ₇ =Q ₄

S ₈ =0, S ₉ =Q ₅ , S ₁₀ =Q ₆

S ₁₆ =0

S ₁₇ =Q ₁₂ , S ₁₈ =Q ₁₃ , S ₁₉ =Q ₁₄ , S ₂₀ =Q ₁₅

Wherein Q _i (i=1, 2, 3, . . . , 15) represents the i-th output of the LFSR.

The power consumption data of the RJ-LFSR type TPG and the TPG using ordinary LFSR (referred to as LFSR type TPG) obtained from the experiment are shown in Table 1 and Table 2.

Table 1 Comparison table of power consumption between RJ-LFSR type TPG and LFSR type TPG

Table 2 Comparison of total power consumption between RJ-LFSR TPG and LFSR TPG

In Tables 1 and 2: A stands for RJ-LFSR TPG, B stands for LFSR TPG, and the proportion data are all based on LFSR TPG, where ΔP _avg represents the percentage of RJ-LFSR TPG test average power consumption drop, ΔP _peak indicates the percentage of decrease in peak power consumption of the RJ-LFSR TPG test. The average power consumption of the test pattern moving in indicates the power consumption of the RJ-LFSR type TPG during the process of serially moving the test pattern into the scan chain. The average power consumption in the scan chain is reduced by 42.4%-47.2%, and the average power consumption of the combinational logic circuit is reduced by 67.8%. %-75.1%. The shift power consumption takes into account the impact of the test pattern moving in and the test response moving out on the internal node jump of the circuit under test. The RJ-LFSR type TPG can reduce the shift power consumption by 23.8%-39.0%, and the peak power consumption has a large reduction range of 24.4 %-52.3%. The total power consumption considers the power consumption of the test pattern moving in, the test response moving out and the combinational logic circuit. The RJ-LFSR TPG can reduce the average power consumption by 25.4%-41.6%, and the peak power consumption by 16.2%-39.7%. Overall, the RJ-LFSR type TPG can significantly reduce the average power consumption and peak power consumption in the scan design test.

The comparison data of fault coverage and hardware overhead of RJ-LFSR TPG and LFSR TPG are shown in Table 3.

Table 3: RJ-LFSR type TPG and LFSR type TPG fault coverage and hardware overhead comparison data table

In Table 3: A represents RJ-LFSR type TPG, B represents LFSR type TPG, and the proportion data are all based on LFSR type TPG; where SFC represents fixed fault coverage, N _p represents the sequence generated by RJ-LFSR type TPG length. For the circuits in the standard test set circuit ISCAS'85, the RJ-LFSR type TPG can reach and exceed the fixed fault coverage of the LFSR type TPG. For the circuits in the standard test set circuit ISCAS'89, the RJ-LFSR type TPG can achieve the same fixed fault coverage with the number of test patterns close to or even less than that required by the LFSR type TPG. It can be concluded that the impact of RJ-LFSR type TPG on the test length can be ignored.

两个输出端口，而可重构Johnson计数器中的D触发器被简化为仅有一个Q输出端口，这样可以降低RJ-LFSR型TPG的硬件开销。RJ-LFSR型TPG硬件开销用其相对于标准测试集电路面积的百分比来表示。对于标准测试集电路ISCAS’85中的电路，硬件开销变化较大：RJ-LFSR型TPG硬件开销在7.2％-98.0％的范围内变化，而LFSR型TPG的硬件开销在13.6％-183.6％之间。对于标准测试集电路ISCAS’89中的电路，硬件开销变化较小：RJ-LFSR型TPG硬件开销在1.1％-6.8％的范围内变化，而LFSR型TPG的硬件开销在0.7％-15.0％之间。In the experiment, the D flip-flop in the LFSR type TPG contains Q and

Two output ports, while the D flip-flop in the reconfigurable Johnson counter is simplified to only one Q output port, which can reduce the hardware overhead of the RJ-LFSR type TPG. The RJ-LFSR type TPG hardware overhead is expressed as a percentage relative to the standard test set circuit area. For the circuits in the standard test set ISCAS'85, the hardware overhead varies greatly: RJ-LFSR type TPG hardware overhead varies in the range of 7.2%-98.0%, while LFSR type TPG hardware overhead varies between 13.6%-183.6% between. For the circuits in the standard test set ISCAS'89, the hardware overhead varies less: RJ-LFSR-type TPG hardware overhead varies in the range of 1.1%-6.8%, while LFSR-type TPG's hardware overhead varies between 0.7%-15.0% between.

The experimental results show that the test sequence generated by the RJ-LFSR TPG can effectively reduce the power consumption of the test pattern moving and the power consumption of the combinational logic, and it basically has no effect on the test length and hardware overhead.

Claims (2)

1. the low-power consumption test graph builder of an integrated circuit comprises linear feedback shift register, linear phase shifter, Johnson counter, XOR gate network; The clock frequency of said linear feedback shift register is f ₁, formation sequence Q=[Q ₁Q ₂... Q _m], wherein m is a natural number; Output sequence S=[the S of said linear phase shifter ₁S ₂... S _mS _M+1... S _N], it is that the sequence extension that linear feedback shift register generates is formed for the N position, and wherein N is a natural number, and N＞m, and the clock frequency of said Johnson counter is f ₂, its formation sequence J=[J ₁J ₂... J _l], wherein l is a natural number; N＞l; Said XOR gate network output cycle tests X=[X ₁X ₂... X _mX _M+1... X _N], [X wherein ₁X ₂... X _lX _L+1... X _N] be the cycle tests of the combinational logic circuit part of tested integrated circuit, [X ₁X ₂... X _l] be the scan chain list entries of tested integrated circuit; Said linear feedback shift register, linear phase shifter, Johnson counter and XOR gate network satisfy following logical relation:

(a) S=VQ wherein V be the transformation matrix of confirming according to the primitive polynomial of linear feedback shift register;

$\left(b\right),[X_1{X}_2...X_l]=[J_1{J}_2...J_l]\&CirclePlus;[S_1{S}_2...S_l]$

[X _l+1X _l+2...X _N]＝[X _l+1S _l+2...S _N]；

It is characterized in that,

Said Johnson counter is a restructural Johnson counter; Said restructural Johnson counter comprises l d type flip flop of head and the tail serial connection successively; One two input MUX, one two input AND, and TPG_MOD enables control end and Init enables control end; The input end of first d type flip flop of output terminal connection of MUX, its input end connect l d type flip flop respectively

The output terminal of output terminal and AND; The Q output terminal of l d type flip flop and Init enable two input ends that control end is connected respectively to AND; TPG_MOD enables the selection output of control end control MUX; The Q output of l d type flip flop constitutes the formation sequence J=[J of restructural Johnson counter ₁J ₂... J _l].

2. the method for testing of the low-power consumption test graph builder of a kind of integrated circuit according to claim 1 is characterized in that, may further comprise the steps:

(1) TPG_MOD is enabled control end and be changed to high level, Init enables control end when being changed to low level, the output terminal of MUX gating AND, and the output of restructural Johnson counter is set to all-zero state, i.e. J=[00...0];

(2) clock frequency of linear feedback shift register operation is f ₁The CLK1 clock period, formation sequence Q=[Q ₁Q ₂... Q _m], and then linear phase shifter output sequence S=[S ₁S ₂... S _mS _M+1... S _N], wherein m is a natural number;

(3) TPG_MOD enables control end and is set to low level, and clock frequency of restructural Johnson counter operation is f ₂The CLK2 clock period, generate a Johnson sequence J=[J ₁J ₂... J _l];

(4) TPG_MOD enables control end and is set to high level, and Init enables control end and is set to high level, restructural Johnson counter looping shift register mode, and the corresponding CLK2 clock period is moved the 2l cycle successively, produces 2l Johnson sequence J=[J ₁J ₂... J _l], corresponding 2l Johnson sequence J=[J ₁J ₂... J _l], the XOR gate network is correspondingly exported 2l cycle tests X=[X ₁X ₂... X _lX _L+1... X _N];

(5) repeating step 3 and step 4 meet the demands until fault coverage or testing length.

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