CN101609345A - Linear voltage regulator - Google Patents

Abstract

The invention relates to a linear voltage regulator and belongs to the field of electronic technology. The linear voltage regulator includes: an error amplifier, which is composed of a one-stage folded cascode amplifier, used to compare the reference voltage Vref and the feedback voltage of the node NETF, and generate a first output voltage; an output amplifier circuit, which includes a power A PMOS tube and a voltage dividing resistor, the power PMOS tube generates a second output voltage Vout under the action of the first output voltage, and the voltage dividing resistor generates the feedback voltage; a frequency compensation circuit, which includes a voltage-controlled current source and a compensation capacitor, It is used for receiving the feedback voltage and the second output voltage Vout and generating a zero point matched with a pole of the output amplifier circuit. The invention reduces the complexity of the linear voltage regulator, reduces the number of capacitors required for frequency compensation, and the value of the compensation capacitor is small, so that the linear voltage regulator is suitable for full-chip integration.

Description

A Linear Voltage Regulator

technical field

The invention relates to the field of electronic technology, in particular to a linear voltage regulator.

Background technique

Linear voltage regulators are widely used in the power supply of portable electronic devices. The structure of conventional linear voltage regulators is shown in Figure 1. Its core circuit is composed of error amplifier, output amplifier circuit and frequency compensation circuit. The frequency compensation circuit consists of a chip It is composed of external compensation capacitor Cp and series resistor R _ESR . The working principle of the linear voltage regulator shown in Figure 1 is: if the load RL changes to reduce the output voltage Vout, the output voltage Vout is divided by the resistors R1 and R2 and the voltage fed back to the positive terminal of the error amplifier is also reduced, because the reference voltage Vref remains unchanged, so the output voltage of the error amplifier decreases, so the current through the power P-channel metal oxide semiconductor (P-Channel Metal Oxide Semiconductor, PMOS) MP increases, so that Vout increases, the circuit restores balance, and the output The voltage is stable; on the contrary, if the output voltage Vout increases, the voltage fed back to the positive terminal of the error amplifier increases, and the output voltage of the error amplifier increases, so the current through the power PMOS transistor MP decreases, thereby reducing Vout, and the circuit restores balance .

In the linear voltage regulator shown in Figure 1, the frequency compensating capacitor Cp and the series resistor R _ESR produce a zero whose frequency is given by:

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; ESR</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

This zero is used to cancel out the poles of the circuit, giving the voltage regulator enough phase margin to keep the circuit stable.

The circuit shown in Figure 2 is a two-stage amplifier structure commonly used by error amplifiers. If this structure is adopted, the linear voltage regulator has a three-stage amplifier structure. In order to maintain the stability of the circuit, the number of compensation capacitors usually needs to be more than three. One, the compensation circuit is more complex. In addition, the value of the compensation capacitor Cp is usually at the μF level, which cannot be integrated on-chip.

With the continuous increase of system on chip (system on chip, SoC) scale and the rapid development of portable devices, linear voltage regulators that can be integrated on a chip have attracted more and more attention. However, conventional linear voltage regulators cannot be fully integrated due to the aforementioned disadvantages, and thus cannot adapt to the increase in the scale of SoCs and the development of portable devices.

Contents of the invention

In order to solve the technical problem that the structure of the error amplifier in the existing linear voltage regulator is complex and the linear voltage regulator cannot be fully integrated, the present invention provides a linear voltage regulator that does not need an off-chip compensation capacitor. Without degrading circuit performance, the structure of the linear voltage regulator is simplified, thereby simplifying the compensation circuit, reducing the number of compensation capacitors, reducing the value of the compensation capacitor, and making the linear voltage regulator suitable for full-chip integration.

The present invention provides a linear voltage regulator, including:

An error amplifier, which is composed of a one-stage folded cascode amplifier, is used to compare the reference voltage Vref and the feedback voltage of the node NETF, and generate a first output voltage;

An output amplification circuit, which includes a power PMOS transistor and a voltage dividing resistor, the power PMOS transistor generates a second output voltage Vout under the action of the first output voltage, and the voltage dividing resistor generates a second output voltage Vout according to the second output voltage Vout said feedback voltage;

A frequency compensation circuit, which includes a voltage-controlled current source and a compensation capacitor, is used to receive the feedback voltage and the second output voltage Vout, and generate a zero point that matches the pole of the output amplifier circuit.

The error amplifier includes:

The gate of the first PMOS transistor Mp1 is connected to the first bias voltage Vb1, and the source is connected to the power supply voltage VDD;

The source of the second PMOS transistor Mp2 is connected to the drain of the first PMOS transistor Mp1, and the gate is connected to the node NETF;

The source of the third PMOS transistor Mp3 is connected to the drain of the first PMOS transistor Mp1, and the gate is connected to the reference voltage Vref;

The source of the fourth PMOS transistor Mp4 is connected to the power supply voltage VDD;

The source of the fifth PMOS transistor Mp5 is connected to the power supply voltage VDD;

The sixth PMOS transistor Mp6 has its source connected to the drain of the fourth PMOS transistor Mp4, its gate connected to the fourth bias voltage Vb4, and its drain connected to the gate of the fourth PMOS transistor Mp4 respectively. The pole is connected to the gate of the fifth PMOS transistor Mp5;

The source of the seventh PMOS transistor Mp7 is connected to the drain of the fifth PMOS transistor Mp5, and the gate is connected to the fourth bias voltage Vb4;

The source of the first NMOS transistor Mn1 is grounded, the gate is connected to the second bias voltage Vb2, and the drain is connected to the drain of the second PMOS transistor Mp2;

The source of the second NMOS transistor Mn2 is grounded, the gate thereof is connected to the second bias voltage Vb2, and the drain thereof is connected to the drain of the third PMOS transistor Mp3;

The third NMOS transistor Mn3 has its source connected to the drain of the first NMOS transistor Mn1, its gate connected to the third bias voltage Vb3, and its drain connected to the drain of the sixth PMOS transistor Mp6. connect;

The fourth NMOS transistor Mn4 has its source connected to the drain of the second NMOS transistor Mn2, its gate connected to the third bias voltage Vb3, and its drain connected to the seventh PMOS transistor Mp7. The drain is connected;

The drain of the seventh PMOS transistor Mp7 is connected to the drain of the fourth NMOS transistor Mn4 to generate a first output voltage of the error amplifier for controlling the output amplifier circuit.

The output amplifier circuit includes:

The eighth PMOS transistor Mp8 has its source connected to the power supply voltage VDD, its gate receiving the first output voltage, and its drain providing the second output voltage Vout;

a first capacitor C1, one end of which is connected to the second output voltage Vout, and the other end is grounded;

A first resistor R1, one end of which is connected to the second output voltage Vout, and the other end is connected to the gate of the second PMOS transistor Mp2;

A second resistor R2, one end of which is connected to the first resistor R1, and the other end is grounded;

The first resistor R1 and the second resistor R2 are connected to form a feedback node NETF, which is fed back to the gate of the second PMOS transistor Mp2.

The frequency compensation circuit includes:

The fifth NMOS transistor Mn5, the gate of which is connected to the second bias voltage Vb2, and the source of which is grounded;

The sixth NMOS transistor Mn6, the gate of which is connected to the second bias voltage Vb2, and the source of which is grounded;

A seventh NMOS transistor Mn7, the gate of which is connected to the third bias voltage Vb3, and the source of which is connected to the drain of the fifth NMOS transistor Mn5;

An eighth NMOS transistor Mn8, the gate of which is connected to the third bias voltage Vb3, and the source of which is connected to the drain of the sixth NMOS transistor Mn6;

The ninth NMOS transistor Mn9, the gate of which is connected to the second output voltage Vout, and the source of which is connected to the drain of the eighth NMOS transistor Mn8;

The second capacitor C2, one end of which is connected to the drain of the eighth NMOS transistor Mn8, and the other end is grounded;

The gate of the ninth PMOS transistor Mp9 is connected to the fourth bias voltage Vb4, and the drain is connected to the drain of the seventh NMOS transistor Mn7;

The tenth PMOS transistor Mp10, the gate of which is connected to the fourth bias voltage Vb4, and the drain of which is connected to the drain of the ninth NMOS transistor Mn9;

The eleventh PMOS transistor Mp11 has its gate connected to the drain of the tenth PMOS transistor Mp10, its drain connected to the source of the ninth PMOS transistor Mp9, and its source connected to the power supply voltage VDD. connect;

The gate of the twelfth PMOS transistor Mp12 is connected to the drain of the tenth PMOS transistor Mp10, the drain is connected to the source of the tenth PMOS transistor Mp10, and the source is connected to the power supply voltage VDD connected.

The first bias voltage Vb1 makes the first PMOS transistor Mp1 located in a saturation region; the second bias voltage Vb2 makes the first NMOS transistor Mn1, the second NMOS transistor Mn2, and the fifth NMOS transistor Mn2 The transistor Mn5 and the sixth NMOS transistor Mn6 are located in the saturation region; the third bias voltage Vb3 makes the third NMOS transistor Mn3, the fourth NMOS transistor Mn4, the seventh NMOS transistor Mn7 and the sixth NMOS transistor Mn7 The eight NMOS transistors Mn8 are in the saturation region; the fourth bias voltage Vb4 makes the sixth PMOS transistor Mp6, the seventh PMOS transistor Mp7, the ninth PMOS transistor Mp9, and the tenth PMOS transistor Mp10 in a saturated region district.

The invention has the following beneficial effects: the invention reduces the complexity of the linear voltage regulator, reduces the number of capacitors required for frequency compensation, and the value of the compensation capacitor is small, making the linear voltage regulator suitable for full-chip integration.

Description of drawings

Fig. 1 is a schematic structural diagram of a conventional linear voltage regulator in the prior art;

FIG. 2 is a structural schematic diagram of an error amplifier in a conventional linear voltage regulator in the prior art;

3 is a schematic circuit diagram of a linear voltage regulator without an off-chip compensation capacitor provided by the present invention;

Fig. 4 is the equivalent small signal load of the output node when there is no frequency compensation circuit in the present invention;

Fig. 5 is the equivalent small signal load of the output node when the present invention has the frequency compensation circuit;

Fig. 6 is a schematic diagram of the loop gain of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings.

The circuit schematic diagram of the linear voltage regulator without off-chip compensation capacitor provided by the present invention is shown in FIG. 3 , which includes an error amplifier, an output amplifier circuit and a frequency compensation circuit.

An error amplifier, which is composed of a one-stage folded cascode amplifier, is used to compare the reference voltage Vref and the feedback voltage of the node NETF to generate a control voltage;

The output amplifying circuit includes a power PMOS transistor and two voltage dividing resistors, the power PMOS transistor generates the output voltage Vout under the action of the control voltage, and the two voltage dividing resistors generate the feedback voltage. The output node has a capacitor that can be integrated on-chip, which is used to improve the transient response characteristics of the linear voltage regulator of the present invention;

The frequency compensation circuit, which includes a voltage-controlled current source and a compensation capacitor, generates a zero point to make the circuit work stably.

Where the error amplifier includes:

The gate of the first PMOS transistor Mp1 is connected to the bias voltage Vb1, and the source is connected to the power supply voltage VDD;

The source of the second PMOS transistor Mp2 is connected to the drain of the first PMOS transistor Mp1;

The source of the third PMOS transistor Mp3 is connected to the drain of the first PMOS transistor Mp1, and the gate is connected to the reference voltage Vref;

The source of the fourth PMOS transistor Mp4 is connected to the power supply voltage VDD;

The source of the fifth PMOS transistor Mp5 is connected to the power supply voltage VDD;

The sixth PMOS transistor Mp6 has its source connected to the drain of the fourth PMOS transistor Mp4, its gate connected to the bias voltage Vb4, and its drain connected to the gate of the fourth PMOS transistor Mp4 and the fourth PMOS transistor Mp4. The gates of the five PMOS transistors Mp5 are connected;

The source of the seventh PMOS transistor Mp7 is connected to the drain of the fifth PMOS transistor Mp5, and the gate is connected to the bias voltage Vb4;

The first N-channel Metal Oxide Semiconductor (N-Channel Metal Oxide Semiconductor, NMOS) transistor Mn1, its source is grounded, the gate is connected to the bias voltage Vb2, and the drain is connected to the drain of the second PMOS transistor Mp2 connected;

The source of the second NMOS transistor Mn2 is grounded, the gate is connected to the bias voltage Vb2, and the drain is connected to the drain of the third PMOS transistor Mp3;

The source of the third NMOS transistor Mn3 is connected to the drain of the first NMOS transistor Mn1, the gate is connected to the bias voltage Vb3, and the drain is connected to the drain of the sixth PMOS transistor Mp6;

The source of the fourth NMOS transistor Mn4 is connected to the drain of the second NMOS transistor Mn2, the gate is connected to the bias voltage Vb3, and the drain is connected to the drain of the seventh PMOS transistor Mp7;

The drain of the seventh PMOS transistor Mp7 is connected to the drain of the fourth NMOS transistor Mn4 to generate the output voltage of the error amplifier.

The output amplifier circuit includes:

The source of the eighth PMOS transistor Mp8 is connected to the power supply voltage VDD, the gate is connected to the output voltage of the error amplifier, and the drain provides the output voltage Vout;

a first capacitor C1, one end of which is connected to the output voltage Vout, and the other end is grounded;

A first resistor R1, one end of which is connected to the output voltage Vout, and the other end is connected to the gate of the second PMOS transistor Mp2;

A second resistor R2, one end of which is connected to the first resistor R1, and the other end is grounded;

The first resistor R1 and the second resistor R2 are connected to form a feedback node NETF, which is fed back to the gate of the second PMOS transistor Mp2;

The frequency compensation circuit includes:

The fifth NMOS transistor Mn5, the gate of which is connected to the bias voltage Vb2, and the source of which is grounded;

The sixth NMOS transistor Mn6, the gate of which is connected to the bias voltage Vb2, and the source of which is grounded;

The gate of the seventh NMOS transistor Mn7 is connected to the bias voltage Vb3, and the source is connected to the drain of the fifth NMOS transistor Mn5;

The gate of the eighth NMOS transistor Mn8 is connected to the bias voltage Vb3, and the source is connected to the drain of the sixth NMOS transistor Mn6;

The ninth NMOS transistor Mn9 has its gate connected to the output voltage Vout, and its source connected to the drain of the eighth NMOS transistor Mn8;

The second capacitor C2, one end of which is connected to the drain of the eighth NMOS transistor Mn8, and the other end is grounded;

The gate of the ninth PMOS transistor Mp9 is connected to the bias voltage Vb4, and the drain is connected to the drain of the seventh NMOS transistor Mn7;

The gate of the tenth PMOS transistor Mp10 is connected to the bias voltage Vb4, and the drain is connected to the drain of the ninth NMOS transistor Mn9;

The eleventh PMOS transistor Mp11, the gate of which is connected to the drain of the tenth PMOS transistor Mp10, the drain is connected to the source of the ninth PMOS transistor Mp9, and the source is connected to the power supply voltage VDD;

The gate of the twelfth PMOS transistor Mp12 is connected to the drain of the tenth PMOS transistor Mp10, the drain is connected to the source of the tenth PMOS transistor Mp10, and the source is connected to the power supply voltage VDD.

The values of the bias voltages Vb1, Vb2, Vb3 and Vb4 should ensure that the MOS transistors in the present invention are in the saturation region.

Different from the conventional linear voltage regulator shown in Figure 1, the error amplifier of the linear voltage regulator provided by the present invention is a one-stage folded cascode amplifier, so that the linear voltage regulator of the present invention has a two-stage amplifier structure, which can Reduce the complexity of the frequency compensation circuit; the frequency compensation circuit of the linear voltage regulator provided by the present invention adopts a voltage-controlled current source structure, and the value of the required compensation capacitor is small, which is very suitable for full-chip integration.

The impact of the frequency compensation circuit of the present invention on the loop characteristics is analyzed below. The linear voltage regulator provided by the present invention does not need an off-chip compensation capacitor. When the frequency compensation circuit is removed, the small-signal equivalent load of the output node Vout can be simplified as shown in FIG. The resistor-capacitor network shown in 4, where rds is the small-signal resistor of the power PMOS tube, then the pole frequency at the Vout node is:

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; po</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; RL</span>}<span\; class="notranslate">\; /</span><span\; class="notranslate">\; /</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ]</span><span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

When the frequency compensation circuit of the present invention is adopted, since it is a voltage-controlled current source structure, the small-signal equivalent load of the output node Vout can be simplified as the network shown in Figure 5, wherein the size of the voltage-controlled current i is:

i=S*C2*Vout (3)

In the formula, C2 is the capacitance in the frequency compensation circuit, and S=jw is the complex frequency. Can obtain according to the network shown in Figure 5, after adopting the frequency compensation circuit of the present invention, produce a zero point, its frequency is:

$\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="f"\; filenames="A2009103042120017H1.png"\; state="\{\{state\}\}">f</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;R</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

This zero is used to cancel out one pole of the circuit, making the circuit stable.

The value of the capacitor Cp in Fig. 1 is usually in the μF level, which cannot be integrated on the chip. In the present invention, the value of the capacitor C1 is generally 30pF to 50pF, and the value of the capacitor C2 is less than 1pF, so both C1 and C2 can be integrated on the chip.

In addition, the error amplifier in the present invention adopts a one-stage folded cascode amplifier structure, which can ensure the accuracy of the linear voltage regulator while simplifying the frequency compensation circuit. Figure 6 shows the loop gain of the present invention, and it can be seen that the The loop gain of the invention is very high, thus ensuring the high precision of the linear voltage regulator provided by the invention.

The error amplifier in the present invention adopts a one-stage folded cascode amplifier, so that the linear voltage regulator described in the present invention has a two-stage amplifier structure, which is conducive to reducing the number of capacitors required for frequency compensation and simplifying the complexity of the compensation circuit; The compensation circuit in the invention adopts a voltage-controlled current source structure, and only one compensation capacitor is needed, and the capacitance value is small, which is very suitable for full-chip integration; the error amplifier in the invention uses a one-stage folded cascode amplifier, so that the voltage adjustment proposed by the invention The device has very good power supply rejection ratio characteristics.

Various modifications can be made to the above contents by those skilled in the art without departing from the spirit and scope of the present invention defined by the claims. Therefore, the scope of the present invention is not limited to the above description, but is determined by the scope of the claims.

Claims (5)

1. A linear voltage regulator, characterized in that, comprising: an error amplifier, which is composed of a one-stage folded cascode amplifier, and is used for comparing a reference voltage (Vref) and a feedback voltage of a node (NETF), and generating a first output voltage; An output amplifying circuit, which includes a power PMOS transistor and a voltage dividing resistor, the power PMOS transistor generates a second output voltage (Vout) under the action of the first output voltage, and the voltage dividing resistor generates a second output voltage (Vout) according to the second output voltage (Vout) generates the feedback voltage; A frequency compensation circuit, which includes a voltage-controlled current source and a compensation capacitor, is used to receive the feedback voltage and the second output voltage (Vout), and generate a zero point that matches the pole of the output amplifier circuit. 2. The linear voltage regulator according to claim 1, wherein the error amplifier comprises: The first PMOS transistor (Mp1), the gate of which is connected to the first bias voltage (Vb1), and the source is connected to the power supply voltage (VDD); A second PMOS transistor (Mp2), its source connected to the drain of the first PMOS transistor (Mp1), and its gate connected to the node (NETF); The third PMOS transistor (Mp3), its source is connected to the drain of the first PMOS transistor (Mp1), and its gate is connected to the reference voltage (Vref); A fourth PMOS transistor (Mp4), the source of which is connected to the power supply voltage (VDD); The fifth PMOS transistor (Mp5), the source of which is connected to the power supply voltage (VDD); The sixth PMOS transistor (Mp6), its source is connected to the drain of the fourth PMOS transistor (Mp4), its gate is connected to the fourth bias voltage (Vb4), and its drain is respectively connected to the fourth PMOS transistor (Mp4). The gates of the four PMOS transistors (Mp4) are connected to the grid gates of the fifth PMOS transistors (Mp5); A seventh PMOS transistor (Mp7), its source connected to the drain of the fifth PMOS transistor (Mp5), and its gate connected to the fourth bias voltage (Vb4); The first NMOS transistor (Mn1), its source is grounded, its gate is connected to the second bias voltage (Vb2), and its drain is connected to the drain of the second PMOS transistor (Mp2); The second NMOS transistor (Mn2), its source is grounded, its gate is connected to the second bias voltage (Vb2), and its drain is connected to the drain of the third PMOS transistor (Mp3); The third NMOS transistor (Mn3), its source is connected to the drain of the first NMOS transistor (Mn1), its gate is connected to the third bias voltage (Vb3), its drain is connected to the sixth PMOS The drain of the tube (Mp6) is connected; A fourth NMOS transistor (Mn4), its source connected to the drain of the second NMOS transistor (Mn2), its gate connected to the third bias voltage (Vb3), its drain connected to the The drains of the seventh PMOS transistor (Mp7) are connected; The drain of the seventh PMOS transistor (Mp7) is connected to the drain of the fourth NMOS transistor (Mn4), and generates a first output voltage of the error amplifier for controlling the output amplifier circuit. 3. The linear voltage regulator according to claim 2, wherein the output amplifier circuit comprises: An eighth PMOS transistor (Mp8), the source of which is connected to the power supply voltage (VDD), the gate of which receives the first output voltage, and the drain of which provides the second output voltage (Vout); a first capacitor (C1), one end of which is connected to the second output voltage (Vout), and the other end is grounded; A first resistor (R1), one end of which is connected to the second output voltage (Vout), and the other end is connected to the gate of the second PMOS transistor (Mp2); A second resistor (R2), one end of which is connected to the first resistor (R1), and the other end is grounded; The first resistor (R1) is connected to the second resistor (R2) to form a feedback node (NETF), which is fed back to the gate of the second PMOS transistor (Mp2). 4. The linear voltage regulator according to claim 3, wherein the frequency compensation circuit comprises: A fifth NMOS transistor (Mn5), the grid of which is connected to the second bias voltage (Vb2), and the source of which is grounded; A sixth NMOS transistor (Mn6), the gate of which is connected to the second bias voltage (Vb2), and the source of which is grounded; a seventh NMOS transistor (Mn7), the gate of which is connected to the third bias voltage (Vb3), and the source of which is connected to the drain of the fifth NMOS transistor (Mn5); An eighth NMOS transistor (Mn8), the gate of which is connected to the third bias voltage (Vb3), and the source of which is connected to the drain of the sixth NMOS transistor (Mn6); A ninth NMOS transistor (Mn9), the gate of which is connected to the second output voltage (Vout), and the source of which is connected to the drain of the eighth NMOS transistor (Mn8); A second capacitor (C2), one end of which is connected to the drain of the eighth NMOS transistor (Mn8), and the other end is grounded; The ninth PMOS transistor (Mp9), its gate connected to the fourth bias voltage (Vb4), and its drain connected to the drain of the seventh NMOS transistor (Mn7); a tenth PMOS transistor (Mp10), its gate connected to the fourth bias voltage (Vb4), and its drain connected to the drain of the ninth NMOS transistor (Mn9); The eleventh PMOS transistor (Mp11), its gate is connected to the drain of the tenth PMOS transistor (Mp10), the drain is connected to the source of the ninth PMOS transistor (Mp9), and its source is connected to the source of the ninth PMOS transistor (Mp9). the power supply voltage (VDD) is connected; The twelfth PMOS transistor (Mp12), its gate is connected to the drain of the tenth PMOS transistor (Mp10), its drain is connected to the source of the tenth PMOS transistor (Mp10), and its source Connect to the supply voltage (VDD). 5. The linear voltage regulator according to claim 4, characterized in that, the first bias voltage (Vb1) makes the first PMOS transistor (Mp1) in a saturation region; the second bias voltage ( Vb2) make the first NMOS transistor (Mn1), the second NMOS transistor (Mn2), the fifth NMOS transistor (Mn5) and the sixth NMOS transistor (Mn6) be located in the saturation region; the third The bias voltage (Vb3) makes the third NMOS transistor (Mn3), the fourth NMOS transistor (Mn4), the seventh NMOS transistor (Mn7) and the eighth NMOS transistor (Mn8) be located in a saturation region; The fourth bias voltage (Vb4) makes the sixth PMOS transistor (Mp6), the seventh PMOS transistor (Mp7), the ninth PMOS transistor (Mp9) and the tenth PMOS transistor (Mp10) in the saturation region.

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