CN101599461A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

The semiconductor storage device (10) of the present invention has: a semiconductor substrate (13); a first impurity region (17); a second impurity region (15); a channel region (75), formed in the first impurity region (17) ) and the second impurity region (15)); the first gate (42), formed on the main surface of the semiconductor substrate (13) where the channel region (75) is located, on the side of the first impurity region (17) On the main surface of the semiconductor substrate (13) where the channel region (75) is located, the second gate (45) is formed on the main surface of the semiconductor substrate (13) where the channel region (75) is located, on the second impurity region side (15 ) on the main surface; the third insulating film (46), located on the main surface of the semiconductor substrate on the opposite side of the second gate (45) relative to the first gate (42) , and formed on the side of the first gate (42); compared with the interface between the second insulating film (44) and the main surface of the semiconductor substrate directly below it, the third insulating film (46) and The interface of the main surface of the semiconductor substrate located directly below it is located above. Thereby, the total number of steps can be reduced, and the cost can be reduced.

Description

Semiconductor memory device and manufacturing method thereof

This application is a divisional application of the following application, application number: 200610067668.3, title of invention: semiconductor memory device and manufacturing method thereof, application date: March 23, 2006.

technical field

The present invention relates to a semiconductor memory device and a manufacturing method thereof.

Background technique

Generally, a well-known semiconductor integrated circuit device (semiconductor memory device) has a memory cell region in which a plurality of memory cell transistors are formed and a peripheral circuit region in which a plurality of peripheral circuit transistors are formed (see JP-A-2004-228571). For example, Japanese Unexamined Patent Publication No. 2003-309193 describes a semiconductor integrated circuit device having a memory cell transistor and its access circuit on a semiconductor substrate.

This semiconductor integrated circuit device has a memory cell region and a peripheral region on a main surface of a semiconductor substrate, and a plurality of memory cell transistors are formed on the memory cell region. In addition, peripheral circuit transistors such as power supply voltage system MOS transistors and high withstand voltage NMOS transistors are formed in the peripheral region. In manufacturing a semiconductor integrated circuit device configured in this way, peripheral circuit transistors are formed after memory cell transistors are formed. Thus, in the conventional method of manufacturing a semiconductor peripheral circuit device, the steps of forming memory cell transistors and peripheral circuit transistors are two completely different steps.

However, in the method of manufacturing a semiconductor integrated circuit device described in Japanese Unexamined Patent Application Publication No. 2003-309193, since the step of forming memory cell transistors and the step of forming peripheral circuit transistors are two completely different steps, the total number of steps is long. , The problem of high cost.

Contents of the invention

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the total number of steps of a semiconductor integrated circuit device (semiconductor memory device) and reduce the cost.

The method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a semiconductor memory device including: a memory cell region in which a memory cell transistor is formed; and a peripheral circuit in which a peripheral circuit for controlling the operation of the memory cell transistor is formed. The region, wherein, has the following steps: forming a first insulating film on the main surface of the semiconductor substrate; forming a first conductive film on the first insulating film; patterning the first conductive film to form a conductive pattern, the conductive pattern is Form a pattern in which the source region of the memory cell transistor is opened; use the first conductive pattern as a mask to form the source region of the memory cell transistor; form a second insulating film to cover the conductive pattern; form on the second insulating film The second conductive film; etching the second insulating film and the second conductive film to form the memory gate of the memory cell transistor; patterning the conductive pattern to form the gate of the memory cell transistor and the gate of the transistor formed in the peripheral circuit area a gate; a drain region of a transistor forming a memory cell; and a source region and a drain region of a transistor formed in a peripheral circuit region.

The semiconductor storage device of the present invention has: a semiconductor substrate; an isolation region selectively formed on the upper surface of the semiconductor substrate; first and second regions defined by the isolation region and adjacent to each other via the isolation region; A first impurity region on the first region; a second impurity region formed on the first region; a third impurity region formed on the second region; a fourth impurity region formed on the second region; The first channel region between the impurity region and the second impurity region; the second channel region formed between the third impurity region and the fourth impurity region; on the main surface of the semiconductor substrate where the first channel region is located the first gate formed via the first insulating film on the main surface on the first impurity region side; the main gate on the second impurity region side on the main surface of the semiconductor substrate where the first channel region is located A second gate formed on the surface via a second insulating film capable of accumulating charges; of the main surface of the semiconductor substrate where the second channel region is located, the main surface on the side of the third impurity region is provided via a third insulating film The third gate formed thereon; the fourth gate formed on the main surface on the side of the fourth impurity region of the main surface of the semiconductor substrate where the second channel region is located via a fourth insulating film capable of accumulating charges ; Formed on the isolation region between the first region and the second region, connecting the second gate formed on the first region and the first connection portion formed on the third gate formed on the second region; forming In the second connection portion between the first connection portions, the second connection portion includes a first conductive film and a second conductive film formed around the first conductive film via a fifth insulating film.

On the other hand, the semiconductor memory device of the present invention has: a semiconductor substrate; an isolation region selectively formed on the semiconductor substrate; an active region defined by the isolation region on the main surface of the semiconductor substrate; the first impurity region; the second impurity region formed on the active region; the channel region formed on the main surface of the semiconductor substrate between the first impurity region and the second impurity region; on the channel region Among the surfaces, a ring-shaped first gate formed on the upper surface on the side of the first impurity region via a first insulating film; a recess formed on the side surface of the first gate located in the second impurity region; In the upper surface of the second impurity region, on the upper surface of the second impurity region, a ring-shaped second gate formed on the side surface of the first gate is formed through a second insulating film capable of accumulating charges; a connection part formed in the concave part for connecting the poles; and a voltage application part connected to the connection part and capable of applying a voltage to the second grid.

On the other hand, the method for manufacturing a semiconductor device according to the present invention includes the steps of: selectively forming an isolation region on the main surface of a semiconductor substrate and defining an active region; forming a first insulating film on the active region; The first conductive film is formed on the film; the first conductive film is patterned to form a conductive film pattern, and the conductive film pattern has an opening on the region formed as the first impurity region that can function as a source region. The side surface of the region side has a concave portion; the conductive film pattern is used as a mask, and impurities are introduced on the main surface of the semiconductor substrate to form a first impurity region; the conductive film pattern is covered to form a second insulating film that can accumulate charges; Forming a second conductive film on the insulating film; etching the second conductive film and the second insulating film, forming a second gate via the second insulating film on the side of the opening of the conductive film pattern; The region where the second impurity region that can function as a drain region is located is etched, and the first gate is formed on the main surface of the semiconductor substrate surrounding the first impurity region; impurities to form a second impurity region.

According to the semiconductor memory device (semiconductor integrated circuit device) and its manufacturing method of the present invention, the total number of steps can be reduced and the cost can be reduced.

The above and other objects, features, aspects, and advantages of the present invention will become more apparent through the detailed description of the present invention understood in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a plan view schematically showing a semiconductor integrated circuit device (nonvolatile semiconductor memory device) according to Embodiment 1. As shown in FIG.

Fig. 2 is a cross-sectional view of a memory cell region in a ROM region.

Fig. 3 is a cross-sectional view of a peripheral circuit region.

4 is a cross-sectional view of a memory cell region during a write operation.

FIG. 5 is a cross-sectional view of a memory cell region during an erase operation.

6 is a cross-sectional view of a memory cell region in the first step of the semiconductor integrated circuit device.

7 is a cross-sectional view of the peripheral circuit region in the first step of the semiconductor integrated circuit device.

8 is a cross-sectional view of a memory cell region in a second step of the semiconductor integrated circuit device.

9 is a cross-sectional view of the peripheral circuit region in the second step of the semiconductor integrated circuit device.

10 is a cross-sectional view of a memory cell region in a third step (patterning step of a first conductive film) of the semiconductor integrated circuit device.

11 is a cross-sectional view of the peripheral circuit region in the third step of the semiconductor integrated circuit device.

12 is a cross-sectional view of a memory cell region in a fourth step (forming a channel region under a memory gate of a memory cell transistor) of the semiconductor integrated circuit device.

13 is a cross-sectional view of the peripheral circuit region in the fourth step of the semiconductor integrated circuit device.

14 is a cross-sectional view of a memory cell region in a fifth step (step of forming a second insulating film) of the semiconductor integrated circuit device.

15 is a cross-sectional view of the peripheral circuit region in the fifth step of the semiconductor integrated circuit device.

16 is a cross-sectional view of a memory cell region in a sixth step (step of forming a memory gate and a source region) of the semiconductor integrated circuit device.

17 is a cross-sectional view of the peripheral circuit region in the sixth step of the semiconductor integrated circuit device.

18 is a cross-sectional view of a memory cell region in a seventh step (control gate and gate formation step) of the semiconductor integrated circuit device.

19 is a cross-sectional view of the peripheral circuit region in the seventh step of the semiconductor integrated circuit device.

20 is a cross-sectional view of a memory cell region in an eighth step (forming a drain region of a memory cell transistor and an impurity region of a peripheral circuit transistor) in the semiconductor integrated circuit device.

21 is a cross-sectional view of the peripheral circuit region in the eighth step of the semiconductor integrated circuit device.

22 is a cross-sectional view of a memory cell region in a ninth step (step of forming impurity regions of peripheral circuit transistors) in the semiconductor integrated circuit device.

23 is a cross-sectional view of the peripheral circuit region in the ninth step of the semiconductor integrated circuit device.

24 is a cross-sectional view of a memory cell region in a tenth step (forming a memory cell transistor and a sidewall of a peripheral circuit transistor) of the semiconductor integrated circuit device.

25 is a cross-sectional view of the peripheral circuit region in the tenth step of the semiconductor integrated circuit device.

26 is a cross-sectional view of a memory cell region in an eleventh step (metal silicide formation step) of the semiconductor integrated circuit device.

Fig. 27 is a cross-sectional view of the peripheral region of the eleventh step of the semiconductor integrated circuit device.

28 is a cross-sectional view of a memory cell region in a twelfth step (bit line formation step) of the semiconductor integrated circuit device.

29 is a cross-sectional view of a peripheral circuit region in a twelfth step of the semiconductor integrated circuit device.

Fig. 30 is a cross-sectional view showing details of the connecting portion shown in Fig. 39 .

FIG. 31 is a cross-sectional view showing details on the isolation region in FIG. 41. FIG.

Fig. 32 is a cross-sectional view showing in detail the upper surface of the isolation region of Fig. 42 .

FIG. 33 is a cross-sectional view showing details of the isolation region in FIG. 44. FIG.

34 is a plan view of the peripheral circuit region in the step of patterning the conductive film of the semiconductor integrated circuit device.

35 is a plan view of a peripheral circuit region in a seventh step of forming a control gate and a gate.

Fig. 36 is a plan view of the peripheral circuit region of the photomask.

Fig. 37 is a plan view of the peripheral region when gates of the peripheral circuit region are formed.

38 is a cross-sectional view showing in detail a memory cell transistor of the semiconductor integrated circuit device according to the first embodiment.

39 is a plan view of a memory cell region of the semiconductor integrated circuit device according to Embodiment 2. FIG.

40 is a cross-sectional view showing a manufacturing step corresponding to the first manufacturing step shown in FIGS. 6 and 7 among the manufacturing steps of the semiconductor integrated circuit device according to the first embodiment.

41 is a cross-sectional view taken along line XLI-XLI in FIG. 10 , showing a manufacturing step corresponding to the third step of the semiconductor integrated circuit device according to Embodiment 1. FIG.

42 is a cross-sectional view showing a manufacturing step corresponding to the fifth step of the semiconductor integrated circuit device according to Embodiment 1 shown in FIG. 14 .

43 is a cross-sectional view showing a manufacturing step corresponding to the fifth step of the semiconductor integrated circuit device according to Embodiment 1 shown in FIG. 14 .

44 is a cross-sectional view taken along line XLIV-XLIV in FIG. 16 corresponding to the sixth step of the semiconductor integrated circuit device according to Embodiment 1 shown in FIG. 16 .

45 is a cross-sectional view taken along line XLV-XLV in FIG. 18 , showing a manufacturing step after the manufacturing step of the semiconductor integrated circuit device shown in FIG. 44 .

46 is a plan view of a semiconductor integrated circuit device according to Embodiment 3. FIG.

Fig. 47 is a cross-sectional view taken along line XLVII-XLVII of Fig. 46 .

Fig. 48 is a cross-sectional view taken along line XLVIII-XLVIII of Fig. 46 .

49 is a plan view showing a step corresponding to the first step of the manufacturing steps of the semiconductor integrated circuit device according to Embodiment 1 shown in FIGS. 6 and 7 .

50 is a plan view showing a manufacturing step corresponding to the third step of the semiconductor integrated circuit device according to Embodiment 1 shown in FIGS. 10 and 11 .

Fig. 51 is a plan view showing a manufacturing step corresponding to Fig. 16 and Fig. 17 .

FIG. 52 is a plan view showing a manufacturing step after the manufacturing step shown in FIG. 51 .

53 is a plan view of, for example, a RAM region of the semiconductor integrated circuit device according to the fourth embodiment.

FIG. 54 is an equivalent circuit of the memory cell M1.

Fig. 55 is a cross-sectional view taken along line LV-LV in Fig. 53 .

56 is a plan view showing the first step of the manufacturing steps of the semiconductor integrated circuit device according to the fourth embodiment.

Fig. 57 is a cross-sectional view taken along line LVII-LVII of Fig. 56 .

FIG. 58 is a plan view showing manufacturing steps of the semiconductor integrated circuit after the manufacturing steps shown in FIG. 56 .

Fig. 59 is a sectional view taken along line LIX-LIX of Fig. 58 .

FIG. 60 is a plan view showing the manufacturing steps of the semiconductor integrated circuit device after the manufacturing steps shown in FIG. 58 .

Fig. 61 is a cross-sectional view taken along line LXI-LXI in Fig. 60 .

FIG. 62 is a cross-sectional view showing a manufacturing step after the manufacturing step of the semiconductor integrated circuit device shown in FIG. 61 .

Fig. 63 is a cross-sectional view showing a manufacturing step after the manufacturing step shown in Fig. 62 .

FIG. 64 is a plan view of the manufacturing steps shown in FIG. 63 .

FIG. 65 is a plan view showing a manufacturing step after the manufacturing step shown in FIG. 64 .

Fig. 66 is a sectional view taken along line LXVI-LXVI of Fig. 65 .

67 is a plan view of a peripheral circuit region of a semiconductor integrated circuit device according to a modification of Embodiment 4. FIG.

Fig. 68 is a cross-sectional view taken along line LXVIII-LXVIII in Fig. 67 .

69 is a plan view showing the first step of the semiconductor integrated circuit device according to the modified example of the fourth embodiment.

FIG. 70 is a sectional view of FIG. 69 .

FIG. 71 is a plan view showing a manufacturing step after the manufacturing step shown in FIG. 69 .

Fig. 72 is a sectional view of Fig. 71 .

73 is a plan view of a peripheral circuit region in a step of patterning a conductive film of a semiconductor integrated circuit device.

Fig. 74 is a sectional view of Fig. 73 .

FIG. 75 is a cross-sectional view showing a manufacturing step after the manufacturing step of the semiconductor integrated circuit device shown in FIG. 74 .

76 is a plan view of the peripheral circuit region in the seventh step of forming the control gate and the gate.

Fig. 77 is a sectional view of Fig. 76 .

FIG. 78 is a plan view showing a manufacturing step after the manufacturing step shown in FIG. 76 .

Fig. 79 is a sectional view of Fig. 78 .

80 is an operation diagram during a read operation of the semiconductor integrated circuit device according to the third embodiment.

Fig. 81 is an operation diagram of a writing operation.

Fig. 82 is an operation diagram of an erasing operation.

FIG. 83 is a circuit diagram of a semiconductor integrated device according to Embodiment 3. FIG.

FIG. 84 is a schematic diagram of a semiconductor integrated circuit device according to Embodiment 3. FIG.

Fig. 85 is a cross-sectional view showing details of peripheral circuit transistors.

Detailed ways

Embodiments of the present invention will be described using FIGS. 1 to 85 .

(Embodiment 1)

FIG. 1 is a plan view schematically showing a semiconductor integrated circuit device (nonvolatile semiconductor memory device) 10 according to the first embodiment. The semiconductor integrated circuit device 10 is used, for example, as a hybrid microcomputer equipped with a flash memory having a MONOS (Metal Oxide Nitride Oxide Silicon) structure. This semiconductor integrated circuit device 10 has a peripheral circuit region 65 and a memory cell region 67 on a substrate.

The peripheral circuit area 65 has, for example, an MPU (Micro Processing Unit: Micro Processing Unit) area 61, an I/O (Input/Output: Input/Output) area 64, and a ROM control area 63a.

In addition, the storage unit area 67 has a ROM (Read Only Memory: Read Only Memory) area 63 and a RAM (Random Access Memory: Random Access Memory) area 62 .

These respective regions 61 , 63 a , 64 , 63 , and 62 are defined by the isolation region 25 selectively formed on the main surface of the semiconductor substrate 13 . The isolation region 25 is composed of a groove etched to a depth of, for example, about 300 nm on the main surface of the semiconductor substrate 13 and an insulating film such as a silicon oxide film filled in the groove. FIG. 2 is a cross-sectional view of the memory cell region of the ROM region 63 . As shown in FIG. 2 , a plurality of memory cell transistors 27 are formed in the ROM area 63 of the memory cell area 67 .

In this memory cell region 67 , a P-type well 12 is formed on the main surface side of the semiconductor substrate 13 . A plurality of memory cell transistors (first transistors) 27 having, for example, a MONOS structure are formed on the main surface of the semiconductor substrate 13 , and a bit line 48 is provided on the upper surface side of the memory cell transistors 27 . The memory cell transistor 27 has: a drain region (first impurity region) 17 formed on the semiconductor substrate 13; a source region (second impurity region) 15 formed on the main surface of the semiconductor substrate 13; a channel region 75, Formed on the main surface of the semiconductor substrate 13 between the source region 15 and the drain region 17; the control gate (first gate) 42 is formed on the channel region 75 via the insulating film (first insulating film) 41 Of the main surfaces of the semiconductor substrate 13, the main surface on the side of the drain region 17; the memory gate (second gate) 45 is formed on the channel via an insulating film (second insulating film) 44 capable of accumulating charges. Among the main surfaces of the semiconductor substrate 13 where the region 75 is located, the main surface on the source region 15 side is located.

The control gate 42 is formed of, for example, a conductive film such as a polysilicon film implanted (introduced) with impurities such as phosphorus (P). The thickness of the control gate 42 in the direction perpendicular to the main surface of the semiconductor substrate 13 is, for example, about 200 nm, and the width in the direction parallel to the main surface of the semiconductor substrate 13 is, for example, about 90 nm.

A spacer-shaped insulating film 46 made of, for example, a silicon oxide film or the like is formed on the drain region 17 side of the control gate 42 . The memory gate 45 is formed in a spacer shape on the side surface of the control gate 42 on the source region 15 side, and is made of, for example, a conductive film such as a polysilicon film. The width of the bottom of the spacer-shaped memory gate 45 is, for example, about 45 nm. A spacer-shaped insulating film 46 made of a silicon oxide film or the like is formed on the side surface of the memory gate 45 on the side of the source region 15 .

The source region 15 is an LDD (Lightly doped drain: lightly doped drain) structure, which has a low-concentration impurity diffusion layer 15a that introduces n-type impurities such as arsenic (As) and impurities with a higher concentration than the low-concentration impurity diffusion layer 15a. High-concentration impurity diffusion layer 15b of n-type impurities. In the low-concentration impurity diffusion layer 15a, phosphorus or the like is implanted together with arsenic at an ion implantation amount (d-z amount: doping amount) of, for example, 10 ¹³ to 10 ¹⁴ cm ^-2 .

Phosphorus diffuses more easily than arsenic in a direction parallel to the main surface of semiconductor substrate 13 at the time of thermal diffusion. Therefore, the end portion of the low-concentration impurity diffusion layer 15 a on the control gate 42 side has a lower concentration than the central portion of the low-concentration impurity diffusion layer 15 a. Therefore, by implanting phosphorus or the like, a region having a charge density of impurities suitable for forming holes can be formed at the end of the low-concentration impurity diffusion layer 15a. Furthermore, when arsenic is used to form the low-concentration impurity diffusion layer 15a, by simultaneously introducing boron, a structure (Halo structure) in which the boron impurity diffusion layer covers the arsenic impurity diffusion layer can be formed and the electric field can be further increased.

The drain region 17 also has the same structure as the source region 15, and has an n-type low-concentration impurity diffusion layer 17a and a high-concentration impurity diffusion layer 17b having a higher concentration than the low-concentration impurity diffusion layer 17a.

And, on the upper surface of the memory electrode 45, the upper surface of the control gate 42, the upper surface of the source region 15, and the upper surface of the drain region 17, for example, a layer made of cobalt silicide (CoSi) or nickel silicide (NiSi) is respectively formed. metal silicide film 37 . Here, the upper surface of the control gate 42 is formed in a flat surface across the side of the source region 15 to the side of the drain region 17, and the metal silicide film 37 formed on the upper surface of the control gate 42 also extends across the side of the source region 15. The side to the drain region 17 is formed in a flat shape. Therefore, there is no variation in the thickness of the metal silicide film 37, the uniformity of the resistance of the control gate 42 can be realized, and the resistance of the control gate 42 can be set to a desired value.

The channel region 75 has: a channel region (first channel region) 14 under the memory gate, which is located on the side of the source region 15 and formed in a region below the memory gate 45; a channel region (second channel region) under the control gate. The channel region) 16 is formed on the side of the drain region 17 and is formed in a region under the control gate 42 .

The charge density (impurity concentration) of the channel region 14 under the memory gate is smaller than that of the channel region 16 under the control gate. For example, the charge density of the channel region 14 under the memory gate is preferably 10 ¹⁷ -10 ¹⁸ /cm ³ , more preferably 3×10 ¹⁷ -7×10 ¹⁷ /cm ³ , for example about 5×10 ¹⁷ /cm ³ . The charge density (impurity concentration) of impurities in the channel region 16 under the control gate is, for example, 10 ¹⁸ /cm ³ .

The insulating film 44 is formed on the main surface of the semiconductor substrate 13 under the memory gate 45 and across between the control gate 42 and the memory gate 45 .

For example, a silicon oxide film with a thickness of about 5 nm in the vertical direction perpendicular to the main surface of the semiconductor substrate 13, a silicon nitride film with a thickness of about 10 nm formed on the silicon oxide film, and a silicon nitride film formed on the silicon nitride film are sequentially formed. The insulating film 44 is formed by laminating silicon oxide films of about 5 nm in thickness. In addition, the thickness of the insulating film 44 in the direction perpendicular to the main surface of the semiconductor substrate 13 is, for example, about 20 nm.

The insulating film 41 is formed on the main surface of the semiconductor substrate 13 located under the control gate 42, and is composed of, for example, a silicon oxide film with a thickness of about 3 nm.

An insulating film 52 is formed on the surface of the memory cell transistor 27 configured in this way, and an interlayer insulating film 38 is formed on the insulating film 52 . Further, a bit line 48 is formed on the upper surface of the interlayer insulating film 38 .

Also, a contact portion 49 is formed on the metal silicide film 37 formed on the upper surface of the drain region 17 . The contact portion 49 is composed of a contact hole penetrating from the upper surface of the interlayer insulating film 38 to the lower surface side; a conductive film 39 formed on the inner wall surface of the contact hole; a conductive film 50 formed on the conductive film 39 surface side, filled in the contact hole. Furthermore, the contact portion 49 penetrates the interlayer insulating film 38 and is connected to the bit line 48 formed on the interlayer insulating film 38 .

FIG. 3 is a cross-sectional view of the peripheral circuit region 65 . As shown in FIG. 3 , P-type well 12 and N-type well 18 are formed on the main surface of semiconductor substrate 13 where peripheral circuit region 65 is located. In addition, an isolation region (STI (Shallow Trench Isolation: Shallow Trench Isolation) isolation) 25 is formed at the boundary portion between the P-type well and the N-type well 18 . Also, a peripheral circuit transistor 28 a is formed on the upper surface of the P-type well 12 . In addition, a peripheral circuit transistor 28 b is formed on the upper surface of the N-type well 18 . Furthermore, an insulating film 52 is formed on the upper surfaces of the peripheral circuit transistors 28 a and 28 b , and an interlayer insulating film 38 is formed on the upper surfaces of the insulating film 52 . A plurality of upper layer wirings 48 a , 48 b , 48 c , and 48 d are arranged on the upper surface of the interlayer insulating film 38 . The peripheral circuit transistor 28 a has a gate 43 a formed on the main surface of the semiconductor substrate 13 and a gate insulating film 40 formed between the gate 43 a and the semiconductor substrate 13 .

The height of the gate 43a in the direction perpendicular to the main surface of the semiconductor substrate 13 is substantially the same as the height of the control gate 42 of the memory cell transistor 27 shown in FIG. 2 .

Further, the peripheral circuit transistor 28 a has a source region 19 a and a drain region 19 b formed on the main surface of the semiconductor substrate 13 . Side walls 47 are formed on the side surfaces of the gate electrode 43a.

The source region 19a has an N-type low-concentration impurity diffusion layer 19a1 and an N-type high-concentration impurity diffusion layer 19a2 having a higher charge density than that introduced into the low-concentration impurity diffusion layer 19a1. Also, the drain region has the same structure as the source region 19a, and has a low-concentration impurity diffusion layer 19b1 and a high-concentration impurity diffusion layer 19b2 having a higher charge density than the low-concentration impurity diffusion layer 19b1. Furthermore, a metal silicide film 37 made of, for example, cobalt silicide (CoSi) or nickel silicide (NiSi) is formed on the upper surfaces of the gate electrode 43a, the source region 19a, and the drain region 19b.

The peripheral circuit transistor 28b has: a gate 43b formed on the main surface of the semiconductor substrate 13; a gate insulating film 40 formed on the main surface of the semiconductor substrate 13 under the gate 43b; 43b is adjacent to the P-type source region 20a and the P-type drain region 20b on the main surface of the semiconductor substrate 13 . Also, the metal silicide film 37 is formed on the upper surface of the gate electrode 43b, the upper surface of the source region 20a, and the upper surface of the drain region 20b, and a contact portion 49 is formed. The contact portion 49 is connected to the upper layer wiring 48c, 48d.

The write operation of the semiconductor integrated circuit device 10 configured as above will be described with reference to FIG. 4 . FIG. 4 is a cross-sectional view of memory cell region 67 during a write operation. As shown in FIG. 4 , a voltage of, for example, about 0.8 V is applied to the drain region 17 of the selected memory cell transistor 27 a, and a voltage of, for example, about 6 V is applied to the source region 15 . Then, a voltage of approximately 11 V is applied to the memory gate 45 , and a voltage of approximately 1.5 V is applied to the control gate 42 .

In this way, after the voltage is applied, a large electric field is generated near the boundary between the control gate 42 and the memory cell gate 45, and many thermal electrons are generated. Furthermore, electrons are trapped in the insulating film 44 which can store charges. Furthermore, in the insulating film 44, electrons enter the portion of the silicon nitride to write electrical information. This phenomenon is known as source side injection (Source side injection: SSI).

In addition, an erase operation of the semiconductor integrated circuit device 10 configured as above will be described using FIG. 5 . FIG. 5 is a cross-sectional view of memory cell region 67 in an erase operation. As shown in FIG. 5 , for example, a voltage of about 6 V is applied to the source region 15 and a voltage of about 0 V is applied to the drain region 17 . Then, a voltage of approximately 0 V is applied to the control gate 42 , and a voltage of approximately −6 V is applied to the memory gate 45 .

In this way, by applying a negative potential to the memory gate 45 and a positive potential to the impurity diffusion layer on the side of the memory gate, a strong inversion can occur at the end of the source region 15 on the side of the memory gate 45, causing an interband tunneling phenomenon. , creating holes. The generated holes are injected into the insulating film 44 under the memory gate 45 due to the bias voltage, thereby performing an erasing operation.

In this way, the holes recombine with the electrons injected into the insulating film 44, whereby the raised threshold voltage can be lowered.

In the read operation, for example, a voltage of about 1.5 V is applied to the control gate 42 and the memory gate 45 of the selected memory cell transistor 27 . Further, a voltage of, for example, about 0 V is applied to the source region 15 , and a voltage of, for example, about 1.5 V is applied to the drain region 17 . Thus, a voltage between the threshold voltage of the selected memory cell transistor 27 in the write state and the threshold voltage of the memory cell transistor 27 in the erase state is applied between the source region 15 and the drain region 17 . Here, when electrons are trapped in the insulating film 44 of the selected memory cell transistor 27 and the threshold voltage rises, the OFF state is maintained, and when holes are injected into the insulating film 44 , the ON state is established.

A method of manufacturing the semiconductor integrated circuit device 10 configured as described above will be described.

6 is a cross-sectional view of the memory cell region 67 in the first step of the manufacturing process of the semiconductor integrated circuit device 10, and FIG. 7 is a cross-sectional view of the peripheral circuit region 65 in the first step.

As shown in FIG. 7 , the main surface of the semiconductor substrate 13 is selectively etched by, for example, about 300 nm to form grooves for the isolation region (element isolation region) 25 . Then, thermal oxidation is performed to form a thermal oxide film of, for example, about 10 nm in thickness on the main surface of the semiconductor substrate 13 and the surface of the groove portion. In this way, after the thermal oxide film is formed, an insulating film such as a silicon oxide film of about 500 nm is deposited on the main surface of the semiconductor substrate 13, and the silicon oxide film is filled in the groove by CMP (Chemical Mechanical Polishing) to form an isolation layer. Area 25.

Thus, by selectively forming the isolation region 25, on the main surface of the semiconductor substrate 13, the ROM region 63 or the RAM region 62 shown in FIG. 1 and the logic circuit region ( peripheral circuit area) 65 and so on.

In this way, after the isolation region 25 is formed, an insulating film 30 is formed on the main surface of the semiconductor substrate 13 with a thickness of, for example, about 5 nm. It is composed of silicon oxide formed by the oxidation method. Here, as shown in FIG. 6 , impurities having a charge density of, for example, about 10 ¹⁸ /cm ³ are introduced into the main surface of semiconductor substrate 13 where memory cell region 67 of FIG. 1 is located, to form impurity region 16 a.

8 is a cross-sectional view of the memory cell region 67 in the second step (the step of forming the first conductive film) of the semiconductor integrated circuit device 10 . 9 is a cross-sectional view of the peripheral circuit region 65 in the second step of the semiconductor integrated circuit device 10 . As shown in FIGS. 8 and 9, a polysilicon film of about 2.9 nm in thickness is deposited on the upper surface of the insulating film 30 formed on the entire surface of the memory cell 67 and the peripheral circuit region 65 on the main surface of the semiconductor substrate 13. Constructed conductive film 31. Then, an insulating film 32 is deposited on the upper surface of the conductive film 31 made of polysilicon film by a CVD method using TEOS (Tetraethoxysilane: tetraethoxysilane) gas or the like.

10 is a cross-sectional view of the memory cell region 67 in the third step (patterning step of the first conductive film) of the semiconductor integrated circuit device 10 . As shown in FIG. 10, the insulating film 32 and the conductive film 31 are patterned to form a conductive pattern 31a forming an opening 31b in a region where the source region 15 of the memory cell transistor 27 shown in FIG. 2 is formed. FIG. 11 is a cross-sectional view of the peripheral circuit region 65 in the third step of the semiconductor integrated circuit device 10 . As shown in FIG. 11 , the conductive film pattern 31 a covers the main surface of the semiconductor substrate 13 in the peripheral circuit region 65 .

12 is a cross-sectional view of the memory cell region 65 in the fourth step (the step of forming the channel region 14 under the memory gate of the memory cell transistor) of the semiconductor integrated circuit device 10 . As shown in FIG. 12, the conductive film pattern 31a has an opening 31b exposing a part of the upper surface of the impurity region 16a. Then, using the conductive film pattern 31a as a mask, impurities having a conductivity type different from that of the impurity region 16a are introduced into the main surface of the semiconductor substrate 13 . In this way, when an impurity having a conductivity type different from that of impurity region 16a is introduced into the main surface of semiconductor substrate 13, impurity region 14a having a charge density lower than that of impurity region 16a is formed. In this way, the impurity region 16a remains in the part of the main surface of the semiconductor substrate 13 under the conductive film pattern 31a, and the impurity region 14a having a lower charge density than the impurity region 16a is formed in the portion where the opening 31b of the conductive film pattern 31a is located. .

In this way, by forming the openings 31b in the conductive film pattern 31a in advance, it is possible to separate impurity regions having different concentrations without using a mask.

In this way, the conductive pattern 31a can be used as a mask for maskless implantation, and the channel region 14 under the memory gate can be formed more easily. FIG. 13 is a cross-sectional view of the peripheral circuit region 65 in the fourth step of the semiconductor integrated circuit device 10 . As shown in FIG. 13 , in the peripheral circuit region 65 , the conductive film 31 and the insulating film 32 formed on the conductive film 31 are formed substantially over the entire main surface of the semiconductor substrate 13 .

14 is a cross-sectional view of the memory cell region 67 in the fifth step (the second insulating film forming step) of the semiconductor integrated circuit 10 . As shown in FIG. 14, the insulating film 32 is removed, and an insulating film made of silicon oxide, an insulating film made of silicon nitride, and an insulating film made of silicon oxide are sequentially laminated so as to cover the conductive film pattern 31a. Thus, the insulating film 33 is formed to cover the conductive film pattern 31a. Furthermore, silicon oxide may be formed by a thermal oxidation method such as the ISSG oxidation method. As described above, when the insulating film 33 is formed on the conductive pattern 31a, a thermal oxide film is also formed on the main surface of the semiconductor substrate 13 where the opening 31b is located. On the other hand, an insulating film 30 is formed between the conductor pattern 31 a and the main surface of the semiconductor substrate 13 . And, a conductive film 34 made of a polysilicon film or the like is deposited on the upper surface of the insulating film 33 .

FIG. 15 is a cross-sectional view of the peripheral circuit region of the fifth step in the semiconductor integrated circuit device 10. As shown in FIG. As shown in FIG. 15, in the fifth step of the semiconductor integrated circuit device 10, in the region where the peripheral circuit region 65 shown in FIG. The film pattern 31a, the insulating film 33 formed on the upper surface of the conductive film pattern 31a, and the conductive film 34 formed on the insulating film 33.

16 is a cross-sectional view of a memory cell region in the sixth step (step of forming a memory gate and a source region) of the semiconductor integrated circuit device 10 . As shown in FIG. 16, the conductive film 34 formed on the upper surface of the insulating film 33 is etched to form a spacer-shaped memory gate 45 on the inner side of the opening 31b of the conductive film pattern 31a. In this way, the memory gate 45 can be naturally formed by forming the opening 31b in the conductive film pattern 31a in advance. That is, when forming the memory gate 45, the memory gate 45 can be formed without using a mask, and the number of masks can be reduced.

In addition, since the memory gate 45 can be naturally formed, unlike the case where the memory gate 45 is formed by photolithography, it is possible to prevent problems such as misalignment due to shifting of the mask or formation failure.

Here, impurity region 14 a has been formed in a region surrounded by sidewall-shaped memory gate 45 in the main surface of semiconductor substrate 13 . Then, using the conductive film pattern 31a and the memory gate 45 as a mask, impurities are introduced to form an n-type low-concentration impurity diffusion layer 15a. Therefore, the impurity region 14a remains on the main surface of the semiconductor substrate 13 located under the memory gate 45, forming the channel region 14 under the memory gate. Also, an impurity region 16a is formed on the main surface of the semiconductor substrate 13 located under the conductive film pattern 31a. Thus, according to the manufacturing method of the semiconductor integrated circuit device 10 of the first embodiment, the channel region 14 under the memory gate can be formed by maskless implantation, and at the same time, the low-concentration impurity layer 15a of the source region 15 can be formed.

17 is a cross-sectional view of the peripheral circuit region in the sixth step of the semiconductor integrated circuit device 10 . As shown in FIG. 17 , a conductive film 31 and an insulating film 33 formed on the upper surface of the conductive film 31 are sequentially formed on the main surface of the semiconductor substrate 13 in the peripheral circuit region.

18 is a cross-sectional view of the memory cell region in the seventh step (control gate and gate formation step) of the semiconductor integrated circuit device 10, and FIG. 19 is a cross-sectional view of the peripheral circuit region in the seventh step of the semiconductor integrated circuit device 10. In this seventh step, first, the insulating film 33 formed on the memory cell region and the peripheral circuit region shown in FIGS. 16 and 17 is removed. Here, in the memory cell region, the insulating film 33 formed on the upper surface of the conductive film pattern 31a and the insulating film formed on the region sandwiched by the memory gate 45 on the main surface of the semiconductor substrate 13 are removed. 33. Furthermore, in the peripheral circuit region, the insulating film 33 formed on the upper surface of the conductive film pattern 31a is removed. Therefore, the insulating film 33 remains on the side of the conductive pattern 31 a on the opening portion 31 b side and on the main surface of the semiconductor substrate 13 located under the memory gate 45 . That is, the insulating film 33 is formed across the lower surface to the side surface of the formed memory gate 45 . In this way, the insulating film 44 shown in FIG. 2 is formed.

Then, after removing a part of the insulating film 33, a photomask is placed on the upper surface of the conductive pattern 31a, and the conductive pattern 31a is patterned by photolithography. This patterning simultaneously forms the control gate 42 of the memory cell transistor 27 formed in the memory cell region and the gates 43a, 43b of the peripheral circuit transistors 28a, 28b formed in the peripheral circuit region.

In addition, the drain region 17 of the memory cell transistor 27 and the drain regions 19b and 20b of the peripheral circuit transistors 28a and 28b shown in FIG. 2 are exposed externally by patterning.

In the patterning of the conductive film pattern 31a, the selective etching of the silicon oxide film and the polysilicon film is adopted, thereby, the etching on the main surface of the semiconductor substrate 13 where the drain regions 17, 19b, and 20b are located can be suppressed. corrosion damage. In this way, etching damage to the main surface of the semiconductor substrate 13 where the drain regions 17, 19b, and 20b are located is reduced, thereby suppressing depressions on the main surface of the semiconductor substrate 13 where the drain regions 17, 19b, and 20b are located.

20 is a cross-sectional view of a memory cell region in the eighth step (forming a drain region of a memory cell transistor and an impurity region of a peripheral circuit transistor) in the semiconductor integrated circuit device 10 . 21 is a cross-sectional view of the peripheral circuit region in the eighth step of the semiconductor integrated circuit device 10 . In FIGS. 20 and 21 , photolithography is performed using a mask 72 in which regions where the drain region 17 of the memory cell transistor 27 shown in FIG. 1 and the source region 19a and drain region 19b of the peripheral circuit transistor 28a are located are opened. Impurities are implanted into the main surface of the semiconductor substrate 13 exposed from the formed photoresist to form the low-concentration impurity diffusion layer 17a of the memory cell transistor 27, the low-concentration impurity diffusion layer 19a1 of the peripheral circuit transistor 28a, 19b1.

Here, in the manufacturing method of the semiconductor integrated circuit device 10 according to the first embodiment, the so-called ONO film is not formed on the main surface of the semiconductor substrate 13 where the drain regions 17, 19b, 20b and source regions 19a, 20a are located. The insulating film 33. Therefore, no thermal oxidation treatment is performed on the silicon oxide film of the ONO film on the main surface of the semiconductor substrate 13 where the drain regions 17, 19b, 20b and source regions 19a, 20a are located. Thus, the main surface of semiconductor substrate 13 where drain regions 17, 19b, 20b and source regions 19a, 20a are located can suppress dishing by thermal oxidation treatment of ONO film formation.

And, there is no ONO film formed on the main surface of the semiconductor substrate 13 where the drain regions 17, 19b, 20b and source regions 19a, 20a are located, so the damage during removal of the ONO film will not occur, and the leakage of the drain regions 17, 19b can be further suppressed. , 20b and the main surface of the semiconductor substrate 13 where the source regions 19a, 20a are located are recessed.

Furthermore, when the low-concentration impurity diffusion layer 17a is formed as described above, the impurity region 16a shown in FIG.

22 is a cross-sectional view of a memory cell region in the ninth step of the semiconductor integrated circuit 10 (the step of forming the impurity region of the peripheral circuit transistor). 23 is a cross-sectional view of the peripheral circuit region in the ninth step of the semiconductor integrated circuit 10 . As shown in FIG. 22 and FIG. 23, in the ninth step, a photomask 73 is disposed on the main surface of the semiconductor substrate 13, and a peripheral circuit where the source region 20a and the drain region 20b of the transistor 28b are located is formed by photolithography. The partially opened photoresist. In addition, impurities are introduced into the main surface of the semiconductor substrate 13 where the source region 20a and the drain region 20b are located to form low-concentration impurity diffusion layers 20a1 and 20b1.

FIG. 24 is a cross-sectional view of a memory cell region in the tenth step (forming a memory cell transistor and a sidewall of a peripheral circuit transistor) of the semiconductor integrated circuit device 10 . 25 is a cross-sectional view of the peripheral circuit region in the tenth step of the semiconductor integrated circuit device 10 . In FIGS. 24 and 25, an insulating film 36 made of a silicon oxide film or the like is formed on the main surface of the semiconductor substrate 13 by, for example, a CVD method. Then, the insulating film 36 is etched to form spacer-shaped insulating films 36, 46 on the side surfaces of the control gate 42 and the gates 43a, 43b.

Then, impurities are introduced into the main surface of the semiconductor substrate 13, and the high-concentration impurity diffusion layers 17b, 15b and the high-concentration impurity diffusion layers 19a2, 19b2 are formed on the main surface of the semiconductor substrate 13, and the memory cell transistor 27 and the peripheral circuit transistor are formed. 28a. Furthermore, after the high-concentration impurity diffusion layers 20a2 and 20b2 are formed, the peripheral circuit transistor 28b is formed.

FIG. 26 is a cross-sectional view of a memory cell region in the eleventh step (metal silicide formation step) of the semiconductor integrated circuit device 10 . 27 is a cross-sectional view of the peripheral region of the semiconductor integrated circuit device 10 in the eleventh step.

As shown in FIG. 26 and FIG. 27, on the upper surface of the control gate 42 of the memory cell transistor 27 formed, the source region 15, the drain region 17, the source regions 19a, 20a and the drain regions of the peripheral circuit transistors 28a, 28b Metal silicide films 37 made of cobalt silicide (CoSi) or nickel silicide (NiSi) are formed on the upper surfaces of 19b and 20b. At this time, the metal silicide film 37 formed on the upper end surface of the control gate 42 and the metal silicide film 37 formed on the upper end surface of the memory gate 45 are electrically isolated by the insulating film 44 .

28 is a cross-sectional view of a memory cell region in the twelfth step (bit line formation step) of the semiconductor integrated circuit device 10 . 29 is a cross-sectional view of the peripheral circuit region of the semiconductor integrated circuit device 10 in the twelfth step. As shown in FIGS. 28 and 29 , an insulating film 52 is formed on the upper surfaces of the formed memory cell transistors 27 and peripheral circuit transistors 28 a and 28 b , and an interlayer insulating film 38 is formed on the upper surfaces of the insulating films 52 . Furthermore, a contact portion 49 penetrating through the insulating film 52 formed on the high-concentration impurity diffusion layer 17b and the interlayer insulating film 38 is formed. Furthermore, wirings 48 a , 48 b , 48 c , and 48 d are formed on the interlayer insulating film 38 . As described above, the semiconductor integrated circuit device 10 shown in FIGS. 2 and 3 is formed.

In the manufacturing method of the semiconductor integrated circuit device 10, the formation of recesses on the main surface of the semiconductor device 13 where the drain regions 17, 19b, 20b and source regions 19a, 20a are located can be suppressed, so the distance from the semiconductor substrate 13 can be reduced. Drain regions 17, 19b, 20b and source regions 19a, 20a are formed at shallower positions on the main surface of .

Here, when recesses are formed in regions to be drain regions 17, 19b, 20b and source regions 19a, 20a, the main surface of semiconductor substrate 13 located under control gate 42, gates 43a, 43b and drain regions 17, The border regions of 19b, 20b and source regions 19a, 20a form a step difference. In addition, when impurities are introduced into regions to be the drain regions 17, 19b, 20b and source regions 19a, 20a in a state where a step difference of, for example, about 30 nm is formed in the boundary region, the charge density of the impurities in the boundary region increases. Be well known. Therefore, when the introduced impurities are thermally diffused, they are also diffused in a direction horizontal to the main surface of the semiconductor substrate 13 . As a result, there arises a problem that the distance between the source region 15, 19a, 20a and the drain region 17, 19b, 20b decreases, and the threshold voltage of the memory cell transistor 27 decreases rapidly. Furthermore, the threshold voltages of the memory cell transistors 27 vary.

On the other hand, according to the manufacturing method of the semiconductor integrated circuit device 10 of the first embodiment, the formation of recessed portions on the upper surfaces of the drain regions 17, 19a, and 20a and the source regions 19a, 20a can be suppressed. Therefore, it is possible to suppress the formation of a large step difference in the boundary region with the main surface of the semiconductor substrate 13 located under the control gates 42, 43a, 43b.

38 is a cross-sectional view showing in detail memory cell transistor 27 of semiconductor integrated circuit device 10 according to Embodiment 1. As shown in FIG.

As shown in this FIG. 38 , between the main surface of the semiconductor substrate 13 located under the control gate 42 and the main surface R1 of the semiconductor substrate 13 located on the side opposite to the memory gate 45 of the control gate 42 , The distance h2 perpendicular to the direction of the main surface of the semiconductor substrate 13 is, for example, about 2 nm to 3 nm. Furthermore, the distance h1 between the main surface R2 of the semiconductor substrate 13 under the memory gate 45 and the main surface of the semiconductor substrate 13 under the control gate 42 is about 10 nm.

That is, to make the distance h2 smaller than the distance h1, the main surface of the semiconductor substrate 13 located under the insulating film 46 is located above the main surface of the semiconductor substrate 13 located below the memory gate 45 . Furthermore, as shown in FIGS. 20 and 38 , the boundary region between the main surface R2 and the main surface of the semiconductor substrate 13 located under the control gate 42 has almost no step difference, and the boundary region is in a substantially flat state. Impurities are introduced into the main surface R2 to form the low-concentration impurity diffusion layer 17a, so that variations in the charge density of the introduced impurities can be suppressed.

Fig. 85 is a cross-sectional view showing details of peripheral circuit transistors. As shown in FIG. 85 , even when impurities are diffused, it is possible to prevent the impurities from being largely diffused in the direction parallel to the main surface of the semiconductor substrate 13, and to make the threshold voltage of the formed memory cell transistor 27 a desired value. value, and can suppress variations in the threshold voltages of the memory cell transistors 27.

In addition, the time when damage occurs on the main surface of the semiconductor substrate 13 located on both sides of the gates 43a, 43b of the peripheral circuit transistors 28a, 28b is different from the main surface shown in FIG. 38 that occurs when the conductive film pattern 31a is patterned. The timing of R1 damage is the same.

Therefore, it is possible to suppress the formation of a large step portion in the boundary region between the main surface of the semiconductor substrate 13 on both sides of the gates 43a, 43b and the main surface of the semiconductor substrate 13 below the gates 43a, 43b. Along with this, even in the peripheral circuit transistors 28a, 28b, the distance between the source regions 19a, 20a and the drain regions 19b, 20b can be suppressed from becoming small, the threshold voltage of the peripheral circuit transistors 28a, 28b can be suppressed from being small, and can be changed to the desired threshold voltage.

And, the distance in the direction perpendicular to the main surface of the main surface of the semiconductor substrate 13 located under the gates 43a, 43b and the main surface of the semiconductor substrate 13 adjacent to the gates 43a, 43b can be suppressed to, for example, 2 nm to 2 nm. About 3nm. Moreover, in the manufacturing steps shown in FIGS. 6 and 7 , the charge density of the impurities introduced into the main surface of the semiconductor substrate 13 where the memory cell region is located is less than or equal to the charge density of the impurities introduced into the semiconductor substrate 13 where the peripheral circuit region is located. The charge density on the major surface.

In this case, through the thermal oxidation treatment in the manufacturing steps shown in FIGS. The thickness of the insulating film 30 formed on the main surface of the semiconductor substrate 13 .

Furthermore, the insulating film 30 formed on the main surface R1 shown in FIG. Therefore, the main surface R1 is located above the main surface of the semiconductor substrate 13 located on the side surface of the gate. Thus, the threshold voltage of the memory cell transistor 27 can be set to a desired threshold voltage.

Here, the fourth step (the step of forming the channel region under the gate of the memory cell transistor), the fifth step (the step of forming the second insulating film), the sixth step (the step of forming the memory gate, the source region formation step) is a manufacturing step unique to the memory cell transistor 27 which is different from the manufacturing steps of the peripheral circuit transistors 28a and 28b. When performing such steps specific to the memory cell transistor 27, covering the main surface of the semiconductor substrate 13 where the peripheral circuit region is located with the conductive film pattern 31a can suppress influence on the semiconductor substrate 13 where the peripheral circuit region is located.

On the other hand, the following steps are respectively carried out simultaneously: the control gate and the gate of the peripheral circuit transistor are patterned; the drain region 17 of the memory cell transistor 27 and the drain region 19b and the source region 19a of the peripheral circuit transistor 28a are formed; wall; forming a metal silicide film.

In this way, at first, the steps specific to the memory cell transistor 27 are performed while covering the peripheral circuit region, and then the common steps of the memory cell transistor 27 and the peripheral circuit transistors 28a, 28b are performed, thereby reducing the manufacturing cost of the semiconductor integrated circuit device 10. number of steps.

(Embodiment 2)

A semiconductor integrated circuit device 10 according to Embodiment 2 of the present invention will be described with reference to FIGS. 30 to 33 and FIGS. 39 to 45 . 39 is a cross-sectional view of the memory cell region 67 of the semiconductor integrated circuit device 10 according to the second embodiment. As shown in FIG. 39 , the semiconductor integrated circuit device 10 has: an isolation region 90 selectively formed on the main surface of the semiconductor substrate 13 where the memory cell region 67 is located; a plurality of divided memory cells defined by the isolation region 90 The regions MCR1 and MCR2 ; the control gate 42 is formed on each divided memory cell region MCR1 and MCR2 ; the connection region PR is connected between the memory gates 45 .

In addition, a plurality of control gates 42 extending in one direction are formed on the main surface of the semiconductor substrate 13 where the divided memory cell regions MCR1 and MCR2 are located, and a plurality of control gates 42 are formed via an insulating film 44 on the side surfaces of the control gates 42 . The memory gate 45.

Furthermore, an isolation region 92 is formed on the main surface of the semiconductor substrate 13 between the control gates 42 . Furthermore, a plurality of drain regions 17 are defined by the isolation region 92 on the main surface of the semiconductor substrate 13 located between the control gates 42 . Furthermore, a contact portion 49 for applying a desired voltage to each drain region 17 is provided on each drain region 17 .

The source region 15 extending along the memory gates 45 is formed on the main surface of the semiconductor substrate 13 between the memory gates 45 . A channel region 75 shown in FIG. 2 is formed on the main surface of the semiconductor substrate 13 located between the source region 15 and the drain region 17 . On the isolation region 90 between the adjacent divided memory cell regions MCR1 and MCR2 is formed a connection wiring (first connection portion) 45A, which connects the memory gate 45 formed on one divided memory cell region MCR1 to the memory gate 45 via the isolation region. 90 is formed on the memory gate 45 on the adjacent divided memory cell region MCR2.

Furthermore, a connection portion (first connection portion) 59 for connecting the connection wires 45A is formed on the upper surface of the isolation region 90 between the connection wires 45A, and a pair of wires is formed on the first connection portion 59 . A contact portion (voltage applying portion) 69 to which a desired voltage is applied to the memory gate 45 .

Furthermore, connection wiring (third connection portion) 42A connecting control gate 42 formed in divided memory cell region MCR1 and control gate 42 formed in divided memory cell region MCR2 is formed on isolation region 90 . A contact portion 68 for applying a desired voltage to the control gate 42 is formed on the connection wiring, and a pad portion 93 is formed at a lower end portion of the contact portion 68 .

FIG. 30 is a cross-sectional view showing details of the connecting portion 59 shown in FIG. 39 . As shown in FIG. 30 , the connecting portion 59 has: a conductive film (remaining portion) 31A formed on the upper surface of the isolation region 90 and made of, for example, a polycrystalline silicon thin film; and an insulating film (fifth insulating film) 44 formed on the upper surface of the isolation region 90. The side surface (peripheral surface) of the remaining portion 31A is formed of, for example, an ONO film, and a conductive film (second conductive film) 31B is formed on the peripheral surface of the remaining portion 31A to fill between the connection wirings 45A. The contact portion 69 is formed on the upper surface of the connection portion 59 configured in this way. Therefore, the voltage applied to the contact portion 69 is transmitted to the connection wiring 45A through the conductive film 31B, and applied to each memory gate 45 .

Furthermore, in Embodiment 2, two (plural) residual portions 31A are formed between the memory gates 45A in the direction in which the memory gates 45 extend, but the present embodiment is not limited thereto, and may be one. A method of manufacturing the semiconductor integrated circuit device 10 configured as described above will be described. 40 is a cross-sectional view showing a manufacturing step corresponding to the first manufacturing step shown in FIGS. 6 and 7 among the manufacturing steps of the semiconductor integrated circuit device 10 according to the first embodiment.

As shown in FIG. 40 , isolation regions 90 and 92 are selectively formed on the main surface of semiconductor substrate 13 . As a result, divided memory cell regions MCR1 and MCR2 defined by isolation region 90 are formed on the main surface of semiconductor substrate 90 . Furthermore, active region 91 defined by isolation region 92 is formed on the main surface of semiconductor substrate 13 where divided memory cell regions MCR1 and MCR2 are located.

FIG. 41 is a cross-sectional view taken along line XLI-XLI of FIG. 10 showing a manufacturing step corresponding to the third step of the semiconductor integrated circuit device 10 of Embodiment 1, and FIG. 31 shows details on the isolation region 90 in FIG. 41. Sectional view of the situation.

As shown in FIG. 41 and FIG. 31, a residual portion 31A is formed on the isolation region 90 at the same time as the conductive film pattern 31a is formed, and the conductive film pattern 31a forms an opening 31b in the region where the source region 15 is formed.

Also, the distance L1 between the conductive film patterns 31a is formed to be, for example, about 300 nm. In addition, the width L2 of the remaining portion 31A in the direction in which the plurality of conductive film patterns 31a are arranged is, for example, about 150 nm, and the width L3 of the remaining portion 31A in the direction in which the conductive film patterns 31a extend is formed in, for example, about 100 nm. Furthermore, when forming a plurality of remaining portions 31A, the remaining portions 31A are formed such that the distance L4 between the remaining portions 31A is, for example, about 100 nm. In addition, the distance L5 between the remaining portion 31A and the adjacent conductive film pattern 31a is formed to be, for example, 100 nm or less.

42 and 43 are cross-sectional views along line XLII-XLII of FIG. 14 of the manufacturing steps corresponding to the fifth step of the semiconductor integrated circuit device 10 according to Embodiment 1 shown in FIG. 14, and FIG. A cross-sectional view showing the upper surface of the isolation region 90 in FIG. 42 .

As shown in FIG. 14 and FIG. 42, the conductive film patterns 31a are covered, and at the same time, the insulating film 33 is formed on the main surface of the semiconductor substrate 13 between the conductive film patterns 31a. Thus, the insulating film 33 is also formed on both side surfaces of the conductive film 31 a and on the surface of the remaining portion 31A. Also, a conductive film 34 is deposited on the upper surface of this insulating film 33 .

Furthermore, as shown in FIGS. 14 , 32 , and 43 , a conductive film 34 is formed on the upper surface of the insulating film 33 . At this time, the gap between the remaining portion 31A and the gap between the remaining portion 31A and the conductive film pattern 31 a are filled with the conductive film 34 .

FIG. 44 is a cross-sectional view taken along line XLIV-XLIV in FIG. 16 corresponding to the sixth step of the semiconductor integrated circuit device 10 of Embodiment 1 shown in FIG. 16 , and FIG. 33 shows the isolation region 90 in FIG. 44 Sectional view of the details.

As shown in these FIGS. 16 , 33 , and 44 , the conductive film 34 is etched to form the memory gate 45 .

At this time, while forming the memory gate 45 shown in FIG. 2 , the conductive film 31B remains on the surface of the remaining portion 31A. Here, since the remaining portions 31A are arranged so as to be close to each other, the conductive films 31B formed on the surface of the remaining portions 31A are connected and integrated. Also, since the remaining portion 31A is close to the conductive pattern 31a, the conductive film 31B formed on the surface of the remaining portion 31A and the formed memory gate 45 are connected. That is, in the step of forming the memory gates 45 , the memory gates 45 arranged to face each other are integrally connected through the conductive film 31B formed on the surface of the remaining portion 31A.

In this way, in the step of patterning the conductive film 31 in the manufacturing steps of the semiconductor integrated circuit device 10 described in Embodiment 1, the conductive film 31 is patterned to form the remaining portion 31A, thereby naturally forming the remaining portion 31A. Connecting part 59 .

FIG. 45 is a cross-sectional view taken along line XLV-XLV in FIG. 18 , showing a manufacturing step subsequent to the manufacturing step of the semiconductor integrated circuit device 10 shown in FIG. 44 . As shown in FIG. 45, the conductive film pattern 31a is patterned to expose the region to be the drain region 17, and at the same time, the pad portion 93 is formed.

And, as shown in FIG. 30 , a contact portion 69 is formed on the upper surface of the formed connecting portion 59 . That is, the connection portion 59 is used as a lead-out portion of the memory gate 45 shown in FIG. 2 . Furthermore, the manufacturing steps other than the manufacturing steps of the semiconductor integrated circuit device 10 described above include the manufacturing steps of the semiconductor integrated circuit device 10 described in the first embodiment.

According to the manufacturing method of the semiconductor integrated circuit device 10 according to the second embodiment, it is not necessary to provide a step of forming the lead-out portion of the memory gate 45, and the total number of steps and the number of masks in the manufacturing steps of the semiconductor integrated circuit device 10 can be reduced. . Furthermore, the residual portion 31A is formed during the patterning step of the conductive film 31 in the manufacturing steps of the semiconductor integrated circuit device 10 of the first embodiment, and the manufacturing method of the semiconductor integrated circuit device 10 of the second embodiment can be obtained in the same manner as in the first embodiment. 1 of the semiconductor integrated circuit device 10 of the same function and effect.

(Embodiment 3)

A semiconductor integrated circuit device 10 according to Embodiment 3 will be described with reference to FIGS. 46 to 52 . In addition, the same reference numerals are assigned to the same configurations as those of the semiconductor integrated circuit device 10 according to Embodiment 1 or Embodiment 2, and description thereof will be omitted.

FIG. 46 is a plan view of the semiconductor integrated circuit device 10 of the third embodiment. In FIG. 46, the semiconductor integrated circuit device 10 has: an isolation region 90 selectively formed on the main surface of the semiconductor substrate 13 where the memory cell region 67 is located; a strip-shaped active region 91 defined by the isolation region 90; The source region 15 and the drain region 17 formed on each isolation region 91; a plurality of control gates (first gates) 42A, 42B formed in a ring shape; the source regions of the control gates 42A, 42B via the insulating film 44 Ring-shaped memory gates (second gates) 45A and 45B are formed on the side surface on the (first impurity region) 15 side.

The active region 91 is formed in a stripe shape extending in the width direction of the control gates 42A, 42B and the memory gate 45 , and formed at regular intervals in the direction in which the control gates 42A, 42B and the memory gates 45A, 45B extend. indivual.

In addition, source regions 15 are formed at both ends of the strip-shaped active region 19 , and drain regions 17 are formed at the center of the strip-shaped active region 91 . Also, a channel region 75 is formed between the drain region 17 and the source region 15 of the active region 91 .

Therefore, active regions 91 adjacent to each other in the long-axis direction of active regions 91 are arranged such that source regions 15 face each other. Furthermore, a contact portion (voltage application portion) 51 is formed on each source region 15 . This voltage applying unit is connected to upper layer wirings 48B and 48C.

In this way, a voltage is applied to each source region 15 through a contact portion or wiring made of barrier metal or tungsten having a resistance lower than that of the active region, thereby reducing the wiring resistance.

Therefore, fluctuations in the voltage applied to the source region 15 can be suppressed depending on the position of the selected memory cell transistor, and a desired voltage can be applied to the source region 15 of any memory cell transistor, thereby suppressing malfunction.

Here, when the source regions 15 of the respective memory cell transistors are connected through the active region, in order to apply a desired voltage to the source regions of the respective memory cell transistors during the write operation, it is necessary to apply a large voltage to the common source region. Voltage. However, when a large voltage is applied in the state where the source region 15 of a plurality of memory cell transistors is shared, a write operation is caused even to the non-selected memory cell transistors, and malfunctions are likely to occur. On the other hand, as described above, each source region is formed as an independent source region, and a voltage is applied through a wiring whose resistance is lower than that of the active region, whereby malfunction can be suppressed.

The control gates 42A, 42B are formed in a ring shape passing through the channel region 75 of the adjacent active region 91 in the long axis direction of the active region 91 and surrounding the source region 15 of any one of the adjacent active regions 19 . Recesses 96 are formed on side surfaces of the control gates 42A and 42B on the source region 15 side. The recesses 96 are formed on both ends of the control gates 42A and 42B in the longitudinal direction, and are located on the upper surface of the isolation region 90 . In addition, pad portions 93 are formed at both ends in the longitudinal direction of the control gates 42A, 42B, and contact portions (voltage application voltage applying Department) 68.

The memory gates 45A, 45B are formed on inner surfaces of the control gates 42A, 42B, and are formed in a ring shape so as to surround the source region 15 similarly to the control gates 42A, 42B. Pad portions (connection portions) 59 for applying a voltage to the memory gates 45A, 45B are formed at both end portions in the longitudinal direction of the memory gates 45A, 45B. The connecting portion 59 is formed by mixing a part of the conductive film constituting the memory gates 45A and 45B into the concave portion 96 .

Fig. 47 is a cross-sectional view taken along line XLVII-XLVII of Fig. 46 . As shown in FIG. 47 , memory cell transistor 27A including control gate 42A and memory cell transistors 27B and 27C including control gate 42B are formed on the main surface of semiconductor substrate 13 . Also, the memory cell transistors 27A and 27B share the drain region 17 . A contact portion 49 having a barrier metal 39 and a tungsten film 50 is formed on the common drain region 17 .

The contact portion 49 is connected to the upper layer wiring 48B, and is also connected to the bit line 95 via the contact portion 94 .

Further, adjacent memory cell transistors 27B including control gate 42B formed in a ring shape are isolated from each other by isolation region 90 . 48 is a cross-sectional view taken along line XLVIII-XLVIII in FIG. 46 , and is a cross-sectional view near the pad portion 59 . As shown in FIG. 48 , the recess 96 is located on the isolation region 90 , and the insulating film 44 is formed on the inner surface of the recess 96 and the upper surface of the isolation region 90 where the recess 96 is located.

Furthermore, the memory gate 45 is formed in the shape of a sidewall on the inner side of the concave portion 96 , and the memory gate 45 formed on one inner side of the concave portion 96 and the memory gate 45 formed on the other inner side are in contact with each other.

A contact portion 69 is formed via the metal silicide film 37 on the upper surfaces of the memory gates 45 that are in contact with each other in the concave portion 96 .

In this way, the pad portion 59 of the contact portion 69 is constituted by the memory gates 45 formed in the concave portion 96 to be in contact with each other.

In addition, the width of the concave portion 96 is smaller than twice the width of the memory gate 45 shown in FIG. 46 , and is smaller than 60 nm.

In addition, the structure other than the above-mentioned structure is the same as that of the semiconductor integrated circuit device 10 of Embodiment 1 or Embodiment 2 shown. FIG. 83 is a circuit diagram of the semiconductor integrated circuit device 10 constructed as described above, and FIG. 84 is a schematic diagram thereof.

As described above, each operation of the semiconductor integrated circuit device 10 configured will be described. FIG. 80 is an operation diagram during a read operation of the semiconductor integrated circuit device 10 according to the third embodiment. In FIG. 80 and FIG. 46, a voltage of about 0 V is applied to the source region 15 of the selected memory cell. Then, a voltage of, for example, about 0 V is applied to the memory gate 45 of the selected memory cell. Then, a voltage of, for example, about 1.5 V is applied to the control gate 42 of the selected memory cell, a voltage of, for example, about 1 V is applied to the drain region 17 , and a voltage of about 0 V is applied to the semiconductor substrate 13 .

Fig. 81 is an operation diagram of a writing operation. As shown in FIG. 81 , a voltage of, for example, about 6 V is applied to the source region 15 of the selected memory cell, and a voltage of, for example, about 11 V is applied to the memory gate 45 . Then, a voltage of approximately 1V is applied to the control gate 42 of the selected memory cell, a voltage of approximately 0.8V to 1.5V is applied to the drain region 17, and a voltage of approximately 0V is applied to the semiconductor substrate 13.

Fig. 82 is an operation diagram of an erasing operation. As shown in FIG. 82, a voltage of, for example, about 6 V is applied to the source region 15 of the selected memory cell, a voltage of, for example, 3 V is applied to the memory gate 45, and 0 V is applied to the drain region 17 and the control gate. voltage around. Then, a voltage of about 0 V is applied to the semiconductor substrate 13 . Here, a voltage of, for example, about -6V is applied to the memory gate 42 of the unselected memory cell.

A method of manufacturing the semiconductor integrated circuit device 10 of the third embodiment configured as described above will be described.

FIG. 49 is a plan view of a step corresponding to the first step of the manufacturing steps of the semiconductor integrated circuit device 10 according to the first embodiment shown in FIGS. 6 and 7 .

As shown in FIG. 49 , an isolation region 90 is formed on the main surface of the semiconductor substrate 13 where the memory cell region 67 is located, and a plurality of active regions 91 are defined.

FIG. 50 is a plan view showing a manufacturing step corresponding to the third step of the semiconductor integrated circuit device 10 according to Embodiment 1 shown in FIGS. 10 and 11 .

As shown in FIG. 50, a conductive film pattern 31a having an opening 31b in a region where the source region 15 is located in each active region 91 is formed. At this time, the recessed portions 96 are simultaneously patterned on both end portions in the longitudinal direction of the opening portion 31b.

FIG. 51 is a plan view showing a manufacturing step corresponding to the aforementioned FIG. 16 and FIG. 17 . As shown in FIG. 51 and FIG. 16, an insulating film 44 is formed on the surface of the conductive film pattern 31a and the main surface of the semiconductor substrate 13 where the opening 31b is located. At this time, the conductive film 34 is formed both on the inner surface of the concave portion 96 and on the isolation region 90 where the concave portion 96 is located.

Then, the conductive film 34 is deposited (formed) on the upper surface of the insulating film 44 , the conductive film 34 is etched, and the memory gate 45 is formed on the surface of the opening 31 b via the insulating film 34 .

At this time, as shown in FIGS. 51 and 48 , the conductive film 34 constituting the memory gate 45 remains in the concave portion 96 in a sidewall shape, and the pad portion 59 is naturally formed. Here, when the pad portion 59 is formed by photolithography, it is necessary to have a margin for the formed pad portion and the control gate, or to have a margin for occurrence of a defect or the like. On the other hand, as described above, in the case of natural formation, there is no need for such a margin, and the semiconductor integrated circuit device 10 can be miniaturized compared with the case of forming the pad portion by photolithography.

FIG. 52 is a plan view showing a manufacturing step after the manufacturing step shown in FIG. 51. As shown in FIG. 52, the conductive film pattern 31a is patterned to form the control gate 42, and at the same time, the gates of other peripheral circuit transistors are also patterned.

In addition, steps other than the manufacturing steps described above are the same as those of the first and second embodiments.

(Embodiment 4)

A semiconductor integrated circuit device 10 according to Embodiment 4 will be described with reference to FIGS. 53 to 66 . FIG. 53 is a plan view of, for example, a RAM region 62 of the semiconductor integrated circuit device 10 according to the fourth embodiment. As shown in FIG. 53 , a plurality of SRAM memory cells M1 to M6 are formed on the main surface of the semiconductor substrate 13 where the RAM region 62 is located.

The respective memory cells M1 to M6 are arranged on the main surface of the semiconductor substrate 13 in line symmetry with each other. The structure of the memory cell M1 of the SRAM will be briefly described using FIG. 54 . The memory cell M1 has a full CMOS cell structure and has a first inverter and a second inverter. FIG. 54 shows an equivalent circuit of this memory cell M1. The structure of the memory cell M1 of the SRAM will be briefly described using FIG. 54 . The memory cell M1 has a full CMOS cell structure and has first and second inverters and two access NMOS transistors N3 and N4.

The first inverter includes a first driver MOS transistor N1 and a first load PMOS transistor P1, and the second inverter includes a second driver MOS transistor N2 and a second load PMOS transistor P2.

The first inverter and the second inverter form a flip-flop connected to mutual input and output, the source of the first access NMOS transistor N3 is connected to the first storage node Na of the flip-flop, and the second access NMOS transistor The source of N4 is connected to the second storage node Nb of the flip-flop.

The storage node Na is connected to the bit line BL1 through the first access NMOS transistor N3, and the storage node Nb is connected to the bit line BL2 through the second access NMOS transistor N4. Furthermore, the gates of the first and second access NMOS transistors N3 and N4 are connected to the word line WL, and the sources of the first and second load PMOS transistors P1 and P2 are connected to the power supply line VDD.

Next, the layout of the memory cell M1 of the full CMOSSRAM will be described. As shown in FIG. 53, impurities are introduced and P well regions are provided on both sides of the N well region. Furthermore, an isolation region 120 is selectively formed on the main surface of the semiconductor substrate 13, and active regions 102a, 102b, 102c, and 102d are defined in the P well region and the N well region. In addition, N-type impurities such as phosphorus are selectively implanted in the active regions 102a, 102b, 102c, and 102d formed in the P well region to form impurity diffusion layers, and boron is selectively implanted in the active regions formed in the N well region. and other P-type impurities to form an impurity diffusion layer. In the present description, the active regions 102a, 102b, 102c, and 102d are regions including a region serving as a source/drain of a transistor and a region (substrate portion) of an opposite conductivity type to the region located between the regions.

Both the active regions 102a, 102d and 102b, 102c have linear shapes and extend in the same direction (extending direction of the P well region and the N well region). Thereby, variations in the width or formation position of the P-well region or N-well region can be reduced.

The memory cell M1 of this embodiment is composed of six MOS transistors. Specifically, the memory cell M1 is composed of first and second driver NMOS transistors N1 and N2, first and second access NMOS transistors N3 and N4, and first and second load PMOS transistors P1 and P2.

The first and second access NMOS transistors N3 and N4 and the first and second driver NMOS transistors N1 and N2 are respectively formed on the P well region on both sides of the N well region, and the first and second load PMOS transistors P1 and P2 are formed on the central N-well region. The first access NMOS transistor N3 is formed at the intersection of the impurity diffusion region 102a1 and the polysilicon wiring 103a, and the second access NMOS transistor N4 is formed at the intersection of the active region 102d and the polysilicon wiring 103d. The impurity diffusion region 102a1 includes In the source/drain region, the active region 102d includes a source/drain region.

The first driver NMOS transistor N1 is formed at the intersection of the impurity diffusion region 102a1 and the polysilicon wiring 103b, and the second driver NMOS transistor N2 is formed at the intersection of the active region and the polysilicon wiring 103c. The region of the drain, the active region contains the region that becomes the source/drain.

The first load PMOS transistor P1 is formed at the intersection of the impurity diffusion region 102b1 and the polysilicon wiring 103b, and the second access PMOS transistor P2 is formed at the intersection of the active region 102c and the polysilicon wiring 103c. The active region 102c includes a source/drain region.

The polysilicon interconnections 103a to 103d serve as gates of the respective MOS transistors, and extend in the same direction as shown in FIG. 53 . That is, the polysilicon interconnections 103a to 103d extend in a direction (horizontal direction in FIG. 53 ) perpendicular to the direction in which the P-well region and the N-well region extend (the vertical direction in FIG. 53 ), and extend in the direction in which the P-well region and the N-well region are aligned.

An interlayer insulating film (not shown) is formed so as to cover the active regions 102a to 102d and the polysilicon wirings 103a to 103d, and contact portions 104a to 104l are formed to reach the active regions 102a to 102d, An impurity diffusion layer that functions as a source/drain. Conductive layers for connection to upper-layer wiring are embedded in the contact portions 104a to 104l.

In addition, the contact portions 104a and 104l are gate contacts reaching the gate, the contact portions 104f and 104g are shared contacts reaching the impurity diffusion layer and the polysilicon wiring, and the other contact portions 104b, 104c, 104d, and 104e , 104h, 104i, 104j, 104k are diffusion contacts reaching the region of the impurity diffusion layer.

In FIG. 53, these transistors share the N-type impurity diffusion region serving as the drain of the first driver MOS transistor N1 and the N-type impurity diffusion region serving as the drain of the first access NMOS transistor N3. Through the contact portion 104c, the first metal wiring 105a, and the contact portion (common contact) 104f formed on the N-type impurity diffusion region, the drain of the first driver NMOS transistor N1 and the drain of the first access NMOS transistor N3 are connected to each other. The drain of the first load transistor P1 is connected. Its terminal becomes the storage node Na in the equivalent circuit diagram shown in FIG. 54 .

Similarly, the N-type impurity diffused region serving as the drain of the second driver NMOS transistor N2 and the N-type impurity diffused region serving as the drain of the second access NMOS transistor N3 pass through the contact portion 104j, the first metal wiring 105b, and the contact portion (Common contact) 104g is connected to the drain of the second load transistor P2. This terminal becomes the storage node Nb in the equivalent circuit diagram shown in FIG. 54 .

In addition, other memory cells may be configured similarly to the memory cell M1 configured in this way. Here, memory cell M2 is adjacent to memory cell M1 in the direction in which polysilicon interconnection 103b extends, and memory cell M3 is adjacent to memory cell M1 in the direction in which active regions 102a to 102d extend. Also, similarly, the memory cell M4 is adjacent to the memory cell M3 in the direction in which the polysilicon wiring 103b extends.

Here, the distance between the end face of the polysilicon interconnection 103b of the memory cell M1 and the end face of the polysilicon interconnection 103b of the memory cell M2 adjacent to the memory cell M1 is, for example, about 100 nm to 120 nm. In addition, the distance between the impurity region 102 a of the memory cell M1 and the impurity region 102 a of the memory cell M2 is, for example, about 200 nm to 220 nm. Further, an insulating film 44 is formed on the end surfaces of the polysilicon interconnections 103a facing each other between the polysilicon interconnections 103a.

In addition, the distance between the end surface of the polysilicon wiring 103b and the end surface of the polysilicon wiring 103d is also about 100 nm to 120 nm. Furthermore, the insulating film 44 is also formed on the end surfaces of the polysilicon wirings 103b and 103d where the polysilicon wiring 103d and the polysilicon wiring 103b face each other.

Fig. 55 is a cross-sectional view taken along line LV-LV in Fig. 53 . As shown in FIG. 55, the polysilicon interconnection 103b of the memory cells M1 and M2 is formed on the active region 102a via an insulating film 30 such as a silicon oxide film.

Also, the boundary portion of the polysilicon wiring 103b of the memory cell M1 and the polysilicon wiring 103b of the memory cell M2 is located on the isolation region 90 between the active region 102a of the memory cell M1 and the active region 102a of the memory cell M2. The insulating film 44 is also formed on the surface from the isolation region between the polysilicon wiring 103b of the memory cell M1 and the polysilicon wiring 103b of the memory cell M2 to the front ends of the polysilicon wirings 103b, 103b. Insulation between the polysilicon wiring 103b of the memory cell M1 and the polysilicon wiring 103b of the memory cell M2 is ensured by the protective mask 44 . Further, a sidewall-shaped conductive film 34 is formed via an insulating film 44 on the front end surface of the polysilicon wiring 103b at the boundary portion between the polysilicon wirings 103b.

A method of manufacturing the semiconductor integrated circuit device 10 configured as described above will be described with reference to FIGS. 56 to 66 . 56 is a plan view showing the first step of the manufacturing steps of the semiconductor integrated circuit device 10 according to Embodiment 4, and is the first step of the semiconductor integrated circuit device 10 according to Embodiment 1 shown in FIGS. 6 and 7. The step corresponding to the step. In addition, FIG. 57 is a cross-sectional view taken along line LVII-LVII of FIG. 56 . As shown in FIG. 57, an isolation region 120 is selectively formed on the main surface of the semiconductor substrate 13 to define an active region, and further define a P well region and an N well region.

Then, impurities are selectively introduced into the respective P-well regions and N-well regions to form impurity regions 102a to 102d.

FIG. 58 is a plan view showing the manufacturing steps of the semiconductor integrated circuit device 10 after the manufacturing steps shown in FIG. Plan view of the fabrication steps corresponding to Step 2. FIG. 59 is a cross-sectional view taken along line LIX-LIX of FIG. 58 .

As shown in FIGS. 58 and 59, thermal oxidation treatment is performed on the main surface of the semiconductor substrate 13 to form an insulating film 30 made of a silicon oxide film or the like.

Also, a conductive film 31 made of a polysilicon film or the like is deposited on the main surface of the semiconductor substrate 13 via the insulating film 30 .

FIG. 60 is a plan view of the manufacturing steps of the semiconductor integrated circuit device 10 after the manufacturing steps shown in FIG. Floor plan of the corresponding steps. FIG. 61 is a cross-sectional view taken along line LXI-LXI of FIG. 60 .

As shown in FIG. 60 and FIG. 10, a conductive film pattern 31a is formed on the ROM region 63, and the conductive film pattern 31a has: an opening 31b located in the region of the source region of the memory cell transistor formed as a MONOS structure; a plurality of openings 31c to 31f are formed in the area shown in the RAM area 62 shown in FIG. 60 .

Specifically, the conductive film pattern 31a having the following parts is formed: an opening 31c located in the region between the polysilicon wirings 103b of the adjacent memory cells M1 to M6; an opening 31d located in the following region: area, that is, the area between the polysilicon wiring 103a and the polysilicon wiring 103c; the opening 31e, which is located in the area between the polysilicon wiring 103b and the polysilicon wiring 103d; and the opening 31f, which is located in the area : A region located between the polysilicon interconnections 103c of adjacent memory cells M1 to M6.

In FIG. 53, the opening 31c spans from a region between the formed polysilicon interconnection 103b of the memory cell M1 and the polysilicon interconnection 103b of the memory cell M2 to the polysilicon interconnection 103b of the memory cell M3 and the polysilicon interconnection 103b of the memory cell M4. extend the area in between. That is, the opening 31c is formed to extend in the direction in which the active regions 102a to 102d extend. In addition, the openings 31d, 31c, and 31f are also formed elongated in the direction in which the active regions 102a to 102d extend, similarly to the opening 31c. Thus, the conductive film pattern 31a having the elongated openings 31c to 31f can be easily manufactured by a stepper equipped with a laser such as a KrF excimer laser or an ArF excimer laser as a light source.

62 is a cross-sectional view showing a manufacturing step after the manufacturing step of the semiconductor integrated circuit device 10 shown in FIG. The cross-sectional view of the fabrication step corresponding to step 5.

As shown in FIG. 62, an insulating film composed of a so-called ONO film is formed on the surface of the conductive film pattern 31a, the inner wall surfaces of the openings 31c to 31f, and the upper surface of the isolation region 120 where the openings 31c to 31f are located. 44. And, the conductive film 34 is deposited (formed) on the conductive film pattern 31 a via the insulating film 44 . At this time, the conductive film 34 is also filled in the openings 31c to 31f.

63 is a cross-sectional view of a manufacturing step after the manufacturing step shown in FIG. 62, and is a manufacturing step corresponding to the sixth step of the semiconductor integrated circuit device 10 according to Embodiment 1 shown in FIGS. 16 and 17. Cutaway diagram of the steps. FIG. 64 is a plan view of the manufacturing steps shown in FIG. 63 .

As shown in FIG. 63 , the conductive film 34 is etched. As a result, as shown in FIG. 64 , storage gate 45 is formed on the main surface of semiconductor substrate 13 where ROM region 63 is located. At this time, the sidewall-shaped conductive film 34 is formed on the inner side surfaces of the openings 31c to 31f among the openings 31c to 31f.

An insulating film 44 is formed between the spacer-shaped conductive film 34 and the conductive film pattern 31a to ensure an insulating state between the conductive film pattern 31a and the conductive film 34 .

65 is a plan view of a manufacturing step after the manufacturing step shown in FIG. 64, and is a manufacturing step corresponding to the seventh step of the semiconductor integrated circuit device 10 according to the first embodiment shown in FIGS. 18 and 19. floor plan. FIG. 66 is a cross-sectional view taken along line LXV-LXV of FIG. 65 . As shown in FIGS. 65 and 66, the conductive film pattern 31a is patterned to form polysilicon wirings 103a to 103d. The step of forming the polysilicon wirings 103a to 103d first forms a resist mask on the entire upper surface of the conductive film pattern 31a. Then, a photomask 200 is disposed above the resist mask, and an exposure process is performed on the resist mask.

A plurality of opening patterns 200a, 200b are formed on the photomask 200, and the plurality of opening patterns 200a, 200b extend along the direction in which the polysilicon wirings 103a to 103d extend.

The opening pattern 200a is made, for example, to connect the polysilicon wiring 103a and the polysilicon wiring 103c of the memory cell M1, and the polysilicon wiring 103a and the polysilicon wiring 103c of the memory cell M2.

In addition, opening pattern 200b is formed to connect polysilicon line 103b, polysilicon line 103d of memory cell M1, and polysilicon line 103b, polysilicon line 103b, and polysilicon line 103d of memory cell M2, for example.

Photolithography is performed using such a photomask 200 to pattern the conductive film pattern 31a. At this time, the openings 31 c to 31 f have already been formed on the main surface of the formed semiconductor substrate 13 . Therefore, even if the conductive film 31a is patterned using the photomask 200 as described above, it can be isolated by the insulating film 44 formed on the inner wall surfaces of the openings 31c to 31f. For example, the polysilicon wiring 103b of the memory cell M1 and the polysilicon wiring 103b of the memory cell M2 are separated by the insulating film 44 formed on the inner peripheral surface of the opening 31c. In addition, the polysilicon wiring 103a and the polysilicon wiring 103c are also separated by the insulating film 44 formed on the inner peripheral surface of the opening 31d. In addition, the polysilicon wiring 103b and the polysilicon wiring 103d are also separated by the insulating film 44 formed on the inner peripheral surface of the opening 31e. In addition, the polysilicon wiring 103c of the memory cell M1 is isolated from the polysilicon wiring 103c of the memory cell adjacent to the memory cell M1 by the insulating film 44 formed on the inner peripheral surface of the opening 31c.

In this way, the openings 31c to 31f are formed in advance in the boundary regions between the polysilicon wirings 103a to 103d, and the insulating film 44 is formed on the inner wall surfaces of the openings 31c to 31f, whereby the polysilicon wirings 103a to 103d can be naturally divided. 103f. Therefore, when photolithography is performed on the conductive film pattern 31a, patterning can be performed so that the adjacent polysilicon wirings 103a to 103d in the long-axis direction are connected.

Here, the width of the opening 31 c in the minor axis direction (the direction in which the polysilicon wirings 103 a to 103 d extend) is made, for example, 100 nm to 120 nm. In addition, the distance between the opening edge of the opening 31c and the active region 102a can be made, for example, about 50 nm.

Therefore, the distance between the active region 102 a of the memory cell M1 and the active region 102 a of the memory cell M2 can be made to be about 200 nm to 220 nm.

On the other hand, when patterning the polysilicon wirings 103a to 103d in the state where the openings 31c to 31f are not formed, first, it is necessary to ensure the formation of the polysilicon wirings 103a to 103d due to poor formation of the formed polysilicon wirings 103a to 103d. For the tolerance between polysilicon wirings 103a to 103d, for example, the distance between each polysilicon wiring 103a to 103d needs to be made to be about 120nm, for example. Furthermore, the distance between the active regions 102 a to 102 d needs to be secured at, for example, about 100 nm in consideration of tolerances such as mask shift and formation failure. Therefore, for example, the distance between the active region 102 a of the memory cell M1 and the active region 102 a of the memory cell M2 is, for example, about 300 nm to 320 nm.

In particular, P well regions are formed under the opening 31c and on the main surface of the semiconductor substrate 13 on both sides of the opening 31c, and well regions of the same conductivity type are formed. Therefore, the distance between the active region 102a of the memory cell M1 and the active region 102a of the memory cell M2 is completely determined by the distance between the polysilicon wirings 103b.

Therefore, by reducing the distance between the polysilicon interconnections 103 b, the distance between the active regions 102 a can be reliably reduced, which greatly contributes to miniaturization of the semiconductor integrated circuit device 10 . Thus, according to the method of manufacturing the semiconductor integrated circuit device 10 of the fourth embodiment, the distance between the polysilicon wirings of the respective SRAM transistors can be reduced, and the miniaturization of the semiconductor integrated circuit device 10 can be realized. In addition, in Embodiment 4, the case of applying to the SRAM formed in the RAM region 62 of the semiconductor integrated circuit 10 was described, but it is not limited to the case of applying to such a hybrid microcomputer. In addition, it is applicable not only to the case of SRAM but also to the case where a plurality of gates are formed, and the distance between the gates can be reduced.

A modified example of the fourth embodiment will be described with reference to FIGS. 34 to 37 and FIGS. 67 to 79 . 67 is a plan view of a peripheral circuit region of a semiconductor integrated circuit device 10 according to a modified example of the fourth embodiment, and FIG. 68 is a cross-sectional view taken along line LXV111-LXVIII of FIG. 67 . As shown in this FIG. 67, formed on the main surface of the semiconductor substrate 13 where the peripheral circuit region is located: gates (wiring) 42a, 42b extending toward one direction; and a gate (wiring) 42c located on the gate 42a, 42b end side, and extend in a direction intersecting with the direction in which the gate electrodes 42a, 42b extend.

A boundary region of the gate electrodes 42 a , 42 b and the gate electrode 42 c is formed on an isolation region 52 formed on the main surface of the semiconductor substrate 13 . Furthermore, as shown in FIG. 68 , a gate 42 b is formed on the upper surface of the active region 53 through an insulating film 54 , and a part of the gate 42 b reaches on the isolation region 52 . On the end surface of the gate 42b, the portion of the side surface of the gate 42c that faces the gate 42b, and the surface of the isolation region 52 located at the boundary between the gate 42b and the gate 42c, an ONO film, for example, is formed. insulating film 44 . Therefore, isolation between the gate 42b and the gate 42c is ensured. In addition, a sidewall-shaped conductive film 45 is formed on the end surface of the gate 42b through the insulating film 44, and a sidewall-like conductive film 45 is also formed on the peripheral surface of the gate 42c that faces the gate 42b through the insulating film 44. wall-shaped conductive film 45 .

FIG. 69 is a plan view showing the first manufacturing step of the semiconductor integrated circuit device 10 of this modified example, which is similar to the first manufacturing step of the semiconductor integrated circuit device 10 of the first embodiment shown in FIGS. 6 and 7. corresponding steps. FIG. 70 is a sectional view of the above-mentioned FIG. 69 .

As shown in FIGS. 69 and 70 , isolation regions 52 are selectively formed on the main surface of semiconductor substrate 13 to define active regions 53 .

FIG. 71 is a plan view showing a manufacturing step subsequent to the manufacturing step shown in FIG. 69, and corresponds to the second step of the semiconductor integrated circuit device 10 according to Embodiment 1 shown in FIGS. 8 and 9. floor plan. Furthermore, FIG. 72 is a sectional view of FIG. 71 .

As shown in FIGS. 71 and 72 , an insulating film 54 is formed on the main surface of the semiconductor substrate 13 , and a conductive film 31 is deposited (formed) on the upper surface of the insulating film 54 .

34 and 73 are plan views of the peripheral circuit region in the patterning step of the conductive film 31 a of the semiconductor integrated circuit device 10 , and FIG. 74 is a cross-sectional view of FIG. 73 . As shown in FIG. 34, FIG. 73, and FIG. 74, in the patterning step of the conductive film, a conductive film pattern 31a is formed, and the conductive film pattern 31a is formed as a boundary region between adjacent gates of the formed peripheral circuit transistor. There is an opening 80 in the region of 83 .

75 is a cross-sectional view showing a manufacturing step after the manufacturing step of the semiconductor integrated circuit device 10 shown in FIG. The cross-sectional view of the step corresponding to step 5. As shown in FIG. 75, the insulating film 33 is formed on the surface of the opening 80 and the surface of the conductive film pattern 31a. Also, a conductive film 34 is deposited on the upper surface of this insulating film 33 . Furthermore, in the fifth step of forming the memory gate 45 , the conductive film 34 is formed on the surface of the insulating film 44 formed on the surface of the opening 80 . 35 and 76 are plan views of the peripheral circuit region in the seventh step of forming the control gate and the gate. 77 is a sectional view of FIG. 76 , and FIG. 36 is a plan view of the peripheral circuit region of the photomask 72 . As shown in FIG. 35, FIG. 76, and FIG. 77, in the seventh step of the semiconductor integrated circuit device 10, an insulating film 44 is formed on the surface of the opening 80, and on the surface inside the opening 80 of the surface of the insulating film, The conductive film 34 is formed.

In this way, the etching mask 72 shown in FIG. 36 is placed on the upper surface side of the opening 80 where the insulating film 44 and the conductive film 34 are formed, and patterning is performed by photolithography. In addition, FIG. 37 is a plan view of the peripheral region when the gate of the peripheral circuit region is formed. As shown in FIG. 36 , an opening 81 is formed in the etching mask 72 .

In FIG. 37 , this opening 81 is formed so that the formed gate electrodes 42 a , 42 b , and 42 c are connected to each other in the isolation region 83 shown in FIG. 35 . Furthermore, the opening 81 of the etching mask 72 shown in FIG. 36 is arranged on the upper surface side of the conductive pattern 31a and in the area where the gate electrodes 42a, 42b, and 42c are formed. In this way, when the etching mask 72 is arranged, the part of the opening 81 that isolates the region 83 is located on the upper surface of the opening 80 shown in FIG. 35 .

FIG. 78 is a plan view showing a manufacturing step after the manufacturing step shown in FIG. 76 , and FIG. 79 is a cross-sectional view of FIG. 78 . In these FIGS. 78 , 79 , and 37 , when an etching mask 72 is placed and patterning is performed by photolithography, the gates 42 a , 42 b , and 42 c are isolated from the openings 80 shown in FIG. 35 , respectively. That is, adjacent gate electrodes 42 a , 42 b , and 42 c are formed on both sides of the opening 80 . Here, the insulating film 44 is formed on the surface of the opening 80, so the insulating film 44 is formed on the surface of the formed gates 42a, 42b, 42c on the side of the isolation region 83, and the isolation region 83 of the insulating film 44 is formed. The conductive film 34 is formed on the surface of the side. Since the insulating film 44 is formed on the surface of the formed gates 42a, 42b, and 42c on the isolation region 83 side, the gates 42a, 42b, and 42c are electrically isolated.

In this way, in the seventh step of forming the gate, the opening 80 is formed in advance on the part of the isolation region 83 of the gate 42a, 42b, 42c in the conductive pattern 31a, and an insulating layer is formed on the surface of the opening 80. film44. Therefore, the openings 82 formed on the etching mask 72 do not need to be formed so as to isolate the formed gates 42 a , 42 b , and 42 c , but can be formed so as to be connected in the isolation region 83 . In this way, since photolithography can be performed to connect the gates 42a, 42b, and 42c, there is no need to provide a margin between the gates 42a, 42b, and 42c unlike the case of forming isolated gates by photolithography. In this way, according to the method of manufacturing the semiconductor integrated circuit device 10 of the fourth embodiment, the distance between the gate electrodes 42a, 42b, and 42c can be made closer, and the area can be reduced.

In addition, Embodiment 4 is applied to gates of peripheral circuit transistors, but is not limited thereto, and can also be applied to control gates of memory cell transistors or between various wirings. That is, it is a method of manufacturing a semiconductor integrated circuit device having the steps of: forming a conductive film on the main surface of a semiconductor substrate; forming a conductive pattern formed on an isolation region of the formed wiring in the conductive film an opening; forming an insulating film so as to cover the conductive pattern; patterning the insulating film and the conductive pattern using an etching mask to form wiring, and the etching mask has a mode of connecting the formed wiring in the isolation region and the opening formed. According to such a method of manufacturing a semiconductor integrated circuit device, compared with the case where wiring is formed by ordinary photolithography, the space between wirings becomes shorter and the area can be reduced.

The present invention is suitable for a mixed-load microcomputer equipped with a flash memory of a MONOS (Metal Oxide Nitride Oxide Silicon) structure.

Embodiments of the present invention have been described above, but the disclosed embodiments should be considered as examples and not limited thereto. The scope of the present invention is shown by the scope of the claims, and all modifications within the scope of the claims and equality are included.

Claims (8)

1. A method of manufacturing a semiconductor memory device, the semiconductor memory device having: a memory cell area in which a memory cell transistor is formed, and a peripheral circuit area in which a peripheral circuit for controlling the operation of the memory cell transistor is formed, comprising the steps of: selectively forming isolation regions on the main surface of the semiconductor substrate and defining active regions; forming a first insulating film on the active region; forming the first conductive film in the memory cell region; In the memory cell region, the first conductive film is patterned to form a conductive film pattern, and in the conductive film pattern, there is an opening in a region serving as a first impurity region capable of functioning as a source region; introducing impurities into the main surface of the semiconductor substrate by using the conductive film pattern in the memory cell region as a mask; Covering the conductive film pattern, forming a second insulating film capable of accumulating charges formed by the first silicon oxide film, the silicon nitride film and the second silicon oxide film; forming a second conductive film on the second insulating film; In the memory cell area, the second conductive film is etched, and two sidewall-shaped memory gates of the memory cell transistor are simultaneously formed on the side of the opening of the conductive film pattern; In the memory cell region, using the conductive film pattern and the two memory gates as a mask to form the first impurity region; In the memory cell region, the region where the second impurity region that can function as a drain region in the conductive film pattern is located is etched and patterned, and at the same time, the transistor formed on the peripheral circuit region is forming a gate; and Impurities are introduced into the main surface of the semiconductor substrate to form the second impurity region of the memory cell transistor and the source and drain regions of the transistor formed on the peripheral circuit region. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein The step of patterning the first conductive film to form the pattern of the conductive film includes the step of leaving a remaining portion of the first conductive film on a region formed as the first impurity region of the memory cell transistor, The step of forming the second insulating film includes the step of forming the second insulating film so as to cover the remaining portion, The step of forming the memory gate includes: forming a connection portion around the remaining portion, the connection portion being a connection portion that integrally connects the oppositely disposed memory gates, There is also the step of forming a contact portion on the connection portion. 3. A method of manufacturing a semiconductor memory device, the semiconductor memory device having: a memory cell area in which a memory cell transistor is formed, and a peripheral circuit area in which a peripheral circuit for controlling the operation of the memory cell transistor is formed, comprising the steps of: selectively forming isolation regions on the main surface of the semiconductor substrate and defining active regions; forming a first insulating film on the active region; forming a first conductive film on the first insulating film; In the memory cell region, the first conductive film is patterned, an opening is formed in a region of the first impurity region that can function as a source region, and at both sides in the longitudinal direction of the opening, Simultaneous etching of the concave portion on the end side; In the memory cell region, using the conductive film pattern as a mask, introducing impurities into the main surface of the semiconductor substrate; Covering the conductive film pattern, forming a second insulating film that can accumulate charges formed by the first silicon oxide film, the silicon nitride film and the second silicon oxide film; forming a second conductive film on the second insulating film; In the memory cell area, the second conductive film is etched, and sidewall-shaped memory gates of two memory cell transistors are simultaneously formed on the side of the opening of the conductive film pattern; In the memory cell region, using the conductive film pattern and the two memory gates as a mask to form a first impurity region; In the memory cell region, etching the region where the second impurity region that can function as a drain region in the conductive film pattern is located, forming a ring-shaped control gate surrounding the first impurity region ;as well as introducing impurities into the main surface of the semiconductor substrate to form the second impurity region, The first memory gate and the second memory gate of the two memory cell transistors are connected to the ends of the memory cell region by wiring. 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein The step of forming a second conductive film on the second insulating film further includes the step of: filling the concave portion with the second conductive film, thereby forming a pad portion connected to the A voltage application unit that applies a voltage to the memory gate. 5. The method of manufacturing a semiconductor memory device as claimed in claim 3, wherein There is also a step of forming a silicide film on the upper surface of the control gate. 6. The method of manufacturing a semiconductor memory device as claimed in claim 3, wherein The gate of the transistor formed on the peripheral circuit region is formed simultaneously with the formation of the ring-shaped control gate surrounding the first impurity region. 7. A semiconductor memory device, wherein include: semiconductor substrate; an isolation region selectively formed on the main surface of the semiconductor substrate; A first memory cell region and a second memory cell region forming a memory cell transistor adjacent to each other via the isolation region defined by the isolation region; a first impurity region that is formed on the first memory cell region and can function as a source region; a second impurity region that is formed on the first memory cell region and can function as a drain region; a third impurity region that is formed on the second memory cell region and can function as a source region; a fourth impurity region that is formed on the second memory cell region and can function as a drain region; forming a first channel region between the first impurity region and the second impurity region; forming a second channel region between the third impurity region and the fourth impurity region; The first control gate is formed on the main surface located in the second impurity region on the main surface of the semiconductor substrate where the first channel region is located, via a first insulating film. the main surface of the side; The sidewall-shaped first memory gate of the memory cell transistor is formed on the main surface of the semiconductor substrate where the first channel region is located via a second insulating film capable of accumulating charges. a main surface on the side of the first impurity region among the main surfaces of the bottom; The second control gate is formed on the main surface which is located in the fourth impurity region on the main surface of the semiconductor substrate where the second channel region is located, via a third insulating film. the main surface of the side; The sidewall-shaped second memory gate of the memory cell transistor is formed on the main surface of the semiconductor substrate where the second channel region is located via a fourth insulating film capable of accumulating charges. a main surface on the side of the third impurity region among the main surfaces of the bottom; The first connecting portion is formed on the isolation region between the first memory cell region and the second memory cell region, and is connected to the first memory gate formed on the first memory cell region. electrode and the second memory gate formed on the second region; and a second connecting portion formed between the first connecting portions, The second connection portion includes a first conductive film and a second conductive film formed around the first conductive film via a fifth insulating film. 8. A semiconductor memory device comprising: semiconductor substrate; an isolation region selectively formed on the main surface of the semiconductor substrate; an active region defined by the isolation region on the main surface of the semiconductor substrate; a first impurity region formed on the active region and capable of functioning as a source region; a second impurity region formed on the active region and capable of functioning as a drain region; a channel region formed on the main surface of the semiconductor substrate between the first impurity region and the second impurity region; a ring-shaped control gate formed on the upper surface of the channel region on the side of the second impurity region through a first insulating film; a recess formed on a side surface of the control gate on the side of the first impurity region; A ring-shaped sidewall-shaped memory gate is formed on the upper surface of the channel region on the side of the first impurity region through a second insulating film capable of accumulating charges, and is formed on the upper surface of the channel region. on the side of the control grid; a connection part connected to the memory gate and formed in the recess; and A voltage application unit is connected to the connection unit and capable of applying a voltage to the memory gate.

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