CN101593696B - Method for manufacturing semiconductor devices - Google Patents
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- CN101593696B CN101593696B CN2008101127790A CN200810112779A CN101593696B CN 101593696 B CN101593696 B CN 101593696B CN 2008101127790 A CN2008101127790 A CN 2008101127790A CN 200810112779 A CN200810112779 A CN 200810112779A CN 101593696 B CN101593696 B CN 101593696B
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Abstract
A method for manufacturing semiconductor devices includes that: a substrate is prepared, wherein, the substrate comprises a substrate body, a grid arranged on the substrate body and a source region and a drain region which are arranged in the substrate body at the two sides of the grid; a barrier layer covering the substrate is formed; the barrier layer is patterned to expose partial substrate; a primary heat treatment for repairing the substrate is carried out on the substrate covered with the patterned barrier layer; a metal layer is formed to cover the substrate exposed after being patterned; and a secondary heat treatment for forming a metal silicide is carried out on the substrate covered with the metal layer. The invention can reduce the defects such as needle type leakage current, breakthrough leakage current in devices and the like.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of method, semi-conductor device manufacturing method.
Background technology
As shown in Figure 1, the formation method of traditional semiconductor device comprises step 11: as shown in Figure 2, provide substrate, comprise substrate 10, be positioned at grid 20 on the described substrate 10, be positioned at the source region 32 and the drain region 34 of the substrate 10 of described grid 20 both sides; Can comprise light doping section 30 in the described substrate and/or around the side wall 22 of described grid 20 sidewalls; Step 12: as shown in Figure 3, form and cover described suprabasil barrier layer 40; Described barrier layer 40 for example is a silicon rich oxide (SRO); Step 13: as shown in Figure 4, form patterned barrier layer 42; Step 14: as shown in Figure 5, form metal level 60, described metal level 60 covers the substrate that exposes behind the described graphical operation of experience; Step 15: as shown in Figure 6, heat treatment operation is carried out in the substrate with described metal level 60, formed metal silicide 62.
Actual production is found, uses the interior defective that pin type leakage current easily takes place, run through leakage current of device that said method forms.Therefore, under the more and more littler trend of the volume of device,, will reduce the quality and the yield (yield) of device, and increase production cost if still use conventional methods the production device.That how to reduce the problems referred to above becomes those skilled in the art's problem demanding prompt solution.
The notification number of announcing on March 5th, 2003 comprises: provide one to comprise a ground wafer at least for providing a kind of method of making mos field effect transistor in the Chinese patent of " CN1159753C "; Form a trench in ground; Form the bottom of a gate in trench; Form a clearance wall in the both sides of gate and fill up trench; Implanting ions is in the ground of clearance wall both sides; Carry out the first Fast Heating processing procedure in ground, to form source territory and source elongated area; Form a metal level in gate, clearance wall and regions and source; Carry out the second Fast Heating processing procedure on gate and regions and source, to form a metal silicide layer; And remove metal level.The present invention is produced on the gate and the clearance wall of mos field effect transistor in one trench that is pre-formed in ground, to reduce the depth of engagement of source/drain, and reduce the effect that drain voltage causes source electrode and interchannel electrical potential energy to descend and runs through leakage current, avoid in successive process, taking place the defective of pin type leakage current.But, when using said method formation semiconductor device, relating to the significantly change of processing procedure, R﹠D costs are huge.
Summary of the invention
The invention provides a kind of method, semi-conductor device manufacturing method, can reduce pin type leakage current in the device, run through generation of defects such as leakage current.
A kind of method, semi-conductor device manufacturing method provided by the invention comprises:
Substrate is provided, comprises substrate, be positioned at grid on the described substrate, be positioned at the source region and the drain region of the substrate of described grid both sides;
Form the barrier layer that covers described substrate;
Graphical described barrier layer, the expose portion substrate;
The substrate on the barrier layer of cover graphicsization is carried out in order to repair first heat treatment operation of described substrate;
Form metal level, described metal level covers the substrate that exposes behind the described graphical operation of experience;
Substrate with described metal level is carried out in order to form second heat treatment operation of metal silicide.
Alternatively, after form covering the barrier layer of described substrate, before the graphical described barrier layer, also comprise, the step of injecting the 3rd heat treatment operation of ion in described source region and the drain region in order to activate is carried out in the substrate that covers described barrier layer.
Alternatively, the step on graphical described barrier layer comprises:
Adopt dry process that main etching operation is carried out on described barrier layer, removing thickness is the described barrier layer of H0;
Adopt wet process that over-etching operation is carried out on described barrier layer, remove remaining described barrier layer.
Alternatively, carry out described main etching operation after, continue removing thickness is H
1Described barrier layer, H
0With H
1And less than the thickness H on described barrier layer; Alternatively, described barrier layer is a silicon dioxide; Alternatively, described metal level comprises a kind of or its combination in nickel, cobalt, the titanium; Adopt rapid thermal anneal process when alternatively, carrying out the described first and/or the 3rd heat treatment operation; Alternatively, carry out described first and/or the temperature range of the 3rd heat treatment operation be 950 degrees centigrade～1100 degrees centigrade; Alternatively, carry out described first and/or the time range of the 3rd heat treatment operation be 10 seconds～30 seconds.
Compared with prior art, technique scheme has the following advantages:
The method, semi-conductor device manufacturing method that technique scheme provides, by after carrying out graphical described barrier layer operation, increase heat treatment operation, adopt the substrate damage that causes behind the graphical described barrier layer of dry process to repair, can in the heat treatment process of subsequent metal layer, reduce because the metal ion diffusion that lattice dislocation causes, reduce pin type leakage current in the device then, run through generation of defects such as leakage current;
The optional mode of the method, semi-conductor device manufacturing method that technique scheme provides, after increasing heat treatment operation, utilize dry process to remove the ratio on described barrier layer by increase, reducing utilizes wet process to remove the ratio on described barrier layer, can be in reducing device pin type leakage current, run through after the defective such as leakage current, further reduce the generation of etching bottom notch.
Description of drawings
Fig. 1 is for making the schematic flow sheet of semiconductor device in the explanation prior art;
Fig. 2～6 are for making the structural representation of semiconductor device flow process in the explanation prior art;
Fig. 7 adopts first embodiment of the invention for explanation and makes the schematic flow sheet of semiconductor device;
Fig. 8～13 are adopted first embodiment of the invention for explanation and are made the structural representation of semiconductor device flow process.
Embodiment
Although will be described in more detail the present invention as accompanying drawing below, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically as accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 7, the concrete steps of manufacturing semiconductor device comprise:
Step 71: as shown in Figure 8, provide substrate, comprise substrate 100, be positioned at grid 120 on the described substrate 100, be positioned at the source region 142 and the drain region 144 of the substrate 100 of described grid 120 both sides.
Described substrate 100 is including but not limited to the silicon materials that comprise element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).
Comprise in the step that forms grid 120 in the described substrate: deposition grid layer in described substrate; Form patterned resist layer, described patterned resist layer has gate patterns; With described patterned resist layer is mask, and the described grid layer of etching is to form grid 120.Described grid layer comprises polysilicon.Described grid layer also can comprise metal silicide.Described metal silicide by follow-up on polysilicon depositing metal layers, experience annealing process then and obtain.
Can comprise light doping section 140 in the described substrate and/or around the side wall 122 of described grid 120 sidewalls.Described light doping section 140 comprises the lightly doped drain injection, and (Lightly Doped Drain, LDD) district and pocket type (Pocket) ion implanted region, described light doping section 140 are used to define the leakage expansion area, source of MOS device.LDD impurity is positioned at the grid below and is close to the channel region edge, and Pocket impurity is positioned at below, LDD district and is close to the channel region edge, is source/drain region the impurity concentration gradient is provided.
Adopt ion implantation technology to form described light doping section 140, source region 142 and drain region 144.The injection ion packet boracic (B) that relates to, fluoridize inferior boron (BF
2), arsenic (As), phosphorus (P) but or a kind of in other dopant material.
The step that forms described side wall 122 comprises: form the dielectric layer that covers the substrate with grid 120; The described dielectric layer of etching is removed the dielectric layer that covers described grid.Described dielectric layer comprises silica and the silicon nitride or the silicon oxynitride of silica or order stack.Can adopt chemical gas-phase deposition method to form described dielectric layer; But the described dielectric layer of using plasma etching technics etching.
Step 72: as shown in Figure 9, form the barrier layer 160 that covers described substrate.
The mask layer of described barrier layer 160 when forming metal silicide then as the subsequent deposition metal level.Described barrier layer 160 comprises the silicon oxide layer of silicon oxide layer and/or doping.Can adopt chemical gas-phase deposition method to form described barrier layer 160.The silicon oxide layer of described doping includes but not limited to a kind of or its combination in phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), the fluorine silex glass (FSG).
Step 73: as shown in figure 10, form patterned barrier layer 162, the expose portion substrate.
But the graphical described barrier layer of using plasma etching technics.The mask of patterned barrier layer 162 when forming metal silicide then as the subsequent deposition metal level.
In the practice, behind the graphical described barrier layer, form the metal level that covers the substrate that exposes behind the described graphical operation of experience; Then, second heat treatment operation is carried out in the substrate with described metal level, formed metal silicide.Yet actual production is found, experiences the interior defective that pin type leakage current easily takes place, run through leakage current of semiconductor device that this process obtains.
The present inventor thinks after analyzing, the reason that produces the problems referred to above is: cause the substrate damage behind the graphical described barrier layer of using plasma etching technics, then, in the heat treatment process of subsequent metal layer, because lattice dislocation has caused the metal ion diffusion, the diffusion of described metal ion causes pin type leakage current in the described device, runs through leakage current, etc. generation of defects.
Thus, how the present inventor reduces described metal ion diffusion and becomes the direction that reduces above-mentioned defective.And the present inventor's undergoing analysis proposes with the practice back, behind graphical described barrier layer, introduce heat treatment operation, to repair the substrate damage that described etching operation causes, promptly repair the substrate surface lattice dislocation that causes by described etching operation, can reduce the metal ion diffusion that takes place in the heat treatment process of subsequent metal layer.
Step 74: as shown in figure 11, the substrate on the barrier layer 162 of cover graphicsization is carried out in order to repair first heat treatment operation of described substrate.
Adopt rapid thermal annealing (RTA) technology when carrying out described first heat treatment operation.The temperature range of carrying out described first heat treatment operation is 950 degrees centigrade～1100 degrees centigrade, as 1000 degrees centigrade; The time range of carrying out described first heat treatment operation was 10 seconds～30 seconds, as 20 seconds.
After experiencing described first heat treatment operation, described substrate, comprise substrate 102, be positioned at grid 124 on the described substrate 102, be positioned at described grid 124 both sides substrate 102 source region 147 and drain region 148 and cover the barrier layer 164 of described substrate; Perhaps, also comprise light doping section 146 and/or around the side wall 126 of described grid 124 sidewalls.
For verifying the influence of described first heat treatment operation to device performance, the present inventor has carried out batch test.Result of the test shows, after substrate with grid, light doping section, side wall and source region and drain region carried out described first heat treatment operation, utilize electron beam scanning detect to judge, the device count that occurs the problems referred to above in every substrate is reduced to 2 by 18, decreases by 89%.Promptly by after carrying out graphical described barrier layer operation, increase heat treatment operation, can repair and adopt the substrate damage that causes behind the graphical described barrier layer of dry process, then can in the heat treatment process of subsequent metal layer, reduce because the metal ion diffusion that lattice dislocation causes, can reduce pin type leakage current in the device, run through generation of defects such as leakage current.
Step 75: as shown in figure 12, form metal level 180, described metal level 180 covers the substrate that exposes behind the described graphical operation of experience.
Can adopt metallochemistry vapor deposition process or physical vapor deposition process such as plating, sputter to form described metal level 180.Described metal level 180 for example is a cobalt, and described metal level 180 also can be a kind of or its combination in nickel, chromium, titanium, titanium tungsten, tantalum or the nickel platinum.In the practice, different process nodes is selected different metals usually for use, as, be nickel during 90 nanometer processing procedures; Be chromium during 65 nanometer processing procedures.
Step 76: as shown in figure 13, the substrate with described metal level 180 is carried out in order to form second heat treatment operation of metal silicide 182.
The step of carrying out second heat treatment operation comprises:
Step 7601: first annealing operation is carried out in the substrate with described metal level, to form the first phase silicide layer;
Step 7602: remove described metal level;
Step 7603: carry out second annealing operation, to form metal silicide layer.
When carrying out described first annealing operation, temperature range is 250 degrees centigrade～350 degrees centigrade, and as 300 degrees centigrade, the duration scope was 10 seconds～30 seconds, as 20 seconds.Can adopt cmp or its method that combines with wet processing to remove described metal level.When carrying out described second annealing operation, temperature range is 350 degrees centigrade～500 degrees centigrade, and as 400 degrees centigrade, 450 degrees centigrade, the duration scope was 10 seconds～30 seconds, as 20 seconds.
Especially, after form covering the barrier layer of described substrate, before the graphical described barrier layer, also can comprise, the substrate that covers described barrier layer is carried out the step of the 3rd heat treatment operation.Described the 3rd heat treatment operation injects ion in order to thermal annealing is carried out in the source/drain region that forms behind the experience ion implant operation to activate.Described the 3rd heat treatment operation also can be in order to strengthen the uniformity on the described barrier layer that forms.
Adopt rapid thermal annealing (RTA) technology when carrying out described the 3rd heat treatment operation.The temperature range of carrying out described the 3rd heat treatment operation is 950 degrees centigrade～1100 degrees centigrade, as 1000 degrees centigrade; The time range of carrying out described the 3rd heat treatment operation was 10 seconds～30 seconds, as 20 seconds.
In addition, the step on graphical described barrier layer comprises:
Step 7301: adopt dry process that main etching operation is carried out on described barrier layer, removal thickness is H
0Described barrier layer;
Step 7302: adopt wet process that over-etching operation is carried out on described barrier layer, remove remaining described barrier layer.
Preferably, carry out described main etching operation after, continue removing thickness is H
1Described barrier layer, H
0With H
1And less than the thickness H on described barrier layer.
In the practice,, will cause the damage of certain degree at substrate surface if when utilizing dry process to remove described barrier layer fully; And when adopting wet process to remove described barrier layer fully, easily form depression (notching) at the place, base angle of described side wall, therefore, in the traditional handicraft, the method that adopts dry process and wet process to combine is usually removed described barrier layer; That is, at first, adopt dry process to remove the barrier layer of thickness, so that when adopting described dry process to remove described barrier layer, the plasma that relates to can't touch described substrate less than described barrier deposition thickness; Subsequently, adopt wet process to remove remaining described barrier layer, reduce the time that described wet process acts on described substrate, to reduce generation in the place, base angle of described side wall depression.
And adopt method provided by the invention, owing to introduced first heat treatment operation to repair the substrate damage that causes owing to dry process, therefore, the present inventor proposes, and increases the ratio on the barrier layer that utilizes described dry process removal, though will increase the weight of described substrate damage, but, introducing under the prerequisite of first heat treatment operation, increasing the substrate damage that obtains behind the aforementioned proportion, still the substrate damage that can obtain when adopting traditional ratio; In addition, after increasing the ratio on the barrier layer that utilizes described dry process removal, make the thickness on the described barrier layer that the employing wet process is removed reduce, can reduce the time that described wet process acts on described substrate, and then can reduce generation in the place, base angle of described side wall depression.
Particularly, if in the conventional art, the thickness on the described barrier layer of deposition is H, the thickness of using the described barrier layer of dry process removal is H
0The time, adopt wet process to remove the T of being consuming time on remaining described barrier layer
0And when adopting the method that the present inventor provides, when the thickness on the described barrier layer of deposition was H, the thickness of using the described barrier layer that dry process removes was H
0+ H
1, H＞H
0+ H
1And adopt wet process to remove the T of being consuming time on remaining described barrier layer, T＜T
0
In other words, after increasing heat treatment operation, utilize dry process to remove the ratio on described barrier layer by increase, reducing utilizes wet process to remove the ratio on described barrier layer, can be in reducing device pin type leakage current, run through after the defective such as leakage current, further reduce the generation of etching bottom notch.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (9)
1. a method, semi-conductor device manufacturing method is characterized in that, comprising:
Substrate is provided, comprises substrate, be positioned at grid on the described substrate, be positioned at the source region and the drain region of the substrate of described grid both sides;
Form the barrier layer that covers described substrate;
Graphical described barrier layer, the expose portion substrate;
The substrate on the barrier layer of cover graphicsization is carried out in order to repair first heat treatment operation of described substrate;
Form metal level, described metal level covers the substrate that exposes behind the described graphical operation of experience;
Substrate with described metal level is carried out in order to form second heat treatment operation of metal silicide.
2. method, semi-conductor device manufacturing method according to claim 1, it is characterized in that: after forming the barrier layer that covers described substrate, before the graphical described barrier layer, also comprise, the step of injecting the 3rd heat treatment operation of ion in described source region and the drain region in order to activate is carried out in the substrate that covers described barrier layer.
3. method, semi-conductor device manufacturing method according to claim 1 is characterized in that, the step on graphical described barrier layer comprises:
Adopt dry process that main etching operation is carried out on described barrier layer, removal thickness is H
0Described barrier layer;
Adopt wet process that over-etching operation is carried out on described barrier layer, remove remaining described barrier layer.
4. method, semi-conductor device manufacturing method according to claim 3 is characterized in that: after carrying out described main etching operation, continuing to remove thickness is H
1Described barrier layer, H
0With H
1And less than the thickness H on described barrier layer.
5. method, semi-conductor device manufacturing method according to claim 1 is characterized in that: described barrier layer is a silicon dioxide.
6. method, semi-conductor device manufacturing method according to claim 1 is characterized in that: described metal level comprises a kind of or its combination in nickel, cobalt, the titanium.
7. method, semi-conductor device manufacturing method according to claim 1 and 2 is characterized in that: adopt rapid thermal anneal process when carrying out the described first and/or the 3rd heat treatment operation.
8. method, semi-conductor device manufacturing method according to claim 7 is characterized in that: carry out described first and/or the temperature range of the 3rd heat treatment operation be 950 degrees centigrade～1100 degrees centigrade.
9. method, semi-conductor device manufacturing method according to claim 7 is characterized in that: carry out described first and/or the time range of the 3rd heat treatment operation be 10 seconds～30 seconds.
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|---|---|---|---|
| CN2008101127790A CN101593696B (en) | 2008-05-26 | 2008-05-26 | Method for manufacturing semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101127790A CN101593696B (en) | 2008-05-26 | 2008-05-26 | Method for manufacturing semiconductor devices |
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|---|---|
| CN101593696A CN101593696A (en) | 2009-12-02 |
| CN101593696B true CN101593696B (en) | 2011-05-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0259616A1 (en) * | 1986-09-12 | 1988-03-16 | International Business Machines Corporation | Silicon semiconductor device structure and process for forming same |
| US5893751A (en) * | 1996-08-09 | 1999-04-13 | United Microelectronics Corporation | Self-aligned silicide manufacturing method |
| CN1902740A (en) * | 2003-12-30 | 2007-01-24 | 英特尔公司 | Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films |
-
2008
- 2008-05-26 CN CN2008101127790A patent/CN101593696B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0259616A1 (en) * | 1986-09-12 | 1988-03-16 | International Business Machines Corporation | Silicon semiconductor device structure and process for forming same |
| US5893751A (en) * | 1996-08-09 | 1999-04-13 | United Microelectronics Corporation | Self-aligned silicide manufacturing method |
| CN1902740A (en) * | 2003-12-30 | 2007-01-24 | 英特尔公司 | Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films |
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|---|---|
| CN101593696A (en) | 2009-12-02 |
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