CN101589467A - Semiconductor device comprising electromigration prevention film and manufacturing method thereof - Google Patents
Semiconductor device comprising electromigration prevention film and manufacturing method thereof Download PDFInfo
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- CN101589467A CN101589467A CN200880002910.6A CN200880002910A CN101589467A CN 101589467 A CN101589467 A CN 101589467A CN 200880002910 A CN200880002910 A CN 200880002910A CN 101589467 A CN101589467 A CN 101589467A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 230000002265 prevention Effects 0.000 title description 36
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 230000001681 protective effect Effects 0.000 claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims abstract description 11
- 238000007789 sealing Methods 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 73
- 239000002184 metal Substances 0.000 claims description 73
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 27
- 229920001721 polyimide Polymers 0.000 claims description 17
- 239000009719 polyimide resin Substances 0.000 claims description 17
- 229920005989 resin Polymers 0.000 claims description 17
- 239000011347 resin Substances 0.000 claims description 17
- 238000009713 electroplating Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 229910010272 inorganic material Inorganic materials 0.000 claims description 12
- 239000011147 inorganic material Substances 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000010953 base metal Substances 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 239000012528 membrane Substances 0.000 description 66
- 238000000034 method Methods 0.000 description 30
- 239000000377 silicon dioxide Substances 0.000 description 15
- 239000003822 epoxy resin Substances 0.000 description 14
- 229920000647 polyepoxide Polymers 0.000 description 14
- 239000000945 filler Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 239000011368 organic material Substances 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 6
- 230000000717 retained effect Effects 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000005011 phenolic resin Substances 0.000 description 3
- 229920001568 phenolic resin Polymers 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 description 1
- ZCQWOFVYLHDMMC-UHFFFAOYSA-N Oxazole Chemical compound C1=COC=N1 ZCQWOFVYLHDMMC-UHFFFAOYSA-N 0.000 description 1
- 241001364096 Pachycephalidae Species 0.000 description 1
- 229920000265 Polyparaphenylene Polymers 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- -1 polyparaphenylene Polymers 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一种半导体装置包括半导体衬底、设置在半导体衬底的一侧上并具有连接焊盘部分的多个布线、以及分别设置在布线的连接焊盘部分上的多个柱状电极，每个柱状电极都包括外周表面和顶表面。电迁移防护膜设置在至少布线的表面上。密封膜绕柱状电极的外周表面设置。
A semiconductor device includes a semiconductor substrate, a plurality of wirings provided on one side of the semiconductor substrate and having a connection pad portion, and a plurality of columnar electrodes respectively provided on the connection pad portions of the wirings, each columnar electrode Both include the peripheral surface and the top surface. The electromigration protective film is provided on at least the surface of the wiring. A sealing film is provided around the outer peripheral surface of the columnar electrode.
Description
Technical field
The present invention relates to comprise the semiconductor device and the manufacture method thereof of electromigration prevention film.
Background technology
In the open No.2004-207306 of Japanese patent application KOKAI, a kind of semiconductor device that is called as chip size packages (CSP) has been described.This semiconductor device comprises Semiconductor substrate, and described substrate has lip-deep a plurality of connection pads disposed thereon.On the upper surface that is arranged at the dielectric film on the Semiconductor substrate, a plurality of wirings are set, make them be electrically connected with corresponding connection pads.Columnar electrode is arranged on the connection pads respective upper surfaces partly of these wirings.Diaphragm seal is arranged on the upper surface of wiring and dielectric film, makes that the upper surface of sealing film is concordant with the upper surface of columnar electrode.Soldered ball is separately positioned on the upper surface of columnar electrode.
In above-mentioned conventional semiconductor device, directly the diaphragm seal of capping wiring is made by epoxy resin, thereby exists metal (copper) ion in the wiring to be diffused into problem in the diaphragm seal because of electromigration takes place, and this is a factor that causes short circuit between wiring.
In addition, the epoxy resin made by for example silica of filler wherein can be used as the material of diaphragm seal.In this semiconductor device, wiring may be subjected to the mechanical damage of filler.Rupture the problem that the miniaturization of existence wiring is restricted because of mechanical damage in order to prevent wiring.
Summary of the invention
Therefore the purpose of this invention is to provide a kind of semiconductor device and manufacture method thereof, be subjected to the mechanical damage of filler at an easy rate even also can prevent to connect up under its short circuit that causes because of electromigration between can preventing to connect up and the situation that is used as the diaphragm seal material at the resin that comprises filler.
The semiconductor device of the one side of claim 1 comprises according to the present invention:
Semiconductor substrate;
The a plurality of wirings that are arranged on a side of Semiconductor substrate and have the connection pads part;
Be separately positioned on a plurality of columnar electrodes on the connection pads part of wiring, each all comprises outer surface and top surface these columnar electrodes;
At least be arranged on the lip-deep electromigration prevention film of wiring; And
The diaphragm seal that is provided with around the outer surface of columnar electrode.
A kind of semiconductor device of the second aspect of claim 6 according to the present invention comprises:
Semiconductor substrate;
Be arranged on a plurality of wirings of the upside of Semiconductor substrate;
Be arranged on the surface of wiring and have the inorganic insulating membrane of opening in the corresponding part of connection pads part with wiring;
Be arranged on the upper surface of inorganic insulating membrane and on the upside of Semiconductor substrate and have an outer embrane of making by organic resin of opening in the corresponding part of connection pads part with wiring; And
Be arranged in the opening of inorganic insulating membrane and among the pallial opening and top and a plurality of columnar electrodes of partly being electrically connected with the connection pads of wiring.
Manufacture method of the present invention according to third aspect present invention comprises:
On the upside of Semiconductor substrate, form a plurality of wirings;
On the connection pads part of wiring, form a plurality of columnar electrodes;
Forming electromigration prevention film on the surface on the surface of wiring, at columnar electrode and on the upside in Semiconductor substrate;
On electromigration prevention film, form diaphragm seal; And
Upper surface one side of grinding-in film is to expose the upper surface of columnar electrode.
Manufacture method of the present invention according to fourth aspect present invention comprises:
On the upside of Semiconductor substrate, form a plurality of wirings;
On the connection pads part of wiring, form a plurality of columnar electrodes;
Forming electromigration prevention film on the surface on the surface of wiring, at columnar electrode and on the upside in Semiconductor substrate;
Removal is formed on the lip-deep electromigration prevention film on the top of columnar electrode;
On electromigration prevention film and columnar electrode, form diaphragm seal; And
Upper surface one side of grinding-in film is to expose the upper surface of columnar electrode.
Manufacturing method for semiconductor device according to fifth aspect present invention comprises:
On the upside of Semiconductor substrate, form a plurality of wirings;
Form inorganic insulating membrane on the surface of wiring, this inorganic insulating membrane has opening in the corresponding part of connection pads part with wiring;
Form the outer embrane of being made by organic resin at the upside of Semiconductor substrate and on inorganic insulating membrane, described outer embrane has opening in the corresponding part of connection pads part with wiring; And
By metallide in the opening of inorganic insulating membrane and among the pallial opening and above form columnar electrode.
According to the present invention, electromigration prevention film is arranged on the surface of wiring at least, and the short circuit between the wiring that therefore can prevent to be caused by electromigration.And electromigration prevention film plays the effect of diaphragm, is subjected to the mechanical damage of filler at an easy rate even also can prevent to connect up like this under the resin that comprises filler is used as the situation of diaphragm seal material.
Description of drawings
Fig. 1 is the cutaway view as the semiconductor device of first embodiment of the invention;
Fig. 2 is the cutaway view of the initial preparation assembly in an example of the method for making semiconductor device shown in Figure 1;
Fig. 3 is the cutaway view of the step after Fig. 2;
Fig. 4 is the cutaway view of the step after Fig. 3;
Fig. 5 is the cutaway view of the step after Fig. 4;
Fig. 6 is the cutaway view of the step after Fig. 5;
Fig. 7 is the cutaway view of the step after Fig. 6;
Fig. 8 is the cutaway view of the step after Fig. 7;
Fig. 9 is the cutaway view of the step after Fig. 8;
Figure 10 is the cutaway view of the step after Fig. 9;
Figure 11 is the cutaway view as the semiconductor device of second embodiment of the invention;
Figure 12 is the cutaway view of the predetermined process in an example of the method for making semiconductor device shown in Figure 11;
Figure 13 is the cutaway view of the step after Figure 12;
Figure 14 is the cutaway view as the semiconductor device of third embodiment of the invention;
Figure 15 is the cutaway view of the assembly of the initial preparation in an example of the method for making semiconductor device shown in Figure 14;
Figure 16 is the cutaway view of the step after Figure 15;
Figure 17 is the cutaway view of the step after Figure 16;
Figure 18 is the cutaway view of the step after Figure 17;
Figure 19 is the cutaway view of the step after Figure 18;
Figure 20 is the cutaway view of the step after Figure 19;
Figure 21 is the cutaway view of the step after Figure 20;
Figure 22 is the cutaway view of the step after Figure 21;
Figure 23 is the cutaway view of the step after Figure 22;
Figure 24 is the cutaway view of the step after Figure 23;
Figure 25 is the cutaway view of the step after Figure 24;
Figure 26 is the cutaway view as the semiconductor device of four embodiment of the invention;
Figure 27 is the cutaway view of the predetermined process in an example of the method for making semiconductor device shown in Figure 26;
Figure 28 is the cutaway view of the step after Figure 27;
Figure 29 is the cutaway view of the step after Figure 28;
Figure 30 is the cutaway view of the step after Figure 29;
Figure 31 is the cutaway view of the step after Figure 30;
Figure 32 is the cutaway view of the step after Figure 31;
Figure 33 is the cutaway view of the step after Figure 32; And
Figure 34 is the cutaway view as the semiconductor device of fifth embodiment of the invention.
Embodiment
(first execution mode)
Fig. 1 represents the cutaway view as the semiconductor device of first embodiment of the invention.This semiconductor device is called as CSP, and comprises silicon substrate (Semiconductor substrate) 1.The integrated circuit (not shown) be arranged on the upper surface of silicon substrate 1 or among, and be arranged on the peripheral part of the upper surface of silicon substrate 1 by a plurality of connection pads 2 of making of metal (for example aluminium based metal), make these connection pads be electrically connected with integrated circuit.
The dielectric film of being made by inorganic material (for example silica or silicon nitride) 3 is arranged on the upper surface of the connection pads 2 except that the center of connection pads 2 and on the upper surface of silicon substrate 1.Expose by the opening 4 that is arranged on the dielectric film 3 at the center of connection pads 2.(for example the electric insulation diaphragm 5 made of polyimide resin or polyparaphenylene Ben Bing Er oxazole (PBO) resin is arranged on the upper surface of dielectric film 3 by inorganic material.Opening 6 is arranged in opening 4 corresponding parts diaphragm 5 and dielectric film 3.Recess or groove 7 are arranged on the peripheral part of diaphragm 5.
A plurality of wirings 8 are arranged on the upper surface of diaphragm 5.Each wiring 8 all has double-decker, and it is made up of with the last metal level 10 that is become by the copper on the upper surface that is arranged on foundation metal layer 9 foundation metal layer 9 that is for example become by the copper on the upper surface that is arranged on diaphragm 5.One end of wiring 8 is electrically connected with connection pads 2 by the opening 4,6 of the aligning of dielectric film 3 and diaphragm 5.The columnar electrode 11 that is made of copper is arranged on wiring 8 the other end or on the upper surface of connection pads part.
Make and part is given prominence to electromigration prevention film 12 with the outer surface of capping columnar electrode 11 cylindrically and is arranged on the surface of wiring 8 and on the upper surface of diaphragm 5 by polyimide resin or PBO resin.Recess 13 with the recess 7 corresponding parts of diaphragm 5 in be arranged on the peripheral part of electromigration prevention film 12.Therefore, the outer surface of diaphragm 5 is preferably concordant with the outer surface of electromigration prevention film 12.
The recess 7 that passes through diaphragm 5 and electromigration prevention film 12 at dielectric film 3; the diaphragm seal of being made by epoxy resin 14 is set on 13 upper surfaces that expose and on the upper surface of electromigration prevention film 12; described epoxy resin comprises the filler of being made by for example silica, makes that the upper surface of described diaphragm seal 14 can be concordant with the upper surface of columnar electrode 11.Sealing film 14 is by the side surface of the cylindrical projections sealing columnar electrode 11 of electromigration prevention film 12.Soldered ball 15 is separately positioned on the upper surface of corresponding columnar electrode 11.
Below, will an example of the method for making described semiconductor device be described.At first; as shown in Figure 2; prepare such assembly; dielectric film 3 that wherein on the upside that is in the silicon substrate (hereinafter referred to as semiconductor wafer 21) under the wafer state, forms the connection pads 2 made by aluminium based metal, makes by for example silica or silicon nitride and the diaphragm of making by for example polyimide resin or PBO resin 5; and by passing the center that opening 4,6 that dielectric film 3 and diaphragm 5 form exposes connection pads 2.
In this case, the integrated circuit (not shown) with predetermined function is formed in the zone of formation semiconductor device of upper surface of semiconductor wafer 21, and every group of connection pads 2 be formed on appropriate section in integrated circuit in each be electrically connected.In Fig. 2, corresponding with line by the zone of Reference numeral 22 expressions.Recess that extends along the upper surface of wafer 21 or groove 7 be formed on diaphragm 5 with line 22 corresponding parts in and be formed on its both sides.
Then, as shown in Figure 3, foundation metal layer 9 is formed on the center upper surface that the opening 4,6 that passes through dielectric film 3 and diaphragm 5 of connection pads 2 exposes, on the dielectric film 3 and on the entire upper surface of diaphragm 5.The formation method and the conductive material of this foundation metal layer 9 are unrestricted, and can only be the copper layer that forms by electroless plating, can only be the copper layer that forms by sputter, perhaps can be by carry out the copper layer that sputter forms on thin layer (for example titanium layer that forms by sputter).
Then, electroplate etchant resist formation film and be formed on the upper surface of foundation metal layer 9, and this film is patterned to form plating etchant resist 23.Opening 24 is formed on electroplates going up in the regional corresponding part of metal level 10 with formation of etchant resist 23.Afterwards, utilize foundation metal layer 9 to implement to have the metallide of copper, on the upper surface that is in the part in the opening 24 of electroplating etchant resist 23 of foundation metal layer 9, form metal level 10 thus as the electroplating current path.Subsequently, remove plating etchant resist 23.
Then, as shown in Figure 4, electroplate etchant resist formation film and be formed on the upper surface of metal level 10 and foundation metal layer 9, and this film is patterned to form plating etchant resist 25.In this case, opening 26 be formed on electroplate etchant resist 25 with form the connection pads part just in the regional corresponding part of columnar electrode 11 that goes up metal level 10.Afterwards, utilize foundation metal layer 9 to implement to have the metallide of copper, make columnar electrode 11 be formed on being on the connection pads respective upper surfaces partly in the opening 26 of electroplating etchant resist 25 of metal level 10 as the electroplating current path.
Then, remove and electroplate etchant resist 25, and utilize subsequently and go up metal level 10 as mask etching and the foundation metal layer 9 of removing the zone that is not in metal level 10 belows.Thereby foundation metal layer 9 only is retained in the below of metal level 10 as shown in Figure 5.In this state, wiring 8 is made of foundation metal layer 9 and the last metal level 10 that is formed on the upper surface of foundation metal layer 9.
Then, on outer surface (upper surface and outer circumferential side surface) and on the upper surface of diaphragm 5, form the electromigration prevention film of making by for example polyimide resin or PBO resin 12 by proper method (for example whirl coating) on the surface of wiring 8, at columnar electrode 11.Afterwards, as shown in Figure 6, form recess 13 in recess 7 corresponding parts electromigration prevention film 12 and diaphragm 5 by photoetching process.
Then; as shown in Figure 7; for example pass through silk screen print method or whirl coating at recess 7 by diaphragm 5 and electromigration prevention film 12; form the diaphragm seal of making by for example epoxy resin 14 on the upper surface of the upper surface of 13 dielectric films that expose 3 and electromigration prevention film 12; described epoxy resin comprises the filler of being made by for example silica, makes that the thickness of sealing film 14 can be bigger than the height of columnar electrode 11 (thickness that comprises the part on the upper surface that is formed on columnar electrode 11 of electromigration prevention film 12).
Then, upper surface one side of diaphragm seal 14 is suitably ground and is removed, with the upper surface of the cylindrical part on the outer surface that is formed on columnar electrode 11 of the upper surface that exposes columnar electrode 11 as shown in Figure 8 and electromigration prevention film 12, and the upper surface of the diaphragm seal 14 that comprises these exposing surfaces is flattened.
Then, as shown in Figure 9, soldered ball 15 is formed on the upper surface of corresponding columnar electrode 11.Afterwards, as shown in figure 10,, obtain a plurality of semiconductor devices shown in Figure 1 thus along tangent line 22 cutting semiconductor chips 21, dielectric film 3 and diaphragm seal 14.
In thus obtained semiconductor device, the surface (upper surface and side surface) of wiring 8 and the outer surface of columnar electrode 11 are coated with the electromigration prevention film of being made by for example polyimide resin or PBO 12, as shown in Figure 1.Therefore, between wiring, any electromigration can be do not produced, the short circuit that produces because of 8 the electromigration of connecting up can be prevented thus.
In addition, in semiconductor device shown in Figure 1, wiring 8 surface coverage has the electromigration prevention film of being made by for example polyimide resin or PBO resin 12, is used as the mechanical damage that wiring 8 under the situation of material of diaphragm seal 14 also can not be easy to be subjected to filler even make at the epoxy resin that comprises the filler of being made by for example silica.
In semiconductor device shown in Figure 1, the whole outer surface of columnar electrode 11 is coated with electromigration prevention film 12, and soldered ball 15 only is arranged on the upper surface of columnar electrode 11, makes the upper surface of cylindrical part of outer surface of covering columnar electrode 11 of electromigration prevention film 12 expose in the upper surface of diaphragm seal 14.In this case, if electromigration prevention film 12 is made by polyimide resin or PBO resin, the moisture resistance reliability reduces because of these resins have moisture absorption.Therefore second execution mode of the present invention that can improve the moisture resistance reliability will be described below.
(second execution mode)
Figure 11 represents the cutaway view as the semiconductor device of second embodiment of the invention.The difference of this semiconductor device and semiconductor device shown in Figure 1 is that the following outer surface of columnar electrode 11 is coated with electromigration prevention film 12, and the last outer surface of columnar electrode 11 is coated with diaphragm seal 14, makes the upper surface of cylindrical part of electromigration prevention film 12 not expose in the upper surface of diaphragm seal 14.
Below, will an example of the method for making this semiconductor device be described.In this case; after step shown in Figure 6; by whirl coating for example on the upper surface that the recess that passes through diaphragm 5 and electromigration prevention film 12 or the groove 7,13 of dielectric film 3 exposes and on the upper surface of the part the top of the cylindrical part of the electromigration prevention film on the outer surface that is formed on columnar electrode 11 as shown in figure 12 12 on the electromigration prevention film 12, form etchant resist 41.In this case, the thickness of the part on the upper surface that is formed on electromigration prevention film 12 of etchant resist 41 be columnar electrode 11 height roughly half.
Then, obtain etching and removal on the last outer surface that is formed on columnar electrode 11 of electromigration prevention film 12 and than the outstanding higher cylindrical part of the upper surface of etchant resist 41, make the outstanding higher last outer surface of upper surface of ratio etchant resist 41 of columnar electrode 11 expose as shown in figure 13.Subsequently, the same with manufacture method in above-mentioned first execution mode, form step, soldered ball by diaphragm seal and form step and scribe step to obtain structure as shown in figure 11 be a plurality of semiconductor devices that the last outer surface of columnar electrode 11 is coated with diaphragm seal 14.
In thus obtained semiconductor device, the last outer surface of columnar electrode 11 and also have the upper surface of the cylindrical part of electromigration prevention film 12 to be coated with the diaphragm seal of being made by fluid-tight epoxy resin 14 as shown in figure 11 thus makes the moisture resistance reliability be improved.In this case, when diaphragm seal 14 is made by the epoxy resin that comprises the filler that silica for example makes, also can improve the moisture resistance reliability.
(the 3rd execution mode)
Figure 14 represents the cutaway view as the semiconductor device of the 3rd execution mode of the present invention.This semiconductor device is called as CSP, and comprises silicon substrate (Semiconductor substrate) 1.The integrated circuit (not shown) is arranged on the upper surface of silicon substrate 1, and is arranged on the peripheral part of the upper surface of silicon substrate 1 by a plurality of connection pads 2 of making of metal (for example aluminium based metal), makes these connection pads link to each other with integrated circuit.
By comprising on the upper surface that first inorganic insulating membrane of making as the inorganic material of the silica of main component or silicon nitride 16 is arranged on the connection pads 2 except the center of connection pads 2 and on the upper surface of silicon substrate 1.Expose by the opening 4 that is arranged on first inorganic insulating membrane 16 at the center of connection pads 2.The organic protective film of being made by organic material (for example polyimide resin or epoxy resin) (organic insulating film) 40 is arranged on the upper surface of first inorganic insulating membrane 16.Opening 6 is arranged in opening 4 corresponding parts organic protective film 40 and first inorganic insulating membrane 16.
The foundation metal layer 9 that is become by for example copper is arranged on the upper surface of organic protective film 40.The upper electrode layer 10 that is made of copper is arranged on the entire upper surface of foundation metal layer 9, and these layers constitute wiring 8.An end that comprises foundation metal layer 9 of wiring 8 is electrically connected with connection pads 2 by the opening 4,6 of first inorganic insulating membrane 16 and organic protective film 40.By comprising on the upper surface that second inorganic insulating membrane of making as the inorganic material of the silica of main component or silicon nitride 19 is arranged on wiring 8 and organic protective film 40.Opening 20 be formed on second inorganic insulating membrane 19 with wiring 8 the corresponding part of connection pads part in.
The outer embrane of being made by organic material (polyimide resin or epoxy resin) 29 is arranged on the upper surface of second inorganic insulating membrane 19.Opening 30 be formed on outer embrane 29 with wiring 8 the corresponding part of connection pads part in.The foundation metal layer of being made by metal (for example copper) 37 is arranged on the connection pads upper surface partly that the opening 20,12 that pass through second inorganic insulating membrane 19 and outer embrane 29 of wiring 8 exposes, on the inner wall surface of the opening 20 of second inorganic insulating membrane 19, on the inner wall surface of the opening 30 of outer embrane 29 and outer embrane 29 on the upper surface of the part of the opening 30 of outer embrane 29.The columnar electrode 11 that is made of copper is arranged on the entire upper surface of foundation metal layer 37.
Each columnar electrode 11 all divides 11a by the following column electrode part in the opening 20,12 that is arranged on second inorganic insulating membrane 19 and outer embrane 29 and is arranged on down the column electrode part and divides on the upper surface of 11a and the perimembranous and the last column electrode part on the outer embrane 29 is divided 11b.The following column electrode part of columnar electrode 11 divides 11a partly to be electrically connected by the corresponding connection pads of the part in the opening 20,12 that is arranged on second inorganic insulating membrane 19 and outer embrane 29 of foundation metal layer 37 with wiring 8.Soldered ball 15 is arranged on the outer circumferential side surface of the neighboring on the upper surface of being located at outer embrane 29 of foundation metal layer 37 and the last column electrode part of columnar electrode 11 is divided on the surface of 11b.
Below, will an example of the method for making this semiconductor device be described.At first, as shown in figure 15, prepare such assembly, wherein: the connection pads part of making by for example aluminium based metal 2, by comprising first inorganic insulating membrane 16 made as the inorganic material of the silica of main component or silicon nitride and being formed on the upper surface of the silicon substrate (hereinafter referred to as semiconductor wafer 21) that is in wafer state by the organic protective film 40 that organic material (for example polyimide resin or epoxy resin) is made; And expose by the opening 4,6 that is formed on first inorganic insulating membrane 16 and the organic protective film 40 at the center of connection pads 2.
In this case, the integrated circuit (not shown) with predetermined function is formed on the upper surface of semiconductor wafer 21 and forms in the zone of semiconductor device, and connection pads 2 is electrically connected with integrated circuit in being formed on appropriate section.In Figure 15, corresponding with line by the zone of Reference numeral 22 expressions.
Then; as shown in figure 16; the layer (hereinafter simply being called foundation metal layer 9 in order to simplify) that is used to form foundation metal layer 9 is formed on the entire upper surface of passing through the part that the opening 4,6 on first inorganic insulating membrane 16 and the organic protective film 40 exposes of connection pads 2 and on the entire upper surface of organic protective film 40.In this case, foundation metal layer 9 can only be the copper layer that forms by electroless plating, can only be the copper layer that forms by sputter, perhaps can be by carry out the copper layer that sputter forms on thin layer (for example titanium layer that forms by sputter).
Then, electroplate etchant resist 23 patterned/be formed on the upper surface of foundation metal layer 9.In this case, opening 24 be formed on electroplate etchant resist 23 with the regional corresponding part that forms wiring 8 (upper electrode layers 10) in.Afterwards, utilize foundation metal layer 9 to implement to have the metallide of copper as the electroplating current path, be formed for forming the layer (hereinafter simply being called metal level in order to simplify) of the last metal level of wiring 8 thus, it is formed on the upper surface in the opening 24 that foundation metal layer 9 is in plating etchant resist 23.Subsequently, separate to electroplate etchant resist 23, afterwards the foundation metal layer in the zone that is not in the metal level below 9 is utilized and gone up metal level and carry out etching and removal as mask, foundation metal layer 9 only is retained in below the metal level, as shown in figure 17 thus.
Then, as shown in figure 18, by comprising that second inorganic insulating membrane of making as the inorganic material of the silica of main component or silicon nitride 19 is formed on the upper surface of wiring 8 and organic protective film 40 by plasma CVD method.In this case, the technological temperature that forms second inorganic insulating membrane 19 is preferably 250 ℃ or lower, makes the organic protective film of being made by organic material (for example polyimide resin) 40 that has formed not be subjected to fire damage.
For example, if adopt Si (OH
2H
5)
4(TEOS), can be the SiO of 500nm-1000nm then in 10-20 minute, forming thickness under about 120 ℃ technological temperature as process gas
2Film.If adopt SiH (OCH
3)
3(TMS), can be the SiO of 500nm-1000nm then in 10-20 minute, forming thickness under about 80 ℃ technological temperature as process gas
2Film.
Then, as shown in figure 19, on the upper surface of second inorganic insulating membrane 19, form the outer embrane of making by organic material (for example polyimide resin or epoxy resin) 29 by for example whirl coating.Afterwards, utilize the photomask (not shown) by photoetching process outer embrane 29 with wiring 8 the corresponding appropriate section of connection pads part in form opening 30.
Then, as shown in figure 20, the positive etchant resist made by for example phenolic resins is 39 patterned/be formed on the upper surface of outer embrane 29.In this case, opening 26 is formed in opening 30 corresponding parts etchant resist 39 and outer embrane 29 (just connect up 8 connection pads part).
Then, second inorganic insulating membrane 19 utilizes etchant resist 39 to bear dry etching to form opening 20 in opening 30 corresponding parts second inorganic insulating membrane 19 and outer embrane 29 (just connect up 8 connection pads part), as shown in figure 21 as mask.In this case, dry etching can be for example general reactive ion etching (RIE) or can be high-density plasma dry etching described below.
Then, separate etchant resist 39.In addition, can utilize outer embrane 29 to need not to adopt etchant resist 39 to implement dry etching as mask.Equally in this case, dry etching can be for example general reactive ion etching (RIE), perhaps can be high-density plasma dry etching described below.
Then, as shown in figure 22, by the sputter formation foundation metal layer 37 on the upper surface of the connection pads part that the opening 20,12 that pass through second inorganic insulating membrane 19 and outer embrane 29 of wiring 8 exposes and on the entire upper surface of outer embrane 29 of copper for example.Afterwards, electroplate etchant resist 27 patterned/be formed on the upper surface of foundation metal layer 37.In this case, be formed on than the opening 30 bigger openings 28 of outer embrane 29 and electroplate dividing in the regional corresponding part of 11b of etchant resist 27 with its last column electrode part that goes up formation columnar electrode 11.
Then, utilize foundation metal layer 37 to implement to have the metallide of copper with opening 20 at second inorganic insulating membrane 19 and outer embrane 29 as the electroplating current path, form down the column electrode part on 12 the foundation metal layer 37 and divide 11a, and in the opening 28 of electroplating etchant resist 27, divide on the 11a and divide 11b forming the column electrode part on the upper surface of foundation metal layer 37 subsequently in column electrode part down.
In this case, owing to electroplate the opening 30 that the opening 28 of etchant resist 27 is slightly larger than outer embrane 29, so plated metal isotropically is deposited in the opening 28 of electroplating etchant resist 27.Like this, the last column electrode part that is formed in the opening 28 of electroplating etchant resist 27 divides 11b to have the protrusion shape.Thereby, form the columnar electrode 11 that divides 11a and last column electrode part to divide 11b to form by following column electrode part.
Then, separate and electroplate etchant resist 27, utilize columnar electrode 11 as the part that is not in the zone of columnar electrode 11 belows on mask etching and the removal foundation metal layer 37 subsequently, foundation metal layer 37 only is retained in columnar electrode 11 belows thus, as shown in figure 23.Subsequently, by silk screen print method the last column electrode part that the solder flux (not shown) is applied to columnar electrode 11 is divided on the upper surface of 11b, and the soldered ball (not shown) is installed on the upper surface of solder flux subsequently.
Then, after reflux course, be installed in the soldered ball fusing on the upper surface of solder flux, obtain corners and curing by surface tension subsequently, the last column electrode part that makes soldered ball 15 be formed on columnar electrode 11 is divided on the surface of the foundation metal layer 37 on the upper surface that is formed at outer embrane 29 comprising of 11b, as shown in figure 24.Afterwards, as shown in figure 25,, obtain a plurality of semiconductor devices as shown in figure 14 thus along line 22 cutting semiconductor chips 21, first inorganic insulating membrane 16, organic protective film 40, second inorganic insulating membrane 19 and outer embrane 29.
At this; in above-mentioned manufacturing method for semiconductor device; second inorganic insulating membrane 19 that has opening 20 in the corresponding part of connection pads part with wiring 8 is formed on the organic protective film 40 that comprises wiring 8; and the outer embrane 29 that has opening 30 in the corresponding part of connection pads part with wiring 8 is formed on second inorganic insulating membrane 19; afterwards by the opening 20 of metallide at second inorganic insulating membrane 19 and outer embrane 29; the connection pads of the wiring 8 in 12 partly goes up and forms columnar electrode 11; as shown in figure 22, make and no longer to need specific process of lapping.
In addition, in the semiconductor device that obtains by above-mentioned manufacture method, the surface except connection pads part of wiring 8 is coated with second inorganic insulating membrane of making as the inorganic material of the silica of main component or silicon nitride by comprising 19 as shown in figure 14, make can suppress to connect up between 8 and connect up 8 and columnar electrode 11 between electromigratory generation.
(the 4th execution mode)
Figure 26 is the cutaway view as the semiconductor device of four embodiment of the invention.The difference of this semiconductor device and semiconductor device shown in Figure 14 is that second inorganic insulating membrane 19 with opening 20 only is arranged on the surface that comprises foundation metal layer 9 of wiring 8, and the 3rd inorganic insulating membrane 38 is arranged on the inner wall surface of opening 20 of second inorganic insulating membrane 19, on the inner wall surface of the opening 30 of outer embrane 29 and the getting around on mouthfuls 30 the upper surface of outer embrane 29.
Below, will an example of the method for making this semiconductor device be described.In this case, after step shown in Figure 180, by for example phenolic resins make positive etchant resist 31 patterned/be formed on the upper surface of second inorganic insulating membrane 19, as shown in figure 27.In this case, first opening 32 be formed on etchant resist 31 with wiring 8 the corresponding part of connection pads part in.And second opening 33 is formed on and covers on the corresponding etchant resist 31 of part between second inorganic insulating membrane 19 of wiring 8 end face.
Then, second inorganic insulating membrane 19 utilizes etchant resist 31 to bear dry ecthing to form opening 20 and remove second opening, 33 corresponding parts second inorganic insulating membrane 19 and etchant resist 31 in first opening, 32 corresponding parts second inorganic insulating membrane 19 and etchant resist 31 (just connect up 8 connection pads part), as shown in figure 28 as mask.
In this case, dry ecthing can be for example general reactive ion etching (RIE) or can be high-density plasma dry ecthing described below.And in this state, second inorganic insulating membrane 19 with opening 20 only is formed on the surface that comprises foundation metal layer 9 of wiring 8.Afterwards, separate etchant resist 31.
Then, as shown in figure 29, the outer embrane made by organic material (for example polyimide resin or epoxy resin) is 29 patterned/be formed on the upper surface that comprises second inorganic insulating membrane 19 of organic protective film 40.In this case, utilize the photomask (not shown) to form opening 30 in the corresponding appropriate section of the connection pads part with wiring 8 of outer embrane 29 by photoetching process.
Then, as shown in figure 30, by plasma CVD method on the upper surface of the connection pads part that wiring 8 the opening 20,12 that pass through second inorganic insulating membrane 19 and outer embrane 29 exposes and on the entire upper surface of outer embrane 29 formation by comprising the 3rd inorganic insulating membrane of making as the inorganic material of the silica of main component or silicon nitride 38.Equally in this case, the technological temperature that forms the 3rd inorganic insulating membrane 38 is preferably 250 ℃ or lower, makes organic protective film 40 and the outer embrane 29 made by organic material (for example polyimide resin) that have formed can not be subjected to fire damage.
Then, the positive etchant resist made by for example phenolic resins is 34 patterned/is formed on the upper surface of the 3rd inorganic insulating membrane 38.In this case, positive etchant resist 34 only be formed on the upper surface on the inner wall surface of the opening that is formed at outer embrane 29 30 of the 3rd inorganic insulating membrane 38 and the upper surface that gets around mouthful of the 3rd inorganic insulating membrane 38 on.
Then, the 3rd inorganic insulating membrane 38 utilizes positive etchant resist 34 to bear dry ecthing as mask, makes the 3rd inorganic insulating membrane 38 only be retained in positive etchant resist 34 belows, as shown in figure 31.Just, the 3rd inorganic insulating membrane 38 be formed on the inner wall surface of opening 20 of second inorganic insulating membrane 19, on the inner wall surface of pallial opening 30 and the getting around on mouthfuls 30 the upper surface of outer embrane 29.In this state, the connection pads of wiring 8 part is exposed by the opening 17 that is formed on the 3rd inorganic insulating membrane 38.Afterwards, separate etchant resist 34.
At this, dry etching in this case preferably should be the high-density plasma dry etching, it makes and changes into isoionic gas and have longer mean free path, so that the etching of the 3rd inorganic insulating membrane 38 on the inner wall surface of the opening 20,12 that especially is formed on second inorganic insulating membrane 19 and outer embrane 29 is reduced to minimum.
For example, helicon (whistler wave) Etaching device can produce high-density plasma under high vacuum, and is preferred.In this case, if adopt CF
4As process gas, to the OH that wherein adds total amount 5%-10%
2, then can improve etching efficiency.And, can adopt the inductively coupled plasma Etaching device that can produce high-density plasma.
Then, shown in figure 32, by copper for example on the upper surface of the connection pads part that the opening that passes through the 3rd inorganic insulating membrane 38 17 of wiring 8 exposes, on the 3rd inorganic insulating membrane 38 and the sputter on the entire upper surface of outer embrane 29 form foundation metal layer 37.Afterwards, electroplate etchant resist 35 patterned/be formed on the upper surface of foundation metal layer 37.In this case, be formed on than the opening 17 bigger openings 36 of the 3rd inorganic insulating membrane 38 and electroplate dividing in the regional corresponding part of 11b of etchant resist 35 with its last column electrode part that goes up formation columnar electrode 11.
Then, utilize foundation metal layer 37 implements to have copper as the electroplating current path metallide to divide 11a and electroplating subsequently that following column electrode part in the opening 36 of etchant resist 35 is divided on the 11a and dividing 11b forming the column electrode part on the upper surface of foundation metal layer 37 with column electrode part under forming on the foundation metal layer 37 of the opening 17 of the 3rd inorganic insulating membrane 38.
Equally in this case, owing to electroplate the opening 17 that the opening 36 of etchant resist 35 is slightly larger than the 3rd inorganic insulating membrane 38, so plated metal isotropically is deposited in the opening 36 of electroplating etchant resist 35.Like this, the last column electrolysis section 11b that is formed in the opening 36 of electroplating etchant resist 35 has the protrusion shape.Thereby, form the columnar electrode 11 that divides 11a and last column electrode part to divide 11b to form by following column electrode part.
Then, separate and electroplate etchant resist 35, and utilize columnar electrode 11 foundation metal layer in the zone that is not in columnar electrode 11 belows 37 to be carried out etching and removal subsequently as mask, foundation metal layer 37 only is retained in the below of columnar electrode 11 thus, as shown in figure 33.Subsequently, the same with in the above-described 3rd embodiment manufacture method, by solder flux apply step, soldered ball forms step and scribe step obtains a plurality of semiconductor devices shown in Figure 26.
In the semiconductor device of thus obtained the 4th execution mode, the surface coverage except connection pads part of wiring 8 has second inorganic insulating membrane of making as the inorganic material of the silica of main component or silicon nitride by comprising 19, and the following column electrode part of columnar electrode 11 divides the outer surface of 11a to be coated with the 3rd inorganic insulating membrane of making as the inorganic material of the silica of main component or silicon nitride by comprising 38.Thereby, can be suppressed at the wiring 8 between, between the columnar electrode 11 and connect up 8 and columnar electrode 11 between produce electromigration.
(the 5th execution mode)
Figure 34 is the cutaway view as the semiconductor device of fifth embodiment of the invention.The difference of this semiconductor device and semiconductor device shown in Figure 26 is that second inorganic insulating membrane 19 with opening 20 not only is arranged in the wiring 8, and it is arranged on the entire upper surface of organic protective film 40.In an example of the method for making this semiconductor device, can after step shown in Figure 21, implement the step shown in Figure 30 that is not shown specifically.
Claims (25)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007014533A JP4765947B2 (en) | 2007-01-25 | 2007-01-25 | Semiconductor device and manufacturing method thereof |
| JP014533/2007 | 2007-01-25 | ||
| JP2007086418A JP2008244383A (en) | 2007-03-29 | 2007-03-29 | Semiconductor device and manufacturing method thereof |
| JP086418/2007 | 2007-03-29 | ||
| PCT/JP2008/051594 WO2008091023A1 (en) | 2007-01-25 | 2008-01-24 | Semiconductor device comprising electromigration prevention film and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101589467A true CN101589467A (en) | 2009-11-25 |
| CN101589467B CN101589467B (en) | 2012-05-30 |
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|---|---|---|---|
| CN200880002910.6A Expired - Fee Related CN101589467B (en) | 2007-01-25 | 2008-01-24 | Semiconductor device comprising electromigration prevention film and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP4765947B2 (en) |
| CN (1) | CN101589467B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201389A (en) * | 2010-03-23 | 2011-09-28 | 卡西欧计算机株式会社 | Semiconductor device provided with tin diffusion inhibiting layer and manufacturing method of the same |
| CN102867758A (en) * | 2011-07-08 | 2013-01-09 | 颀邦科技股份有限公司 | Bump Manufacturing Process and Its Structure |
| CN108695314A (en) * | 2017-04-05 | 2018-10-23 | 三星电子株式会社 | The conductive layer of integrated circuit and its manufacturing method and integrated circuit |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5277788B2 (en) * | 2008-08-14 | 2013-08-28 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| JP5296590B2 (en) | 2009-03-30 | 2013-09-25 | 新光電気工業株式会社 | Manufacturing method of semiconductor package |
| US9024431B2 (en) | 2009-10-29 | 2015-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die contact structure and method |
| US9190348B2 (en) | 2012-05-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scheme for connector site spacing and resulting structures |
| JP5633095B2 (en) * | 2013-02-08 | 2014-12-03 | 新光電気工業株式会社 | Semiconductor package manufacturing method and semiconductor package |
| JP6365106B2 (en) * | 2014-08-18 | 2018-08-01 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
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| US5391397A (en) * | 1994-04-05 | 1995-02-21 | Motorola, Inc. | Method of adhesion to a polyimide surface by formation of covalent bonds |
| JP3905032B2 (en) * | 2002-12-20 | 2007-04-18 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| JP4307296B2 (en) * | 2004-03-12 | 2009-08-05 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP2006147810A (en) * | 2004-11-19 | 2006-06-08 | Casio Comput Co Ltd | Semiconductor device and manufacturing method thereof |
-
2007
- 2007-01-25 JP JP2007014533A patent/JP4765947B2/en not_active Expired - Fee Related
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201389A (en) * | 2010-03-23 | 2011-09-28 | 卡西欧计算机株式会社 | Semiconductor device provided with tin diffusion inhibiting layer and manufacturing method of the same |
| CN102867758A (en) * | 2011-07-08 | 2013-01-09 | 颀邦科技股份有限公司 | Bump Manufacturing Process and Its Structure |
| CN102867758B (en) * | 2011-07-08 | 2015-12-02 | 颀邦科技股份有限公司 | Bump Manufacturing Process and Its Structure |
| CN108695314A (en) * | 2017-04-05 | 2018-10-23 | 三星电子株式会社 | The conductive layer of integrated circuit and its manufacturing method and integrated circuit |
| CN108695314B (en) * | 2017-04-05 | 2023-12-12 | 三星电子株式会社 | Integrated circuit, method for manufacturing the same and conductive layer of the integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101589467B (en) | 2012-05-30 |
| JP4765947B2 (en) | 2011-09-07 |
| JP2008182059A (en) | 2008-08-07 |
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