CN101582454B - Double-bit U-shaped memory structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a double-bit U-shaped memory structure and a manufacturing method thereof. The memory disclosed by the invention is structurally characterized in that the bottom of the floating gate is U-shaped and is embedded in the substrate. The memory structure of the invention comprises a substrate; the control grid is arranged on the surface of the substrate; the floating grid is arranged on two sides of the control grid, wherein the floating grid is provided with a U-shaped bottom which is embedded in the substrate; a first dielectric layer between the control gate and the substrate; a second dielectric layer between the U-shaped bottom of the floating gate and the substrate; a third dielectric layer between the control gate and the floating gate; the local doping area is arranged in the U-shaped floating gate channel right below the floating gate; and a source/drain doped region disposed in the substrate at one side of the floating gate.

Description

Double-bit U-shaped memory structure and manufacturing method thereof

technical field

The invention relates to a memory structure and a manufacturing method thereof, in particular to a double-bit memory element structure with a U-shaped bottom floating gate and a manufacturing method thereof.

Background technique

Flash memory has the characteristics of non-volatility, reerasable read-write, and fast transmission, so it has a wide range of applications, making many portable products use flash memory recently. It is used in many information, communication and consumer electronics. It has been considered as a necessary component in the product. In order to provide lightweight and high-quality electronic component products, improving the component integration and quality of flash memory has become the focus of the development of the information industry.

Please refer to FIG. 1 , which is a schematic structural diagram of a known dual-bit flash memory cell. As shown in FIG. 1 , a known flash memory cell includes a substrate 10, a control gate 12 disposed on the substrate 10, two floating gates 14a, 14b respectively disposed on both sides of the control gate 12, and a dielectric layer 16 disposed on the substrate 10. Between the control gate 12 and the substrate 10 and between the floating gates 14a, 14b and the substrate 10, the dielectric layer 18 is arranged between the control gate 12 and the floating gates 14a, 14b, and the source/drain doped regions 20 is located in the substrate on one side of the floating gates 14a, 14b, the pocket doped region 22 adjoins the source/drain doped region 20, and the floating gate channel 24.

The structure of the above-mentioned known flash memory has floating gates 14a, 14b formed on both side walls of the control gate 12, and can store double-bit data. As the size of the device design keeps shrinking, the floating gate channel keeps shortening. However, the length of the floating gate channel has a great influence on the performance of the flash memory. In general, the longer the floating gate channel, the better the performance of the flash memory. Although reducing the device size can increase the integration level, it will shorten the floating gate channel of the flash memory, resulting in a decrease in device performance. In addition, it will also reduce the process margin.

Furthermore, in the known flash memory, the pocket-type doped region is formed after the dopant is laterally diffused by a heating process after implantation. Since the pocket-type doped region is adjacent to the source/drain doped region, the pocket-type doped region Doped regions are susceptible to source/drain doped regions, causing process control issues. Therefore, developing a new memory structure and process, improving the performance of the flash memory and improving the process control are the current efforts of the semiconductor industry.

Contents of the invention

In view of this, the present invention provides a memory structure and its manufacturing method. By using the bottom of the U-shaped floating gate arranged in the substrate, the length of the floating gate channel can be increased while the element is shrunk, and the performance of the flash memory can be improved. , and disposing a local doped region directly under the floating gate instead of the pocket-type doped region in the known technology can effectively avoid the above-mentioned problem of process control. In addition, the memory structure of the present invention can improve the gate-induced drain leakage (GIDL) phenomenon and increase the writing speed of the flash memory.

According to a preferred embodiment of the present invention, a structure of a memory element in the present invention includes: a substrate, a control gate disposed on the surface of the substrate, and a floating gate disposed on both sides of the control gate, wherein the floating gate has U shaped bottom embedded in the substrate, a first dielectric layer between the control gate and the substrate, a second dielectric layer between the U-shaped bottom of the floating gate and the substrate, a second dielectric layer between the U-shaped bottom of the floating gate and the substrate, Three dielectric layers between the control gate and the floating gate, a local doped region, a U-shaped floating gate channel directly below the floating gate, and a source/drain doped region , set in the substrate on one side of the floating gate.

According to a preferred embodiment of the present invention, one aspect of the present invention provides a method for manufacturing a flash memory device, comprising: providing a substrate, including a first trench and a second trench disposed in the substrate, and then, on the substrate The first trench and the bottom of the second trench form a local doping region, and then, after forming a first dielectric layer to cover the surface of the first trench, the surface of the second trench and the surface of the substrate, a second trench is formed. A conductive layer fills and covers the first groove and the second groove, then, forms a second dielectric layer on both sides of the first conductive layer, and then forms an opening in the first groove and the second groove. In the first conductive layer between the two trenches, finally, a doped region is formed in the substrate between the first trench and the second trench.

Description of drawings

FIG. 1 is a schematic structural diagram of a known dual-bit flash memory cell.

2 to 7 are schematic diagrams illustrating a manufacturing method of a memory device according to a preferred embodiment of the present invention.

Explanation of reference signs

10 base 12 control grid

14 floating gate 16, 18 dielectric layer

20 source/drain doped region 22 pocket doped region

24 Floating Gate Trench 50 Substrate

52 dielectric layer 54 hard mask layer

56 trenches 58 local doping regions

60 area 62 dielectric layer

64 conductive layers 66 grooves

68 dielectric layer 70 conductive layer

72 openings 74 floating gates

76 source/drain doped regions 80 floating gate channel

57U bottom

Detailed ways

2 to 7 are schematic diagrams illustrating a manufacturing method of a memory device according to a preferred embodiment of the present invention. As shown in FIG. 2 , firstly, a substrate 50 is provided, which is overlaid with a dielectric layer 52 and a patterned hard mask layer 54 , wherein the dielectric layer 52 includes silicon oxide, and the hard mask layer 54 includes silicon nitride.

As shown in FIG. 3, using the hard mask layer 54 as a mask, a trench 56 is formed in the substrate 50, wherein the trench 56 has a U-shaped bottom 57, and then in the substrate 50 around the U-shaped bottom 57 of the trench 56. The local doping region 58 is formed, and then the hard mask 54 and the dielectric layer 52 in the region 60 are removed by using a mask (not shown), so that the substrate 50 in the region 60 is exposed.

As shown in FIG. 4 , a dielectric layer 62 is formed on the surface of the trench 56 and the surface of the substrate 50 in the region 60 as a tunneling dielectric layer. According to a preferred embodiment of the present invention, the dielectric layer 62 can be formed by high temperature oxidation. Then, a conductive layer 64 is formed, and the conductive layer 64 fills the trench 56 . Next, a polishing process is used to align the surface of the conductive layer 64 with the surface of the hard mask 54 .

As shown in FIG. 5 , the remaining hard mask 54 is removed, forming recesses 66 . Then, a dielectric layer 68 is formed, so that the dielectric layer 68 conformably covers the surface of the conductive layer 64 and the groove 66 . According to a preferred embodiment of the present invention, the dielectric layer 68 may be an oxide layer-silicon nitride layer-oxide layer (ONO) dielectric layer structure, and its formation method is, for example, first utilizing high temperature oxidation (high temperature oxidation, HTO) to make an oxide layer. layer, and then use low-pressure chemical vapor deposition (LPCVD) to make a nitrogen-silicon layer.

As shown in FIG. 6 , part of the dielectric layer 68 is removed, leaving only the dielectric layer 68 on both sides of the groove 66 . According to another preferred embodiment of the present invention, the dielectric layer 68 at the bottom of the groove 66 may also remain, and only the dielectric layer 68 above the conductive layer is removed.

As shown in FIG. 7, a conductive layer 70 is filled in the groove 66 as a control gate, and then, using the aforementioned mask (not shown) for removing the hard mask 54 located in the region 60, in the conductive layer 70 An opening 72 is formed to expose a portion of the dielectric layer 62 to form a floating gate 74 . Next, source/drain doped regions 76 are formed in the substrate 50 below the opening 72 by ion implantation. In operation, floating gate channel 80 is formed around the bottom of the U-shape of floating gate 74 . So far, the memory device of the present invention is completed, and then a dielectric layer can be formed on both sides of the opening 72 in subsequent processes, and the dielectric layer 62 at the bottom of the opening 72 can be removed, and then contact plugs can be formed in the opening 72 .

What Fig. 7 depicts is the structure of the memory element according to the preferred embodiment of the present invention. The memory element of the present invention includes a substrate 50, a control gate 70 disposed on the surface of the substrate 50, and a floating gate 74 disposed on the control gate 70. The floating gate 74 has a U-shaped bottom 57 embedded in the substrate 50, the dielectric layer 52 is used as a control gate dielectric layer, between the control gate 70 and the substrate 50, and the dielectric layer 62 is used as a through-hole The tunnel dielectric layer is interposed between the U-shaped bottom 57 of the floating gate 74 and the substrate 50, the dielectric layer 68 is interposed between the control gate 70 and the floating gate 74, and the local doped region 58 is disposed on the floating gate. The U-shaped floating gate channel 80 directly below the gate 74 and the source/drain doped region 76 are disposed in the substrate 50 on one side of the floating gate 74 . The aforementioned dielectric layer 52 may be composed of silicon oxide and silicon oxide-silicon nitride-silicon oxide structure (ONO), for example, silicon oxide is used as the lower layer, while the silicon oxide-silicon nitride-silicon oxide structure is covered on the on; or may only be composed of silicon oxide.

According to a preferred embodiment of the present invention, if the dopant in the source/drain doped region 76 is P-type, such as boron, then the dopant in the local doped region 58 is N-type, such as arsenic, wherein the local The doped region 58 is formed by ion implantation, the ion dose used is about 5E13, and the ion energy is about 50KeV.

The function of the local doped region 58 of the present invention is mainly to replace the pocket-type doped region in the known technology, to avoid abnormal penetration between the source and drain of the switch memory and to increase the threshold voltage difference of the switching state of the element. The advantage of the local doped region 58 is that the process is not easily affected by the source/drain doped region, and better process control can be provided.

In addition, the floating gate 74 of the present invention has a U-shaped bottom 57 embedded in the substrate. Compared with the traditional memory (see FIG. 1 ), its floating gate channel will be shortened as the integration of components increases. The floating gate of the present invention The gate 74 can provide a longer floating gate channel 80 while increasing the pole concentration, and can increase the gate-induced drain leakage (GIDL) to improve the writing efficiency. In this way, the memory can It has better performance and can also improve the process margin.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (11)

1. A memory element structure comprising: base; a control grid disposed on the surface of the substrate; a floating gate, disposed on both sides of the control gate, wherein the floating gate has a U-shaped bottom embedded in the substrate; a first dielectric layer between the control gate and the substrate; a second dielectric layer between the U-shaped bottom of the floating gate and the substrate; a third dielectric layer between the control gate and the floating gate; a locally doped region disposed around the U-shaped floating gate channel directly below the floating gate; and The source/drain doped region is arranged in the substrate on one side of the floating gate. 2. The memory structure of claim 1, wherein the first dielectric layer is silicon oxide. 3. The memory structure of claim 1, wherein the first dielectric layer is composed of silicon oxide and silicon oxide-silicon nitride-silicon oxide. 4. The memory structure of claim 1, wherein the third dielectric layer comprises silicon oxide-silicon nitride-silicon oxide. 5. The memory structure as claimed in claim 1, wherein when the source/drain doped region is P-type, the local doped region is N-type. 6. The memory structure of claim 1, wherein the second dielectric layer between the floating gate and the substrate is U-shaped. 7. The memory structure of claim 1, wherein the bottom of the locally doped region is U-shaped. 8. A method of manufacturing a memory element, comprising: providing a substrate, including a first groove and a second groove disposed in the substrate, wherein the bottom of the first groove is U-shaped and the bottom of the second groove is U-shaped; forming local doped regions at the bottom of the first trench and the second trench; forming a first dielectric layer covering the surface of the first trench, the surface of the second trench and the surface of the substrate; forming a first conductive layer to fill and cover the first trench and the second trench; forming a second dielectric layer on both sides of the first conductive layer; forming an opening in the first conductive layer between the first trench and the second trench; and A doped region is formed in the substrate between the first trench and the second trench. 9. The manufacturing method of the memory device according to claim 8, after forming the opening, forming a contact plug in the opening. 10. The manufacturing method of the memory device as claimed in claim 8, wherein the second dielectric layer comprises silicon oxide-silicon nitride-silicon oxide. 11. The manufacturing method of the memory device according to claim 8, wherein the second dielectric layer defines recessed regions on both sides of the conductive layer, and the manufacturing method is performed after forming the second dielectric layer and before forming the opening , which additionally includes the following steps: filling the recessed area with a second conductive layer; and Parts of the second conductive layer and the second dielectric layer are ground to expose the first conductive layer.

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