CN101577254B

CN101577254B - Method for manufacturing thin film transistor array substrate

Info

Publication number: CN101577254B
Application number: CN200910048543XA
Authority: CN
Inventors: 谭莉; 吴宾宾
Original assignee: SVA Group Co Ltd
Current assignee: Nanjing CEC Panda LCD Technology Co Ltd
Priority date: 2009-03-30
Filing date: 2009-03-30
Publication date: 2011-03-23
Anticipated expiration: 2029-03-30
Also published as: CN101577254A

Abstract

The invention relates to a method for manufacturing a thin film transistor array substrate, which comprises the following steps: forming a transparent conducting layer directly on a second metal layer; depositing passivation layers before stripping photoresist; and stripping the photoresist together with the passivation layers on a pixel electrode, a source top electrode, a drain top electrode, a data wire top electrode and a data bonding pad top electrode through a stripping process. Thus, the method reduces a light shielding process, and can simplify the manufacturing process, reduce the cost and improve the yield.

Description

Method for manufacturing thin film transistor array substrate

Technical field

The present invention relates to a kind of manufacture method of semiconductor element, relate in particular to method for manufacturing thin film transistor array substrate.

Background technology

Present LCD is a main flow with Thin Film Transistor-LCD (TFT LCD) mainly, the general structure of TFT LCD (Thin Film Transistor Liquid Crystal Display) is to have thin-film transistor array base-plate respect to one another and color membrane substrates, wadding is set keeping the box gap between two substrates, and between this box gap filling liquid crystal.

The tft array substrate of volume production needs four-wheel light shield operation mostly at least at present.Fig. 1 is the plane graph of the prior art tft array substrate of employing four road light shield operations manufacturings, and Fig. 2 is the sectional view along the A-A ' of Fig. 1 and B-B ' line drawing.Shown in seeing figures.1.and.2, the array base palte of prior art is formed with grid line intersected with each other 11 and data wire 52 on substrate 1, and grid line 11 forms TFT 91 with the zone of intersection of data wire 52.TFT 91 comprises grid 10, source electrode 51 and drains 50.Described grid 10 is formed on the first metal layer that directly contacts with substrate 1, is coated with gate insulation layer 20, semiconductor layer 30, ohmic contact 40, source electrode 51, drain electrode 50 and passivation layer 60 on grid 10 successively.Grid 10 is connected to grid line 11, and source electrode 51 is connected to data wire 52.Form pixel electrode 78 in the pixel region that is limited by grid 10 and data wire 52 intersections, described pixel electrode 78 links to each other by the drain electrode 50 of contact hole 70 and TFT 91.

Describe the manufacture method of the tft array substrate of the liquid crystal panel that adopts four road light shield operations in detail hereinafter with reference to Fig. 3 A～3D.

With reference to Fig. 3 A, adopt the first road light shield on substrate, to form first conductive pattern group that comprises grid line 11 (with reference to Fig. 1), grid 10 and grid pad 12.

With reference to Fig. 3 B, earlier deposit gate insulation layer 20, active layer 30 and ohmic contact layer 40 on the substrate of gate pattern successively being formed with, again deposition second conductive metal layer 50 on ohmic contact layer 40.Utilize the second road light shield on gate insulation layer 20, to form the pattern that comprises active layer 30 and ohmic contact layer 40 then, and second conductive pattern layer that comprises data wire 52 (with reference to Fig. 1), source electrode 51, drain electrode 50 and data pads 53 (with reference to Fig. 1).

With reference to Fig. 3 C, after second conductive layer pattern forms, then on substrate, use PECVD deposit passivation layer 60, after forming passivation layer,, form contact hole 61 by photoetching and the etching work procedure that adopts the 3rd road light shield.

With reference to Fig. 3 D, after contact hole 61 formed, deposition last layer transparency conducting layer 70 formed the 3rd conductive pattern group that comprises pixel electrode 78, grid pad top electrode 72 and data pads top electrode 73 on passivation layer by the 4th road light shield.

In LCD, because tft array substrate needs semiconductor process and many wheel light shield operations, therefore its manufacturing process is very complicated and manufacturing cost is than higher, and main cause is that one takes turns the light shield operation and comprises such as a plurality of operations such as thin film deposition operation, matting, photo-mask process, etching work procedure, photoresist lift off and inspection operations.

In order to address this problem, hope can provide a kind of manufacture method that can reduce the tft array substrate of light shield operation quantity.

Summary of the invention

Technical problem to be solved by this invention provides and a kind ofly adopts many gray-level masks and reduce the method for manufacturing thin film transistor array substrate of light shield operation quantity.

The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of method for manufacturing thin film transistor array substrate, may further comprise the steps:

One substrate is provided, and on this substrate, forms a first metal layer and one first photoresist layer, utilize one first light shield on this first metal layer, to form grid line, grid and grid pad;

On this substrate, continue to deposit a gate insulation layer, semi-conductor layer, an ohmic contact layer, one second metal level and one second photoresist layer successively, utilize one second light shield on this second metal level, to form source electrode, drain electrode, raceway groove and data wire bottom electrode and data pads bottom electrode;

On this substrate, continue deposition one transparency conducting layer and one the 3rd photoresist layer, utilize one the 3rd road light shield to form pixel electrode, source electrode top electrode, drain electrode top electrode and data wire top electrode and data pads top electrode;

Before the 3rd photoresist lift off, continue deposit passivation layer, by stripping process the 3rd photoresist on pixel electrode, source electrode top electrode, drain electrode top electrode and data wire top electrode and the data pads top electrode is peeled off together with the passivation layer on it afterwards.

In the said method, described second light shield is a gray-level mask more than.

The manufacture method that the present invention contrasts the thin-film transistor array base-plate of existing four road light shield operations has following beneficial effect: the present invention is by directly forming transparency conducting layer on second metal level, and before photoresist lift off deposit passivation layer, by stripping process the photoresist on pixel electrode, source electrode top electrode, drain electrode top electrode and data wire top electrode and the data pads top electrode is peeled off together with the passivation layer on it then, thereby reduced the light shield operation one, can simplify manufacture process, reduce cost, improve output.In addition, adopt the data wire of the thin-film transistor array base-plate of said method manufacturing to be formed, can effectively reduce data wire resistance, reduce the generation of broken data wire, improve yield by second metal level and transparency conducting layer.

Description of drawings

Fig. 1 is the plane graph of the tft array substrate of employing prior art four road light shield operations.

Fig. 2 is the sectional view along the A-A ' of Fig. 1 and B-B ' line drawing.

Fig. 3 A～3D is the making flow process cutaway view of the tft array substrate of prior art.

Fig. 4 is the plane graph of tft array substrate of the present invention.

Fig. 5 is the sectional view along the I-I ' of Fig. 4 and II-II ' line drawing.

Fig. 6 is according to plane graph and the sectional view of making first conductive pattern and grid pad contact hole method in the tft array substrate of the present invention.

Fig. 7 is according to plane graph and the sectional view of making semiconductor pattern and second conductive layer pattern and drain contact hole and data pads contact hole method in the tft array substrate of the present invention.

Fig. 8 is according to plane graph and the sectional view of making the 3rd conductive pattern group of methods in the tft array substrate of the present invention.

Embodiment

The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.

Figure 4 shows that plane graph, Figure 5 shows that along the I-I ' of Fig. 4 and the sectional view of II-II ' line drawing according to tft array substrate of the present invention.

With reference to Fig. 4 and Fig. 5, tft array substrate according to the present invention comprises the gate insulation layer 200, the TFT901 that is formed at each cross part that are formed on the infrabasal plate, is formed at by the pixel electrode in the pixel region that limits to chi structure 708.

And this tft array substrate also comprises storage capacitance, the grid pad 102 that is connected with grid line 101 that is formed at grid line 101 and pixel electrode 708 overlapping regions and is connected to data pads 503 on the data wire 502.

The grid line 101 that applies gate signal intersects to limit pixel region 708 with the data wire 502 that applies data-signal.

This TFT 901 response grid lines 101 signals apply picture element signal on the data wire 502 to pixel electrode 708.

The drain electrode 500 that this TFT 901 has the grid 100 that is connected to grid line 101, the source electrode 501 that is connected to data wire 502 and is connected to pixel electrode 708.

In addition, TFT 901 also has at source electrode 501 and drains between 500 and forms the active layer 300 of raceway groove, and wherein this active layer 300 is overlapping with gate insulation layer 200 and grid 100 under it, on this active layer 300 also with data wire overlapping 502.On this active layer 300, also be formed for the ohmic contact layer 400 of ohmic contact.

This pixel electrode 708 is connected to the drain electrode 500 of TFT901 and is formed in the pixel region 708.

Therefore form electric field applying the pixel electrode 708 of picture element signal by TFT 901 and apply between the public electrode of reference voltage.Because this electric field, the liquid crystal molecule between following array base palte and color membrane substrates is owing to anisotropy is rotated.The transmittance of pixel region changes according to the rotation degree of liquid crystal molecule, thereby shows various GTGs.

Grid pad 102 is connected to gate driver to apply gate signal to grid line 101.Grid pad 102 comprises grid pad bottom electrode 102, the grid pad top electrode 701 of extension from grid line, forms grid pad top electrode 701 and contact with grid pad bottom electrode 102 by running through gate insulation layer 200 contact holes on transparency conducting layer.

Data pads 503 is connected to data driver to apply data-signal to data wire 502.Data pads 503 comprises data pads bottom electrode 503 and the data pads top electrode 702 of extension from data wire 502, forms pixel electrode 708, data pads top electrode 702, drain electrode top electrode 700 and source electrode top electrode 704 transparent conductive patterns on transparency conducting layer.The top electrode of data pads, source electrode and drain electrode directly contacts with bottom electrode, and pixel electrode directly links to each other with drain electrode top electrode 700, thereby also links to each other with drain electrode bottom electrode 500.

Figure 6 shows that according to making plane graph and the sectional view that first conductive pattern comprises grid pad 102 in the tft array substrate of the present invention.

Please refer to Fig. 6 A and 6B, adopt the first road light shield operation on infrabasal plate, to form to have grid line 101, the gate pattern of grid 100 and grid pad bottom electrode 102.

On infrabasal plate, form the grid metal level by method such as sputter or other depositions.Thereafter photo-mask process and the etching work procedure by the first road light shield is patterned into predetermined structure with this metal level shown in Fig. 6 B, thereby forms the pattern that comprises grid line 101, grid 100 and grid pad bottom electrode 102.

Please refer to Fig. 7 A, formerly be formed with on the array base palte of first conductive layer pattern and deposit gate insulation layer 200 and semiconductor layer 300 and the ohmic contact layer 400 and second metal level 500.Pass through the photo-mask process and the etching work procedure of the second road HTM light shield thereafter, this metal level 500 and semiconductor layer 300 are patterned into predetermined structure, thereby form the semiconductor layer pattern that comprises active layer 300 and ohmic contact layer 400, and comprise data wire 502, second conductive pattern and the gate pads contact hole of source electrode 501, drain electrode 500 and data pads bottom electrode 503.

Photoresist shape thickness schematic diagram when Fig. 7 B is the second road light shield on array base palte, please refer to Fig. 7 B, the shading amount that this second road light shield has the light shield substrate that is made of transparent material, be formed on the lightproof area of light shield substrate and be formed at the light shield substrate is 1/2nd zone, thereby adopts behind the second road light shield exposure imaging this photoresist corresponding respectively to the second light shield shading light part and 1/2nd exposed portion burn-outs partly form the photoresist pattern with predetermined step.The photoresist 800 that makes photoresist 801 on raceway groove place 400, data wire bottom electrode 502, data pads bottom electrode 503, drain electrode bottom electrode 500 and the source electrode bottom electrode 501 have the first the highest height, the place except above-mentioned place and gate pads has second highly, has only the gate pads place not have photoresist.

Please refer to Fig. 7 C, get rid of by the etching first time then and do not have photoresist part just second conductive metal layer and the semiconductor layer and the ohmic contact layer at gate pads place, and after getting rid of half gate insulation layer of gate pads place, thereby adopt oxygen gas plasma to carry out the ashing operation and remove photoresist pattern, and reduce photoresist pattern with first height with second height.In process etching for the second time, raceway groove place 400, data wire bottom electrode 502, data pads bottom electrode 503, drain electrode bottom electrode 500 and source electrode bottom electrode 501 are sentenced outer second conductive metal layer 500 and ohmic contact layer 400 to be got rid of, and get rid of these local half thickness of gate insulation layer, also the whole gate insulation layers on the grid pad are got rid of simultaneously, thereby formed grid pad contact hole.

Employing such as sputtering method or other deposition processs are coated transparency conducting layer on above-mentioned array base palte, this transparency conducting layer is formed by tin indium oxide (ITO), tin oxide (TO), tin indium oxide zinc (ITZO) or indium zinc oxide (IZO).

Thereby photo-mask process and the formation of etching work procedure composition transparent conductive patterns by the 3rd road light shield comprises pixel electrode 708, data pads top electrode 702, drain electrode top electrode 700 and source electrode top electrode 704 transparent conductive patterns, the 3rd conductive pattern of grid pad top electrode 701 and data pads top electrode 702 then.This pixel electrode directly links to each other with drain electrode top electrode 700, thereby also links to each other with drain electrode bottom electrode 500.Electrode on this grid pad links to each other with the grid pad top electrode 701 that is formed by transparency conducting layer by the contact hole that runs through gate insulation layer.

Photoetching and etching technics by the 3rd road light shield will comprise pixel electrode 708, data pads top electrode 702, drain electrode top electrode 700 and source electrode top electrode 704 transparent conductive patterns, the transparency conducting layer in the place beyond grid pad top electrode 701 and the data pads top electrode 702 is carved, and second conductive layer at raceway groove place is carved, do through raceway groove again and carve, the ohmic contact layer at raceway groove place is carved, thereby formed raceway groove.

Please refer to Fig. 4 and Fig. 5 at last; be formed with deposit passivation layer 600 on the array base palte of transparent conductive patterns; afterwards by stripping process with pixel electrode 708; data pads top electrode 702; photoresist lift off on drain electrode top electrode 700 and the source electrode top electrode 704 is fallen; the passivation layer that also just will be deposited on these local photoresists has simultaneously also peeled off together; because this moment, raceway groove place and other before peeling off did not have the place of transparency conducting layer not have photoresist; raceway groove place and other do not have the passivation layer in the place of transparency conducting layer to be retained so, thus make these places particularly the semiconductor layer at raceway groove place can well be protected.

Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims

1. a method for manufacturing thin film transistor array substrate is characterized in that, said method comprising the steps of:

On this substrate, continue to deposit successively a gate insulation layer, semi-conductor layer, an ohmic contact layer, one second metal level and one second photoresist layer, utilize one second light shield to form source electrode, drain electrode, raceway groove and data wire bottom electrode and data pads bottom electrode on this second metal level, described second light shield is a gray-level mask more than;