CN101577102B - scan driver - Google Patents
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- CN101577102B CN101577102B CN2008100992020A CN200810099202A CN101577102B CN 101577102 B CN101577102 B CN 101577102B CN 2008100992020 A CN2008100992020 A CN 2008100992020A CN 200810099202 A CN200810099202 A CN 200810099202A CN 101577102 B CN101577102 B CN 101577102B
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Abstract
A scan driver includes a voltage setting circuit, a Counter circuit, a logic circuit, a Dynamic Decoder, N Level Shift circuits and N output stage circuits, where N is a natural number. The voltage setting circuit sets the N voltage signals to be at a first level. The counter circuit provides counting data to the logic circuit, and the logic circuit generates M control signals according to the counting data, wherein M is a natural number. The dynamic decoder includes a plurality of transistors arranged in N rows to receive N voltage signals, respectively. The transistors are also arranged in M rows, and are respectively controlled by M control signals to determine the levels of the N voltage signals. The N level conversion circuits respectively promote the levels of the N voltage signals, and the N output stage circuits respectively output N grid signals according to the N levels after the levels are promoted.
Description
Technical field
The relevant a kind of scanner driver (Scan Driver) of the present invention, and the scanner driver realized of particularly relevant a kind of applicating counter (Counter) and code translator (Decoder).
Background technology
In the epoch now that development in science and technology is maked rapid progress, LCD has been widely used in electronics and has shown on the product, such as TV, computer screen, notebook computer, mobile phone or personal digital assistant etc.LCD comprises data driver (Data Driver), scanner driver (Scan Driver) and display panels.Have pel array in the display panels, and scanner driver is scanned up to pixel in order to a plurality of pixel columns in the on-pixel array in regular turn with the pixel data with data driver output, and then demonstrates the image that desire shows.
Realize that with counter (Counter) collocation code translator (Decoder) technology of scanner driver is to exist.Traditionally, how to realize scanner driver with static decoders (Static Decoder).Yet,, therefore how to design the less and lower-cost offset buffer of area and be one of direction that industry endeavours because static decoders has circuit area and reach the cost problem of higher more greatly.
Summary of the invention
The invention provides a kind of scanner driver (Scan Driver), compared to traditional scanner driver, the scanner driver that the present invention proposes has the less and lower-cost advantage of circuit area.
Propose a kind of scanner driver according to the present invention, comprise voltage setting circuit, counter (Counter) circuit, dynamic decoder (Dynamic Decoder), a N level conversion (Level Shift) circuit and N output-stage circuit.Voltage setting circuit is first level in order to individual first voltage signal of setting on N the node in during voltage is set of N.Counter circuit produces enumeration data, and enumeration data comprises the K bit data, and the numerical value of enumeration data increases progressively 1 or change its count value every a fixed cycle, and K is a natural number.First logical circuit receives the K bit data, and produces M first control signal accordingly, and M is the natural number greater than K.Dynamic decoder comprises a plurality of the first transistors, and it is arranged and forms N rowed transistor circuit, and N rowed transistor circuit is coupled to N node respectively.The first transistor is also arranged and is formed M row transistor circuit, during an evaluation in, M row transistor circuit is controlled by M first control signal respectively, decides the level of N first voltage signal, N is a natural number.N level shifting circuit promotes the level of N first voltage signal respectively to produce N second voltage signal.N output-stage circuit receives N second voltage signal respectively, and exports N signal respectively.
Propose a kind of scanner driver according to the present invention, comprise voltage setting circuit, counter circuit, a dynamic decoder and N output-stage circuit.Voltage setting circuit is first level in order to individual first voltage signal of setting on N the node in during voltage is set of N.Counter circuit is in response to producing enumeration data, and enumeration data comprises the K bit data, and the numerical value of enumeration data increases progressively 1 or change its count value every a fixed cycle, and K is a natural number.First logical circuit receives the K bit data, and produces M first control signal accordingly.First logical circuit also promotes the level of M first control signal to produce M second control signal.Dynamic decoder comprises a plurality of the first transistors, and the first transistor is arranged and formed N rowed transistor circuit, and N rowed transistor circuit is coupled to N node respectively.The first transistor is also arranged and is formed M row transistor circuit, during an evaluation in, M row transistor circuit is controlled by the level that M second control signal decides N first voltage signal respectively, N is a natural number.N output-stage circuit receives N first voltage signal respectively, and exports N signal respectively.
Description of drawings
For foregoing of the present invention can be become apparent, below conjunction with figs. is elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 is the calcspar according to the scanner driver of first embodiment of the invention.
Fig. 2 is the operation timing figure of the scanner driver of Fig. 1.
Fig. 3 is the circuit diagram of the 0th rowed transistor of dynamic decoder 15 among Fig. 1.
Fig. 4 is the circuit diagram of holding circuit 24_y among Fig. 1.
Fig. 5 is the circuit diagram of the functional circuit among the voltage setup unit 22_u.
Fig. 6 is the 0th row of Sheffer stroke gate planar circuit 16 among Fig. 1 and the circuit diagram of the 1st rowed transistor.
Fig. 7 is the calcspar according to the scanner driver of second embodiment of the invention.
Fig. 8 is the calcspar according to the scanner driver of third embodiment of the invention.
Fig. 9 is among Fig. 8 or the circuit diagram of the 0th rowed transistor of on-plane surface circuit 56.
Figure 10 is the calcspar according to the scanner driver of fourth embodiment of the invention.
Figure 11 is another circuit diagram of holding circuit 24_y among Fig. 1.
Figure 12 is the circuit diagram according to the output-stage circuit 20_y of second embodiment of the invention.
Figure 13 is another circuit diagram according to the output-stage circuit 20_y of second embodiment of the invention.
Figure 14 is the coherent signal timing diagram according to the control signal CTL of first embodiment of the invention and CTL2.
Embodiment
The scanner driver of realizing with dynamic decoder (Dynamic Decoder) collocation counter circuit (Counter) (Scan Driver) that the embodiment of the invention proposes.
First embodiment
Present embodiment proposes the scanner driver with the dynamic decoder realization of the Sheffer stroke gate planar circuit (NAND Plane Circuit) of using low-voltage technology.Please refer to Fig. 1, it is the calcspar according to the scanner driver of first embodiment of the invention.Scanner driver 10 comprises counter circuit 12, logical circuit 14, dynamic decoder 15, level shifting circuit 18_0～18_N-1, output-stage circuit 20_0～20_N-1 and maintenance (Holding) circuit 24_0～24_N-1, and N is a natural number.Dynamic decoder 15 comprises NAND planar circuit 16 and voltage setting circuit 22.
Please refer to Fig. 2, it is the operation timing figure of the scanner driver of Fig. 1.The operation timing of scanner driver 10 mainly is divided into voltage set during T_E during T_P and the evaluation.Among the T_P, voltage setting circuit 22 is set in order to node nd_0～nd_N-1 is carried out voltage level, makes the voltage signal Vo_1～Vo_N-1 on node nd_0～nd_N-1 equal first level during voltage is set.Among the T_E, counter 12 produces the enumeration data that comprises K bit data BD_0～BD_K-1 during evaluation.Logical circuit 14 produces M control signal SC_0～SC_M-1 according to bit data BD_0～BD_K-1.M control signal SC_0～SC_M-1 is in order among the T_E during evaluation, and the N rowed transistor of control NAND planar circuit 16 forms N level control circuit equivalently, to control the level of voltage Vo_0～Vo_N-1 respectively.Wherein, M, N and K are natural number.For instance, M equals 2K, the K power that N equals 2.Next, equaling 8,16 and 256 example respectively with K, M and N comes the operation of scanner driver 10 is described further.
Comprise in the voltage setting circuit 22 the individual voltage setup unit of N (=256) 22_0,22_1,22_2 ... and 22_N-1 (=255), it is respectively in order to level to the first level of setting voltage signal Vo_0～Vo_N-1 (=255) among the T_P during voltage is set.First level for example equals the level VDD of the ceiling voltage of scanner driver 10.Each voltage setup unit 22_0～22_255 has close circuit structure and operation, next, is that example is done explanation to the operation of other voltage setup unit with i voltage setup unit 22_i.Wherein, i is more than or equal to 0, less than the integer of N (=256).
Voltage setup unit 22_i comprises transistor T 1 and T2.The first input end incoming level VDD of transistor T 1, second input end is coupled to node nd_i, and control end receives control signal CTL.Among the T_P, transistor T 1 controlled signal CTL activation is so that the level of voltage signal Vo_i equals level VDD during voltage is set.For instance, control signal CTL is in low level among the T_P during voltage is set, transistor T 1 be P-type mos (Metal Oxide Semiconductor, MOS) transistor, with T_P during voltage is set by low level control signal CTL activation.
The first input end of transistor T 2 is coupled to node nd_i, and second input end is coupled to the output terminal of the i rowed transistor of NAND planar circuit 16, and control end receives control signal CTL.During voltage is set among the T_P, transistor T 2 controlled signal CTL disableds, this moment, transistor T 1 can provide level VDD as voltage signal Vo_i.During evaluation among the T_E, transistor T 2 controlled signal CTL activations, this moment, the output terminal of i rowed transistor was coupled to node nd_i, and this moment, the i rowed transistor can be controlled the level of voltage Vo_i accordingly.Transistor T 2 is a N type MOS transistor, with T_E during evaluation by the control signal CTL activation of high level.
As shown in Figure 3, if above-mentioned nd_i is the drain end of transistor SC_15, above-mentioned T2 transistor can be any the N type MOS transistor in this i string NAND circuit, promptly the control signal SC_1 among Fig. 3, SC_3 ... and in the corresponding transistor of controlling of SC_15 institute any all can be used as above-mentioned T2 transistor.
Other voltage setup unit has identical structure with voltage setup unit 22_i in the voltage setting circuit 22 among Fig. 1, level with the corresponding voltage signal of control among the T_P during voltage is set equals level VDD, and the output terminal that during evaluation, makes 256 rowed transistors in the NAND planar circuit 16 among the T_E respectively respectively short circuit be connected to node nd_1～nd_255.
Enumeration data comprises K (=8) bit data BD_1～BD_K-1 (=7), it for example is respectively least significant bits data (the Least Significant Bit of enumeration data, LSB), inferior lower bit number according to ... and the most significant bits data (Most Significant Bit, MSB).In the present embodiment, counter circuit 12 output count datas for example are Gray code (Gray Code) form.
Logical circuit 14_j receives bit data BD_j, and exports as control signal SC_2j and SC_2j+1 respectively with the oppisite phase data of bit data BD_j and bit data BD_j.For instance, j equals 0, and logical circuit 14_1 receives bit data BD_0, and respectively with the oppisite phase data of bit data BD_0 and bit data BD_0 as control signal SC_0 and SC_1.Logical circuit 14_0 also exports the row of the 1st in control signal SC_0 and SC_1 to the M row transistor and second row transistor respectively, to control its operation respectively.
Other logical circuit 14_1～14_7 carries out the operation close with logical circuit 14_0, providing bit data BD_1～BD_7 as control signal SC_2, SC_4, SC_6, SC_8, SC_10, SC_12 and SC_14 respectively, and the inversion signal that bit data BD_2～BD_7 is provided respectively is as control signal SC_3, SC_5, SC_7, SC_9, SC_11, SC_13 and SC_15.
The x rowed transistor comprises that 8 transistors, voltage sets the transistor of usefulness and the transistor of an evaluation switch, and it is controlled by 8 control signals among control signal SC_0～SC_255 respectively and conducting or end among T_E during evaluation.Form grounding path when the x rowed transistor equals x in order to the numerical value in enumeration data, with the level that drags down node nd_x to earth level.When the numerical value of enumeration data was not equal to x, the level of node nd_x was set in level VDD because of what T_P voltage made during setting, and the x rowed transistor is because form the path of opening circuit, so the level of node nd_x is in level VDD constantly.
For instance, x equals 0, the 0 rowed transistor and equals [00000000] in order to the numerical value in enumeration data
2The time form short circuit paths.Serial transistor in the 0th rowed transistor comprises that grid receives the transistor of the oppisite phase data of bit data BD_0～BD_7, promptly be that the 0th rowed transistor is 8 transistorized series circuits that grid receives control signal SC_1, SC_3, SC_5, SC_7, SC_9, SC_11, SC_13 and SC_15, as shown in Figure 3.So, the 0th rowed transistor can equal at the numerical value of enumeration data 0 and CTL drag down the level of node nd_0 to earth level when making transistor T C conducting.
Though only equaling 0 situation with x in aforesaid operations narration is that example explains, yet, when x equals other numerical value in 1～255, the the 1st～the 255th corresponding rowed transistor also can be carried out the operation close with the 0th rowed transistor, with the level that drags down node nd_1～nd_255 accordingly to earth level.By the aforesaid operations narration as can be known, during an evaluation, among the T_E, be only to have a voltage signal to be in earth level.In addition, when the numerical value of enumeration data increases progressively 1 every the fixed cycle, voltage signal Vo_0～Vo_255 is in earth level among the T_E during the evaluation continuously at 255 in order.
Level shifting circuit 18_0～18_N-1 (=255) is respectively in order to change the level of the last voltage signal Vo_0～Vo_255 of node nd_0～nd_255, with the level of booster tension signal Vo_0～Vo_255, and correspondence obtains voltage signal Vo ' _ 0～Vo ' _ 255.Output-stage circuit 20_0～20_N-1 (=255) promotes all voltage signal Vo ' _ 0～Vo ' _ 255 output scanning signal G0～G255 according to level respectively.Wherein sweep signal G0～G255 for example is the high level enable signal, and output-stage circuit 20_0～20_255 for example has the characteristic of anti-phase output, and it is exported as sweep signal G0～G255 with the inversion signal of voltage signal Vo ' _ 0～Vo ' _ 255 respectively.Wherein, level shifting circuit 18_0～18_255 and circuit of output terminal 20_0～20_255 for example are the circuit of high voltage technology.
The scanner driver 10 of present embodiment is to produce sweep signal G0～G255 with arrange in pairs or groups counter 12 of the dynamic decoder 15 with NAND planar circuit 16 and voltage setting circuit 22.Compared to traditional scanner driver, the scanner driver 10 of present embodiment has that the required transistor size of code translator is less, circuit area is less and lower-cost advantage.
In addition, the NAND planar circuit 16 of present embodiment and voltage setting circuit 22 are the series circuit of many N type MOS transistor.So, when circuit layout (Layout) is planned, can plan with the mode of drain electrode (Drain) by making two adjacent transistor that are one another in series share source electrode (Source).So, the scanner driver 10 of present embodiment and the circuit size of dynamic decoder 15 can be dwindled further.
In addition, because the enumeration data of present embodiment is the Gray code form, when enumeration data increases progressively, once only change the numerical value of a bit data.So, presentation logic circuit 14 only need be adjusted the level of two control signals accordingly when the numerical value of any enumeration data increases progressively.For example, when enumeration data varies to numerical value 3 by numerical value 2, be only bit data BD_0 to be changed into numerical value 0 by numerical value 1.Logical block 14 only need be adjusted control signal SC_0 (=bit data BD_0) accordingly and become numerical value 0 by numerical value 1, and adjustment control signal SC_1 (inversion signal of=bit data BD_0) becomes numerical value 1 by numerical value 0.So, can reduce the electric power that to consume when 14 pairs of NAND planar circuits 16 of logical circuit are controlled.
In the present embodiment, control signal CTL for example is that (it is that T_P is a low level during voltage is set, so that scanner driver 10 stops output scanning signal G0～G255 for GateOutput Enable, GOE) signal for the grid output enable of scanner driver 10.The GOE signal also during evaluation T_E be in high level, with activation scanner driver 10 output scanning signal G0～G255.
The scanner driver 10 of present embodiment also designs a feedback path in holding circuit 24_0～24_N-1 (=255), keep the level of voltage signal Vo ' _ 0～Vo ' _ 255, be subjected to the influence of dynamic loss (Dynamic Leakage) and produce mistake (for example during voltage is set among the T_P, voltage signal Vo ' _ 1 of high level is pulled low near earth level by the parasitic grounding path in the circuit) with the level of avoiding voltage signal Vo ' _ 0～Vo ' _ 255.Because each holding circuit 24_0～24_255 all has identical design, therefore, be that example explains only next with circuit of output terminal 24_y wherein, y is more than or equal to 0, the integer less than 256.
Please refer to Fig. 4, it is the circuit diagram of holding circuit 24_y among Fig. 1.Holding circuit 24_y comprises phase inverter series circuit 25 and transistor T 3.Phase inverter series circuit 25 for example is in series by t (t=s+j) level phase inverter, and its input end receives the voltage signal Vo_y that corresponding y string NAND circuit provides, and its output terminal is in order to provide the input signal of level shifting circuit.Feedback path VC in this example is couple to the gate terminal of transistor T 3, and wherein VC is the phase inverter output of s level, and s is necessary for odd number, and control signal VC is the inversion signal of voltage signal Vo ' _ y.T is whether odd number is by the output stage phase decision.
Among the T_P, transistor T 3 is made voltage signal Vo_y remain on high level sustainably by low level control signal VC conducting constantly during voltage is set.And other holding circuit 24_0～24_N-1 also has close structure and operation with holding circuit 24_y, remains on high level to make the level of corresponding voltage signal among the T_P during voltage is set.
The same, as changing Fig. 4 into Figure 11, be better embodiment; Draw the switch T5 of (Pull-up) in many controls, by control signal CTL2 decision folding, the timing diagram between its CTL2 and the CTL as shown in figure 14, CTL2 and CTL are nonoverlapping signal, wherein nonoverlapping emphasis exists:
Δt2＞0。
So can avoid transferring the electronegative potential DC electric current consume of moment to by noble potential as Vo_y.
14_0～14_K among the logical block of present embodiment such as Fig. 1, also in order to receive control signal XON (one of application function of scanner driver), and in response to control signal XON during whole activations in the T_ON control NAND planar circuit 16 all transistors be conducting, with the level that drags down voltage signal Vo_0～Vo_N-1 (=255) to earth level.Wherein, the signal waveform of control signal XON as shown in Figure 2.So, can be in the sweep signal G0～GN-1 (=255) of high level simultaneously, promptly be that to obtain all be the sweep signal G0～G255 of activation.So, the scanner driver 10 of present embodiment can have the function of the whole activations of sweep signal G0～G255 (All on).
Though in the present embodiment only to pass through all crystals pipe in logical block 14_0～14_K conducting NAND planar circuit 16 and the voltage setting circuit 22 as scanner driver among Fig. 1 10, with the circuit design that reaches sweep signal G0～G255 that output is in high level simultaneously is that example explains, yet the scanner driver 10 of present embodiment is not limited to adopt the aforementioned circuit design, and also can reach identical operations by the circuit design of other form.
For instance, also can be in each voltage setup unit 22_0～22_255 the design function circuit, to come respectively voltage signal Vo_0～Vo_255 with correspondence to drag down in response to control signal XON is earth level, and so, can produce all is the sweep signal G0～G255 of activation.Because the functional circuit among each voltage setup unit 22_0～22_255 all has identical structure and operation, is that example explains with the functional circuit in voltage setup unit 22_u next, u is more than or equal to 0, the integer less than 256.
Please refer to Fig. 5, it is the circuit diagram of the functional circuit among the voltage setup unit 22_u.Functional circuit 28 comprises transistor T 4, and first input end is coupled to node nd_u, and second input end receives earth level, and control end receives control signal XON.Transistor T 4 for example is a N type MOS transistor, with control signal XON conducting in response to high level, with the level that drags down voltage signal Vo_u to earth level.So, also can make voltage signal Vo_u equal earth level effectively, and to make sweep signal Gu be activation by transistor T 4.And the functional circuit in other voltage setup unit also can be carried out and functional circuit 28 identical operations, drawing all voltage signal Vo_0～Vo_255 to earth level, and all sweep signal G0～G255 of activation.
Though the situation that only with the enumeration data is the Gray code form in the present embodiment is that example explains, yet enumeration data is not limited to the Gray code form, and also can be the binary data format of other any form.
Though in the present embodiment only to form the N rowed transistor as the transistor arrangement in NAND planar circuit 16 among Fig. 1 and the voltage setting circuit 22, and the situation that each N rowed transistor has NAND type circuit structure is that example explains, yet the transistor in NAND planar circuit 16 and the voltage setting circuit 22 is not limited to be arranged in the N row, and more can further simplify the circuit structure of NAND planar circuit 16 and voltage setting circuit 22 by various circuit design skills.
In an example, because two adjacent rowed transistors have close circuit structure in NAND planar circuit 16 and the voltage setting circuit 22, therefore, can further simplify the circuit structure of NAND planar circuit 16 and voltage setting circuit 22 by the transistor circuit of part in two rowed transistors in shared NAND planar circuit 16 and the voltage setting circuit 22.For instance, the circuit structure difference of row of the 0th in the NAND planar circuit 16 and the 1st rowed transistor only is that the transistor of reception earth level wherein is respectively transistor T a and the Tb that is controlled by control signal SC_1 and SC_0, as shown in Figure 6.Because remaining transistor circuit has equal structure in the 0th row and the 1st rowed transistor, the user can be by coupling node nda and ndb, and omit the circuit of transistor T d0～Td6.So, the 0th of present embodiment the row and the 1st rowed transistor can reach identical operations by the transistor of negligible amounts.
The aforementioned circuit simplification technique also can be spreaded to the NAND planar circuit 16 in other rowed transistor, to simplify the circuit structure of each rowed transistor.In other example, similar circuit reduction skill also can be spreaded to the transistors share transistor circuit that makes more than two row.
In the present embodiment, though be that example explains as the situation of control signal CTL only with GOE signal (one of application function of scanner driver), yet control signal CTL is not limited to the GOE signal, and also can be the signal that produces by other logical circuit, for example the CTL in the present embodiment is preferably in control signal XON during whole activations, keep noble potential simultaneously, can prevent to cause unnecessary big electric current as the T1 among Fig. 5 and T4 conducting simultaneously.Though the situation that only is N type MOS transistor with the transistor that comprises in the NAND planar circuit 16 is that example explains in the present embodiment, yet NAND planar circuit 16 also can be realized by P type MOS transistor.
The scanner driver of present embodiment is to realize with dynamic decoder with NAND planar circuit and collocation counter.Compared to traditional scanner driver, the scanner driver of present embodiment has that the required transistor size of code translator is less, circuit area is less and lower-cost advantage.
In addition, the dynamic decoder of present embodiment is the series circuit of many N type MOS transistor.So, when topological design, can design by the mode that makes two adjacent transistor that are one another in series share source electrode and drain electrode.So, the scanner driver of present embodiment can be dwindled further.
In addition, because the enumeration data of present embodiment is the Gray code form, when enumeration data increases progressively, once only change the numerical value of a bit data.So, can reduce the electric power that to consume when logical circuit is controlled dynamic decoder, make the scanner driver of present embodiment have the advantage of comparatively power saving.
Second embodiment
Present embodiment proposes the scanner driver with the dynamic decoder realization of the NAND planar circuit of application of high voltages technology.Please refer to Fig. 7, it is the calcspar according to the scanner driver of second embodiment of the invention.The scanner driver 30 of present embodiment and scanner driver 10 differences among first embodiment, the scanner driver 30 that is present embodiment is that level shifting circuit is integrated in the logical circuit 34.So, the logical circuit 34 of present embodiment, dynamic decoder 35 (it comprises NAND planar circuit 36 and voltage setting circuit 42) and output-stage circuit 40_0～40_255 are the circuit of high voltage technology.
In the scanner driver 30 of present embodiment, level shifting circuit is the input side that is arranged at dynamic decoder 35.So, the scanner driver 30 of present embodiment only need be provided with the level that the individual level shifting circuit of K (=8) is changed bit data BD_0～BD_7.So, compared to the scanner driver 10 of first embodiment, the number of the level shifting circuit of scanner driver 30 required uses can drop to K (=8) from numerical value of N (=256) significantly.So, compared to the scanner driver 10 of first embodiment, the scanner driver 30 of present embodiment also can dwindle circuit area further.And compared to traditional scanner driver, the scanner driver 30 of present embodiment also has that the required transistor size of code translator is less, circuit area is less, cost is low and the control operation of the code translator advantage of power saving comparatively.
Because level shifting circuit has been lacked in the output of dynamic decoder 35, so holding circuit can combine with output-stage circuit among Fig. 1, so output-stage circuit as shown in figure 12.The positive antiphase of output-stage circuit can change on demand.Present embodiment adopt anti-phase output-stage circuit (S=1, J=0), to save the element number.
The same, as drawing the switch T5 of (Pull-up) in many controls, by control signal CTL2 decision folding, as shown in figure 13.The same first embodiment is described, so can avoid transferring the electronegative potential DC electric current consume of moment as Vo_y to by noble potential.
The 3rd embodiment
Present embodiment proposes the scanner driver with the dynamic decoder realization of the rejection gate planar circuit (NOR Plane Circuit) of using low-voltage technology.Please refer to Fig. 8, it is the calcspar according to the scanner driver of third embodiment of the invention.Scanner driver 10 differences of the scanner driver 50 of present embodiment and first embodiment are that its dynamic decoder 55 has NOR planar circuit 56, wherein have the transistor that N (=256) row are arranged with the capable circuit structure of NOR.Each rowed transistor includes the transistor of the individual parallel connection of K (=8), and these 8 transistorized first input ends are coupled to the output terminal of each rowed transistor, second input end reception earth level.Because each rowed transistor in the NOR planar circuit 56 has identical operations, next the example that is operating as with the z rowed transistor in the NOR planar circuit 56 explains, and z is more than or equal to 0, the integer less than 256.
The z rowed transistor comprises 8 transistors, and it is controlled by 8 control signals among control signal SC_0～SC_255 respectively and conducting or end among T_E during evaluation.When the z rowed transistor equals z in order to the numerical value in enumeration data respectively, form the path of opening circuit equivalently, make that the voltage signal Vo_z on the corresponding node nd_z can maintain level VDD.And when the numerical value of enumeration data was not equal to z, the z rowed transistor was to form grounding circuit equivalently to go up the level of voltage signal Vo_z to earth level to drag down node nd_z.
For instance, z equals 0, the 0 rowed transistor and equals to form the path of opening circuit at [00000000] 2 o'clock in order to the numerical value in enumeration data.Serial transistor in the 0th rowed transistor comprises that grid receives the transistor of bit data BD ' _ 1～BD ' _ 7, promptly be that the 0th rowed transistor is 8 transistorized parallel circuits that grid receives control signal SC ' _ 0, SC ' _ 2, SC ' _ 4, SC ' _ 6, SC ' _ 8, SC ' _ 10, SC ' _ 12 and SC ' _ 14, as shown in Figure 9.So, the 0th rowed transistor can equal at the numerical value of enumeration data to form the path of opening circuit at 0 o'clock, makes the level of the voltage signal Vo_0 on node nd ' _ 0 maintain level VDD.And be not equal at 0 o'clock at the numerical value of enumeration data, at least one transistor is conducting in the 0th rowed transistor, makes the 0th rowed transistor form grounding path, with the level that drags down the voltage signal Vo_0 on node nd ' _ 0 to earth level.
Though only equaling 0 situation with z in aforesaid operations narration is that example explains, yet, when z equals other numerical value in 1～255, the the 1st～the 255th corresponding rowed transistor also can be carried out the operation close with the 0th rowed transistor, is level VDD with the level of keeping node nd ' _ 1～nd ' _ 255 accordingly.By the aforesaid operations narration as can be known, during an evaluation, among the T_E, only there is a voltage signal to maintain level VDD.Output-stage circuit 60_0～the 60_255 of present embodiment does not for example have anti-phase output characteristics, and directly with the sweep signal output of voltage signal Vo ' _ 0～Vo ' _ 255 as the high level activation.
Though the situation that only has an identical structure with voltage setting circuit in the dynamic decoder 55 62 and voltage setting circuit 22 among first embodiment is that example explains in the present embodiment, yet the voltage setting circuit 62 of present embodiment also can save transistor T 2 wherein, only keep transistor T 1, and will be at the control signal CTL in first example, add together computing of logic unit circuit 54, then can finish by low voltage component.Wherein holding circuit is with described in first embodiment.
In sum, compared to traditional scanner driver, the scanner driver 30 of present embodiment also has that the required transistor size of code translator is less, circuit area is less, lower-cost advantage.
The 4th embodiment
Present embodiment proposes the scanner driver with the dynamic decoder realization of the NOR planar circuit of application of high voltages technology.Please refer to Figure 10, it is the calcspar according to the scanner driver of fourth embodiment of the invention.The scanner driver 70 of present embodiment and scanner driver 50 differences among the 3rd embodiment are that the scanner driver 70 of present embodiment is that level shifting circuit is integrated in the logical circuit 74.So, the logical circuit 74 of present embodiment, dynamic decoder 75 (it comprises NOR planar circuit 76 and voltage setting circuit 82) and output-stage circuit 80_0～80_255 are the circuit of high voltage technology.So, compared to the scanner driver 50 of the 3rd embodiment, the scanner driver 70 of present embodiment also can dwindle circuit area further.And compared to traditional scanner driver, the scanner driver 70 of present embodiment also has that the required transistor size of code translator is less, circuit area is less, the low advantage of cost.Wherein holding circuit is with described in second embodiment.
In sum, though the present invention with preferred embodiment exposure as above, yet it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various changes that are equal to or replacement.Therefore, protection scope of the present invention is when looking accompanying being as the criterion that the application's claim defined.
Claims (28)
1. scanner driver comprises:
One counter circuit, in order to produce an enumeration data, this enumeration data comprises the K bit data, and the numerical value of this enumeration data increases progressively 1 or change its count value every a fixed cycle, and K is a natural number;
One first logical circuit receives this K bit data, and produces M first control signal accordingly, and M is the natural number greater than K;
One dynamic decoder comprises:
One voltage setting circuit is one first level in order to individual first voltage signal of setting on N the node in during voltage is set of N, and N is a natural number; And
A plurality of the first transistors, it is arranged and forms N rowed transistor circuit, this N rowed transistor circuit is coupled to this N node respectively, these the first transistors are also arranged and are formed M row transistor circuit, in during an evaluation, this M row transistor circuit is controlled by this M first control signal respectively, decides the level of this N first voltage signal;
N level shifting circuit, the level that promotes this N first voltage signal respectively is to produce N second voltage signal; And
N output-stage circuit receives this N second voltage signal respectively, and exports N signal respectively.
2. scanner driver according to claim 1 is characterized in that N output terminal of dynamic decoder is coupled to the input end of N holding circuit respectively, and the output terminal of this N holding circuit is coupled to the input end of this N level shifting circuit respectively.
3. scanner driver according to claim 1 is characterized in that the connection that is one another in series of transistor in this N rowed transistor circuit, and an end of this N rowed transistor circuit is coupled to this N node respectively, and the other end receives one second level.
4. scanner driver according to claim 1, it is characterized in that respectively this N rowed transistor circuit comprises a plurality of transistors, these transistors respectively comprise a control end, a first input end and one second input end, wherein this first input end is coupled to node corresponding in this N node, this second input end receives one second level, and this control end receives the first corresponding control signal in this M first control signal.
5. scanner driver according to claim 1 is characterized in that this voltage setting circuit comprises:
N transistor seconds, first input end is coupled to this N node respectively, second input end receives a reference voltage respectively, control end receives one second control signal, this N transistor seconds during this voltage is set in by this second control signal conducting, so that this N of this reference voltage system to be provided respectively a node.
6. scanner driver according to claim 5 is characterized in that this voltage setting circuit also comprises:
N the 3rd transistor, first input end is coupled to this N node respectively, second input end is coupled to this N output terminal respectively, control end receives this second control signal, this N the 3rd transistor during this evaluation in by this second control signal conducting, to couple this N node respectively to this N output terminal.
7. scanner driver according to claim 5 is characterized in that the grid output enable signal of this second control signal for this scanner driver.
8. scanner driver according to claim 1 is characterized in that respectively this N output-stage circuit comprises:
One phase inverter series circuit, the input end of first order phase inverter wherein receives one second voltage signal that change-over circuit corresponding in this N change-over circuit provides, the output terminal of i level phase inverter wherein provides one the 3rd control signal, the 3rd control signal and this second voltage signal are anti-phase, and i is an odd number; And
One the 4th transistor is in order to keep the level of this second voltage signal in response to the 3rd control signal;
Wherein, the output terminal of the afterbody phase inverter in this phase inverter series circuit is in order to export a signal corresponding in this N signal.
9. scanner driver according to claim 8 is characterized in that this output-stage circuit also comprises:
One the 5th transistor, with the 4th transistor series, the 5th transistor is controlled by one the 4th control signal.
10. scanner driver according to claim 1 is characterized in that also comprising:
One functional circuit equals a particular level in order to set this N first voltage signal during whole activations, and making this N signal all is activation.
11. scanner driver according to claim 1, it is characterized in that this first logical circuit is also in order to receive a control signal, and during whole activations, control the capable the first transistor of this M in response to this control signal and equal a particular level to set this N first voltage signal, making this N signal all is activation.
12. scanner driver according to claim 1 is characterized in that this enumeration data is the Gray code form.
13. scanner driver according to claim 1 is characterized in that:
M equals 2K, and this M first control signal comprises this K bit data and K antiphase data;
Respectively this M row transistor circuit comprises (K-1) power transistor of 2; And
The K power that N equals 2, respectively this N rowed transistor circuit comprises K transistor.
14. a scanner driver comprises:
One counter circuit, in order to produce an enumeration data, this enumeration data comprises the K bit data, and the numerical value of this enumeration data increases progressively 1 or change its count value every a fixed cycle, and K is a natural number;
One first logical circuit receives this K bit data, and produces M first control signal accordingly, and this first logical circuit also comprises a level shifting circuit, in order to the level that promotes this M first control signal to produce M second control signal;
One dynamic decoder comprises:
One voltage setting circuit is one first level in order to individual first voltage signal of setting on N the node in during voltage is set of N, and N is a natural number; And
A plurality of the first transistors, arrange and form N rowed transistor circuit, this N rowed transistor circuit is coupled to this N node respectively, these the first transistors are also arranged and are formed M row transistor circuit, in during an evaluation, this M row transistor circuit is controlled by this M second control signal respectively, decides the level of this N first voltage signal; And
N output-stage circuit receives this N first voltage signal respectively, and exports N signal respectively.
15. scanner driver according to claim 14 is characterized in that N output terminal of dynamic decoder is coupled to the input end of N holding circuit, the output terminal of this N holding circuit is coupled to the input end of this N output-stage circuit respectively.
16. scanner driver according to claim 14 is characterized in that the connection that is one another in series of transistor in this N rowed transistor circuit, an end of this N rowed transistor circuit is coupled to this N node respectively, and the other end receives one second level.
17. scanner driver according to claim 14, it is characterized in that respectively this N rowed transistor circuit comprises a plurality of transistors, these transistors respectively comprise a control end, a first input end and one second input end, wherein this first input end is coupled to node corresponding in this N node, this second input end receives one second level, and this control end receives the first corresponding control signal in this M first control signal.
18. scanner driver according to claim 14 is characterized in that this voltage setting circuit comprises:
N transistor seconds, first input end is coupled to this N node respectively, second input end receives a reference voltage respectively, control end receives one second control signal, this N transistor seconds during this voltage is set in by this second control signal conducting, so that this N of this reference voltage system to be provided respectively a node.
19. scanner driver according to claim 18 is characterized in that this voltage setting circuit also comprises:
N the 3rd transistor, first input end is coupled to this N node respectively, second input end is coupled to this N output terminal respectively, control end receives this second control signal, this N the 3rd transistor during this evaluation in by this second control signal conducting, to couple this N node respectively to this N output terminal.
20. scanner driver according to claim 18 is characterized in that the grid output enable signal of this second control signal for this scanner driver.
21. scanner driver according to claim 14 is characterized in that respectively this N output-stage circuit comprises:
One phase inverter series circuit, the input end of first order phase inverter wherein receives one first corresponding voltage signal in this N first voltage signal, the output terminal of i level phase inverter wherein provides one the 3rd control signal, and the 3rd control signal and this first voltage signal are anti-phase, and i is an odd number; And
One the 4th transistor is in order to keep the level of this first voltage signal in response to the 3rd control signal;
Wherein, the output terminal of the afterbody phase inverter in this phase inverter series circuit is in order to export a signal corresponding in this N signal.
22. scanner driver according to claim 21 is characterized in that this output-stage circuit also comprises:
One the 5th transistor, with the 4th transistor series, the 5th transistor is controlled by one the 4th control signal.
23. scanner driver according to claim 14 is characterized in that also comprising:
One functional circuit equals a particular level in order to set this N first voltage signal during whole activations, and making this N signal all is activation.
24. scanner driver according to claim 14, it is characterized in that this first logical circuit is also in order to receive a control signal, and during whole activations, control the capable the first transistor of this M in response to this control signal and equal a particular level to set this N first voltage signal, making this N signal all is activation.
25. scanner driver according to claim 14 is characterized in that this enumeration data is the Gray code form.
26. scanner driver according to claim 14 is characterized in that:
M equals 2K, and this M second control signal comprises this K bit data and K antiphase data;
Respectively this M row transistor circuit comprises (K-1) power transistor of 2; And
The K power that N equals 2, respectively this N rowed transistor circuit comprises K transistor.
27. a scanner driver comprises:
One counter circuit is in order to produce an enumeration data;
One first logical circuit receives this enumeration data, and produces a plurality of first control signals accordingly;
One dynamic decoder comprises:
One voltage setting circuit is one first level in order to a plurality of first voltage signals of setting in during voltage is set; And
A plurality of the first transistors are coupled to this voltage setting circuit, during an evaluation in, be controlled by this a plurality of first control signals, decide the level of these a plurality of first voltage signals;
A plurality of level shifting circuits, the level that promotes these a plurality of first voltage signals respectively is to produce a plurality of second voltage signals; And
A plurality of output-stage circuits receive these a plurality of second voltage signals respectively, and export a plurality of signals respectively.
28. a scanner driver comprises:
One counter circuit is in order to produce an enumeration data;
One first logical circuit receives this enumeration data, and produces a plurality of first control signals accordingly, and this first logical circuit also comprises a level shifting circuit, in order to the level that promotes these a plurality of first control signals to produce a plurality of second control signals;
One dynamic decoder comprises:
One voltage setting circuit is one first level in order to a plurality of first voltage signals of setting in during voltage is set; And
A plurality of the first transistors are coupled to this voltage setting circuit, during an evaluation in, be controlled by this a plurality of second control signals, decide the level of these a plurality of first voltage signals; And
A plurality of output-stage circuits receive these a plurality of first voltage signals respectively, and export a plurality of signals respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100992020A CN101577102B (en) | 2008-05-08 | 2008-05-08 | scan driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100992020A CN101577102B (en) | 2008-05-08 | 2008-05-08 | scan driver |
Publications (2)
| Publication Number | Publication Date |
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| CN101577102A CN101577102A (en) | 2009-11-11 |
| CN101577102B true CN101577102B (en) | 2011-09-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008100992020A Expired - Fee Related CN101577102B (en) | 2008-05-08 | 2008-05-08 | scan driver |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010039208A (en) * | 2008-08-05 | 2010-02-18 | Nec Electronics Corp | Gate line drive circuit |
| TWI457909B (en) | 2012-05-29 | 2014-10-21 | Sitronix Technology Corp | Scan the drive circuit |
| CN102708827B (en) * | 2012-06-01 | 2014-08-20 | 矽创电子股份有限公司 | scan drive circuit |
| TWI483196B (en) * | 2012-10-31 | 2015-05-01 | Sitronix Technology Corp | Decode scan drive |
| CN104851391B (en) * | 2015-05-20 | 2017-10-17 | 深圳市华星光电技术有限公司 | A kind of drive circuit |
| CN112703552A (en) * | 2018-10-10 | 2021-04-23 | 深圳市柔宇科技股份有限公司 | GOA circuit and display device |
| WO2020124604A1 (en) * | 2018-12-21 | 2020-06-25 | 深圳市柔宇科技有限公司 | Display panel and driving method thereof, display device, and terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6239775B1 (en) * | 1997-06-14 | 2001-05-29 | Lg Electronics Inc. | Driving circuit of plasma display panel |
| CN1311522A (en) * | 2000-02-29 | 2001-09-05 | 株式会社半导体能源研究所 | Displaying device and its mfg. method |
| CN1373504A (en) * | 2001-02-28 | 2002-10-09 | 株式会社半导体能源研究所 | Method for mfg. semiconductor device |
| CN1598950A (en) * | 1996-12-19 | 2005-03-23 | 松下电器产业株式会社 | Optical disk reproducing device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1598950A (en) * | 1996-12-19 | 2005-03-23 | 松下电器产业株式会社 | Optical disk reproducing device |
| US6239775B1 (en) * | 1997-06-14 | 2001-05-29 | Lg Electronics Inc. | Driving circuit of plasma display panel |
| CN1311522A (en) * | 2000-02-29 | 2001-09-05 | 株式会社半导体能源研究所 | Displaying device and its mfg. method |
| CN1373504A (en) * | 2001-02-28 | 2002-10-09 | 株式会社半导体能源研究所 | Method for mfg. semiconductor device |
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| CN101577102A (en) | 2009-11-11 |
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