CN101577086A - Automatic addressing method of series circuit and automatic detection method of series quantity - Google Patents

Abstract

An automatic addressing method for a series circuit and an automatic detection method for the number of series connections. The series circuit is formed by connecting a plurality of identical integrated circuits in series, and the automatic detection method is based on the automatic addressing method. The automatic addressing method includes the following steps: first, the integrated circuits are caused to sequentially transmit an initialization address command. Then, each time an integrated circuit receives the initialization address command, the address information corresponding to the integrated circuit is provided.

Description

Automatic addressing method of series circuit and automatic detection method of series connection quantity

technical field

The invention relates to an automatic addressing method and an automatic detection method, and in particular to an automatic addressing method for a series circuit and an automatic detection method for the serial connection quantity.

Background technique

In real life, many electronic devices operate with a large number of identical integrated circuits (ICs), such as LED (light emitting diode) display panels, image sensing arrays, etc. Taking an LED display panel as an example, in addition to having a large number of LEDs, it also uses a large number of driver chips to drive these LEDs, and uses a small number of control chips to control the operation of these driver chips.

In the above-mentioned electronic equipment, in order to reduce the component cost of these a large number of identical integrated circuits and obtain smaller component volumes, when designing such integrated circuits, the introduction of such integrated circuits is usually reduced as much as possible. foot count. In this way, in addition to effectively reducing the component volume and component cost of this type of integrated circuit, the control method of the control chip is relatively simple. However, due to the limited number of pins of this type of integrated circuit, this type of integrated circuit is operated in series in electronic equipment, and there is no corresponding address information, so many actions will be repeated, resulting in low efficiency . The driver chip in the LED display panel will be used as an illustration below.

FIG. 1 is a schematic diagram of the structure of an LED display panel. Please refer to FIG. 1 , the architecture includes a control chip 102 and four driver chips for driving LEDs, which are marked with 104 , 106 , 108 and 110 respectively. In addition, the label IN in the figure indicates the data input terminal of the chip, OUT indicates the data output terminal of the chip, CMO indicates the command output terminal of the chip, and CMI indicates the command receiving terminal of the chip. When it is necessary to update the display data, the data will be sent out from the data output terminal OUT of the control chip 102, and then transmitted sequentially according to the arrangement order of these driving chips, and when the data of each driving chip has been transmitted to the predetermined address, the control The chip 102 will issue a specific command to tell all the driver chips to display the data to be displayed. This data transmission form can not only be used to transmit display data, but also can be used to set various statuses in the status register inside the drive chip. Since the control chip 102 and the above-mentioned four driving chips are connected to form a ring structure, the control chip 102 can further read back the states of all the driving chips through the ring structure for applications such as error detection or system detection.

However, under such an architecture, since each driver chip has no corresponding address information, any command sent by the control chip 102 through the command output terminal CMO will be received by all the driver chips synchronously, so whether it is to update the display Data, or setting or reading the state of the driver chip, must reset all the driver chips. For example, even if only one of the above four driver chips needs to update the display data, but limited by such a structure, the control chip 102 still has to resend the display data of all the driver chips, thus making the data transfer Repeated operation of the action results in inefficiency.

Contents of the invention

The object of the present invention is to provide an automatic addressing method for series circuits, which can set addresses for multiple serially connected integrated circuits.

Another object of the present invention is to provide an automatic detection method for the number of serial connections, which can detect the number of multiple integrated circuits connected in series.

Based on the above and other objectives, the present invention proposes an automatic addressing method for a series circuit, and the series circuit is composed of a plurality of identical integrated circuits connected in series. The method includes the following steps: firstly, make the above-mentioned integrated circuit deliver an initialization address command sequentially. Then, whenever an integrated circuit receives the initialization address command, it provides the corresponding address information of the integrated circuit.

Based on the above and other objectives, the present invention further proposes an automatic detection method for the number of serial connections, which is suitable for a series circuit, and the series circuit is composed of multiple identical integrated circuits connected in series. The method includes the following steps: firstly, make the above-mentioned integrated circuit deliver an initialization address command sequentially. Next, whenever an integrated circuit receives the above-mentioned initialization address command, the address information corresponding to the integrated circuit is provided, wherein the address information of the above-mentioned integrated circuit has a specific relationship. Then, when the last integrated circuit in the above-mentioned integrated circuits transmits the initialization address command, the number of integrated circuits is calculated according to the address information corresponding to the last integrated circuit and the above-mentioned specific relationship.

According to the automatic addressing method of the serial circuit described in an embodiment of the present invention and the automatic detection method of the serial number described in an embodiment, the above-mentioned initialization address command is provided by a control circuit.

According to the automatic addressing method for series circuits described in an embodiment of the present invention and the automatic detection method for the number of serial connections described in an embodiment, the first integrated circuit among the above-mentioned integrated circuits receives an initialization address command, and its The corresponding address information is also provided by the control circuit, and the address information corresponding to each subsequent integrated circuit is provided by the previous integrated circuit.

According to the automatic addressing method for series circuits described in an embodiment of the present invention and the automatic detection method for the number of serial connections described in an embodiment, the first integrated circuit among the above-mentioned integrated circuits is coupled to a predetermined potential, and according to This predetermined potential generates the above-mentioned initialization address command.

According to the automatic addressing method of the serial circuit described in an embodiment of the present invention and the automatic detection method of the number of serial connections described in an embodiment, when the first integrated circuit generates an initialization address command, it provides its own address information, and the address information corresponding to each subsequent integrated circuit is provided by the previous integrated circuit.

According to an automatic addressing method for series circuits and an automatic detection method for the number of serial connections according to an embodiment of the present invention, the address information corresponding to each integrated circuit is provided by a control circuit.

In the present invention, each integrated circuit in the series circuit transmits an initialization address command sequentially, and whenever an integrated circuit receives the initialization address command, it provides the address information corresponding to this integrated circuit, so these integrated circuits can be processed. addressing. In addition, if the address information provided to these integrated circuits has a specific relationship, when the last integrated circuit in the above-mentioned integrated circuits transmits an initialization address command, it can be based on the address information corresponding to the last integrated circuit and the above-mentioned specific relationship. relationship to count the number of integrated circuits. Once each integrated circuit has been addressed, the integrated circuit with a specific address can be designated for operation, so that many actions will not be repeated, and the operating efficiency is improved.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail together with accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of the structure of an LED display panel.

FIG. 2 shows the same ring architecture as the device shown in FIG. 1 .

FIG. 3 illustrates a ring architecture similar to the device shown in FIG. 2 .

FIG. 4 is a flowchart of an automatic addressing method for a series circuit according to an embodiment of the present invention.

FIG. 5 is a flowchart of a method for automatically detecting the number of serial connections according to an embodiment of the present invention.

FIG. 6 illustrates another ring architecture.

[Description of main component symbols]

102: Control chip

104, 106, 108, 110: driver chip

202: Control circuit

204, 206, 208, 210: integrated circuits

402, 404, 502, 504, 506: steps

CMI: command receiver

CMO: command output

GND: ground voltage

IN, IN1, IN2: data input terminals

OUT, OUT1, OUT2: data output terminals

VDD: supply voltage

Detailed ways

(first embodiment):

FIG. 2 shows the same ring architecture as the device shown in FIG. 1 . Please refer to FIG. 2 , the structure includes a control circuit 202 and four serially connected integrated circuits, which are respectively marked as 204 , 206 , 208 and 210 . In addition, the label IN in the figure represents the data input end of the circuit, OUT represents the data output end of the circuit, CMO represents the command output end of the circuit, and CMI represents the command receiving end of the circuit. In this architecture, the control circuit 202 and the four serially connected integrated circuits can be realized by using the control chip 102 and the driving chip shown in FIG. 1 respectively.

When the system power of the ring structure is turned on, all integrated circuits are in an unaddressed state. At this time, the control circuit 202 sends out the initialization address command and the address information f(1) of the integrated circuit 204 from its data output terminal OUT, and the integrated circuit 204 will present the initialization address state after receiving the initialization address command, and wait to receive address information, and after receiving the address information f(1), it is addressed as f(1) accordingly. Subsequently, the integrated circuit 204 will change the address information f(1) to f(2) as the address information of the integrated circuit 206, and transmit the initialization address command and address information f(2) through its data output terminal OUT to IC 206. After receiving the initialization address command, the integrated circuit 206 will assume the initialization address state, and wait to receive address information, and address f(2) accordingly after receiving the address information f(2).

Then, the integrated circuit 206 changes the address information f(2) to f(3) as the address information of the integrated circuit 208 , and transmits the initialization address command and the address information f(3) to the integrated circuit 208 . Then the operation, and so on, so all integrated circuits will be addressed. Therefore, the control circuit 202 can designate an integrated circuit with a specific address to perform operations, such as updating processing data, or performing operations such as status setting. Because the control circuit 202 will send the operation command and the specific address from its data output terminal OUT at the same time, the operation command and the specific address will be transmitted according to the sequence of the integrated circuits, and only the integrated circuits that match the specific address will send the operation command As valid, and according to the specified operation, as for other integrated circuits, it is only responsible for transmission.

In addition, since the integrated circuit 210 will transmit the initialization address command and address information f(5) to the control circuit 202, when the control circuit 202 receives the initialization address command, it can know that all integrated circuits have completed addressing, and Since the address information of each integrated circuit has a specific relationship, when the control circuit 202 receives the address information f(5), it can reversely deduce the address information of the integrated circuit 210, and then according to the address information of the integrated circuit 210 and the specific relationship relationship to calculate the number of integrated circuits connected in series.

(second embodiment):

Please refer to FIG. 2 again. When the system power of the ring structure is turned on, all integrated circuits are in an unaddressed state. At this time, the control circuit 202 sends an initialization address command through its data output terminal OUT, so that the integrated circuit 204 receives the initialization address command and assumes an initialization address state, and waits for receiving address information. Then, the control circuit 202 outputs the address information f(1) of the integrated circuit 204 to all integrated circuits from its command output terminal CMO. Since only the integrated circuit 204 is waiting to receive the address information, only the integrated circuit 204 will receive the address information f(1), and address it accordingly as f(1). Subsequently, the integrated circuit 204 transmits the initialization address command to the integrated circuit 206 through its data output terminal OUT, so that the integrated circuit 206 receives the initialization address command and assumes the initialization address state, and waits for receiving address information. At this time, the control circuit 202 outputs the address information f(2) of the integrated circuit 206 to all integrated circuits from its command output terminal CMO. Since only the integrated circuit 206 is waiting to receive the address information, only the integrated circuit 206 will receive the address information f(2) and address it accordingly as f(2).

Next, the integrated circuit 206 also transmits the initialization address command to the integrated circuit 208 through its data output terminal OUT, and then the control circuit 202 outputs the address information f(3) of the integrated circuit 208 from its command output terminal CMO to the integrated circuit 208. take over. Subsequent operations can be deduced by analogy, so all integrated circuits will be addressed, so the control circuit 202 can designate the integrated circuits with specific addresses to operate. In addition, when the integrated circuits 210 complete addressing, they will also transmit the initialization address command to the control circuit 202, so the control circuit 202 can know that all integrated circuits have completed addressing. Since the address information of each integrated circuit sent by the control circuit 202 has a specific relationship, the control circuit 202 can calculate the number of integrated circuits connected in series according to the address information of the integrated circuit 210 and the specific relationship.

(third embodiment):

FIG. 3 illustrates a ring architecture similar to the device shown in FIG. 2 . Please refer to FIG. 3 , this structure also includes a control circuit 202 and four serially connected integrated circuits, which are respectively marked as 204 , 206 , 208 and 210 . In addition, the labels IN, OUT, CMO and CMI in the figure also respectively represent the data input terminal of the circuit, the data output terminal of the circuit, the command output terminal of the circuit and the command receiving terminal of the circuit. Please refer to FIG. 2 and FIG. 3 at the same time. After comparison, it can be found that the data input terminal IN of the integrated circuit 204 in FIG. 3 is not coupled to the data output terminal OUT of the control circuit 202, but is connected to a predetermined potential, for example It is the power supply voltage VDD or the ground voltage GND.

When the system power of the ring structure is turned on, all integrated circuits are in an unaddressed state. At this time, the integrated circuit 204 will detect whether its data input terminal IN is fixedly coupled to the predetermined potential, and if it is determined to be yes, the integrated circuit 204 will generate an initialization address command and provide its own address information f(1), to address itself as f(1). Subsequently, the integrated circuit 204 will change the address information f(1) to f(2) as the address information of the integrated circuit 206, and transmit the initialization address command and address information f(2) through its data output terminal OUT to IC 206. After receiving the initialization address command, the integrated circuit 206 will assume the initialization address state, and wait to receive address information, and address f(2) accordingly after receiving the address information f(2). Then, the integrated circuit 206 changes the address information f(2) to f(3) as the address information of the integrated circuit 208 , and transmits the initialization address command and the address information f(3) to the integrated circuit 208 . Then the operation, and so on, so all integrated circuits will also be addressed.

In addition, since the integrated circuit 210 will transmit the initialization address command and address information f(5) to the control circuit 202, when the control circuit 202 receives the initialization address command, it can know that all integrated circuits have completed addressing, and Since the address information of each integrated circuit has a specific relationship, when the control circuit 202 receives the address information f(5), it can reversely deduce the address information of the integrated circuit 210, and then according to the address information of the integrated circuit 210 and the specific relationship relationship to calculate the number of integrated circuits connected in series.

(fourth embodiment):

Please refer to FIG. 3 again. When the system power of the ring structure is turned on, all integrated circuits are in an unaddressed state. At this time, the integrated circuit 204 will detect whether its data input terminal IN is fixedly coupled to a predetermined potential, and when the determination is yes, the integrated circuit 204 will generate an initialization address command, and thus present an initialization address state and wait for receiving address information . Then, the control circuit 202 outputs the address information f(1) of the integrated circuit 204 to all integrated circuits from its command output terminal CMO. Since only the integrated circuit 204 is waiting to receive the address information, only the integrated circuit 204 will receive the address information f(1), and address it accordingly as f(1). Subsequently, the integrated circuit 204 transmits the initialization address command to the integrated circuit 206 through its data output terminal OUT, so that the integrated circuit 206 receives the initialization address command and assumes the initialization address state, and waits for receiving address information. At this time, the control circuit 202 outputs the address information f(2) of the integrated circuit 206 to all integrated circuits from its command output terminal CMO. Since only the integrated circuit 206 is waiting to receive the address information, only the integrated circuit 206 will receive the address information f(2) and address it accordingly as f(2). Subsequent operations can be deduced by analogy, so all integrated circuits will be addressed, so the control circuit 202 can designate the integrated circuits with specific addresses to operate.

In addition, when the integrated circuits 210 complete addressing, they will also transmit the initialization address command to the control circuit 202, so the control circuit 202 can know that all integrated circuits have completed addressing. Since the address information of each integrated circuit sent by the control circuit 202 has a specific relationship, the control circuit 202 can calculate the number of integrated circuits connected in series according to the address information of the integrated circuit 210 and the specific relationship.

According to the operations described in the above embodiments, an automatic addressing method for a series circuit can be summarized, which is suitable for a series circuit formed by connecting multiple identical integrated circuits in series, as shown in FIG. 4 . FIG. 4 is a flowchart of an automatic addressing method for a series circuit according to an embodiment of the present invention. Please refer to FIG. 4 , in this method, firstly, these integrated circuits transmit an initialization address command sequentially (as shown in step 402 ). Next, whenever an integrated circuit receives an initialization address command, address information corresponding to the integrated circuit is provided (as described in step 404 ).

In addition, according to the operations described in the above-mentioned embodiments, an automatic detection method for the number of series connections can also be summarized, which is also applicable to a series circuit formed by series connection of multiple identical integrated circuits, as shown in Figure 5 Show. FIG. 5 is a flowchart of a method for automatically detecting the number of serial connections according to an embodiment of the present invention. Please refer to FIG. 5 , in this method, firstly, these integrated circuits transmit an initialization address command sequentially (as shown in step 502 ). Next, whenever an integrated circuit receives the above initialization address command, the corresponding address information of the integrated circuit is provided, wherein the address information of these integrated circuits has a specific relationship (as shown in step 504 ). Then, when the last integrated circuit in these integrated circuits transmits the initialization address command, the number of these integrated circuits is calculated according to the address information corresponding to the last integrated circuit and the above-mentioned specific relationship (as shown in step 506 ).

Although in the devices shown in the above-mentioned embodiments, the connection relationship between the components can only provide data transmission in the form of a single bit string, those skilled in the art should know that even if the bus width (bus width) between the components is changed, , can also implement the present invention. For example, the user can change the data bus width of the device shown in FIG. 2 to make it another ring structure as shown in FIG. 6 . Please refer to Figure 2 and Figure 6 at the same time. After comparison, it can be found that each component in Figure 6 has two data input terminals (shown as IN1 and IN2) and two data output terminals (shown as OUT1 and OUT2) , so that each component can receive data of two bit strings at the same time, or output data of two bit strings at the same time. In addition, although only four integrated circuits are used as an example in the devices shown in the above embodiments, the present invention can still be implemented even if the number of serially connected integrated circuits is changed.

In summary, the present invention enables each integrated circuit in the series circuit to transmit an initialization address command sequentially, and whenever an integrated circuit receives the initialization address command, it provides the address information corresponding to this integrated circuit, so it can These integrated circuits are addressed. In addition, if the address information provided to these integrated circuits has a specific relationship, when the last integrated circuit in the above-mentioned integrated circuits transmits an initialization address command, it can be based on the address information corresponding to the last integrated circuit and the above-mentioned specific relationship. relationship to count the number of integrated circuits. Once each integrated circuit has been addressed, the integrated circuit with a specific address can be designated for operation, so that many actions will not be repeated, and the operating efficiency is improved. Furthermore, through the automatic addressing technology described in the present invention, in the series circuit, the use and maintenance of each integrated circuit will be more flexible.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (12)

1. the automatic addressing method of a series circuit, wherein this series circuit is formed by a plurality of identical integrated circuit serial connections, and this method comprises:

Make these integrated circuit transmit an initialization address order in regular turn; And

When an integrated circuit receives this initialization address order, provide this integrated circuit corresponding address information.

2. the automatic addressing method of series circuit as claimed in claim 1, wherein this initialization address order is provided by a control circuit.

3. the automatic addressing method of series circuit as claimed in claim 2, wherein first integrated circuit in these integrated circuit is except receiving this initialization address order, its corresponding address information is also provided by this control circuit, and each integrated circuit corresponding address information is thereafter provided by previous integrated circuit.

4. the automatic addressing method of series circuit as claimed in claim 1, wherein first integrated circuit in these integrated circuit is coupled to a predetermined potential, and produces this initialization address order according to this predetermined potential.

5. the automatic addressing method of series circuit as claimed in claim 4, wherein when described first integrated circuit produces this initialization address order, provide the address information of itself voluntarily, and each integrated circuit corresponding address information is thereafter provided by previous integrated circuit.

6. the automatic addressing method of series circuit as claimed in claim 1, wherein each integrated circuit corresponding address information is provided by a control circuit.

7. the automatic testing method of a series quantity is applicable to a series connection circuit, and this series circuit is formed by a plurality of identical integrated circuit serial connections, and this method comprises:

Make these integrated circuit transmit an initialization address order in regular turn;

When an integrated circuit receives this initialization address order, this integrated circuit corresponding address information just is provided, wherein the address information of these integrated circuit has a particular kind of relationship; And

When last integrated circuit in these integrated circuit passes out the initialization address order, just calculate the quantity of these integrated circuit according to above-mentioned last integrated circuit corresponding address information and this particular kind of relationship.

8. the automatic testing method of series quantity as claimed in claim 7, wherein this initialization address order is provided by a control circuit.

9. the automatic testing method of series quantity as claimed in claim 8, wherein first integrated circuit in these integrated circuit is except receiving this initialization address order, its corresponding address information is also provided by this control circuit, and each integrated circuit corresponding address information is thereafter provided by previous integrated circuit.

10. the automatic testing method of series quantity as claimed in claim 7, wherein first integrated circuit in these integrated circuit is coupled to a predetermined potential, and produces this initialization address order according to this predetermined potential.

11. the automatic testing method of series quantity as claimed in claim 10, wherein when described first integrated circuit produces this initialization address order, provide the address information of itself voluntarily, and each integrated circuit corresponding address information is thereafter provided by previous integrated circuit.

12. the automatic testing method of series quantity as claimed in claim 7, wherein each integrated circuit corresponding address information is provided by a control circuit.

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