CN101571836A - Method and system for replacing cache blocks - Google Patents
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Abstract
The invention discloses a method and a system for replacing cache blocks sharing a buffer. In the method, firstly, color marks are used for recording which programs of processors the cache blocks respectively belong to; then, the number of the cache blocks occupied by the programs on each processor, the priority of the program on each processor and the system resource consumed by the program on each processor are recorded; and finally, when cache block replacement is needed, the cache block for replacement is selected according to part or all information of the number of the cache blocks occupied by the program on each processor, the priority of the program on each processor and the system resource consumed by the program on each processor. According to the method and the system, at the time of cache block replacement, the fairness of different programs can be ensured.
Description
Technical field
The present invention relates to areas of information technology, more specifically, the present invention relates to be used to replace the method and system of cache blocks.
Background technology
Current, in the computer system of standard, buffer (cache) is a kind of common assembly, and wherein, a buffer comprises a plurality of cache blocks (cache line).After buffer has been expired, need carry out the replacement of cache blocks.At present, most popular replacement algorithm is LRU (least recently used) algorithm.Yet, in the last few years, some new technology (for example transaction internal memory (transactional memory) technology) had appearred, and for these new technology, lru algorithm is also improper, as below describing in detail.
Here the transaction internal memory technology is carried out some introductions.
Transaction internal memory allows application program with parallel but the mode of atom visits shared data.Transaction internal memory can improve performance of parallel program.Can be with reference to by Maurice Herlihy, the realization of transaction internal memory and relevant some terms or notion understood in the article that J.Eliot B.Moss delivered in 1993 " Transactional Memory:Architectural Support for Lock-Free Data Structures " (document 1).
Usually, transaction internal memory adopts hardware component to write down the intermediateness data that affairs are carried out, and comprises the memory address of affairs read data, the memory address of transaction write data and the data that will write etc.
More specifically, before the data with affairs are written to internal memory, earlier these data and memory address thereof temporarily are written to a buffer, in order to collision detection (conflictdetection).When two affairs will be visited identical memory address, and when having at least affairs will revise data in this address, conflict has just taken place.One of them affairs must be abandoned (abort), and is re-executing in the future.Wherein abandon meaning the History Log of these affairs of deletion in buffer.
If still no conflict occurred when affairs finished, then the data that temporarily are stored in relevant these affairs in the buffer are written in the memory system.This action is called submission (commit).
In practice, be difficult to the buffer that each affairs is distributed a special use, therefore be necessary to allow a plurality of affairs share a buffer.
Under these circumstances, belong to which affairs in order to distinguish the data that each cache blocks is stored in the buffer, each cache blocks in the buffer has a corresponding color indicia.This color indicia has write down affairs ID.That is to say which transaction write is this color indicia indicated this cache blocks.
When this buffer has been expired, but when processor also needs to write data in this buffer, cache blocks will take place replace.A kind of algorithm must be arranged, find out the cache blocks that will be replaced.It is lru algorithm that traditional cache blocks is replaced algorithm.The principle of lru algorithm is to select least-recently-used cache blocks to be used for replacing.Yet, under the situation of transaction internal memory, just can not use lru algorithm, the reasons are as follows.
According to the transaction internal memory technology, in case a cache blocks is replaced, the affairs under this cache blocks must be abandoned.More specifically, the cache blocks of selecting to be used to replace is actually the affairs that selection will be abandoned.Therefore, can not be only determine the affairs that to be abandoned with the access frequency of a cache blocks.
Be the fairness that protection is replaced, the influence of these factors below needing to consider:
1) whether affairs are active.In some system, allow affairs the term of execution be suspended, allow processor go to carry out other affairs, return to continue to carry out interrupted affairs after a while again.The affairs that are suspended are called inactive affairs.Their intermediateness data tend to take buffer for a long time, therefore need preferentially replace them.
2) priority of affairs.Obviously the low affairs of priority should be replaced earlier.The priority of affairs has a lot of sources, such as the priority from affiliated thread.
3) system resource that takies of affairs.For active affairs, take that resource is few more to mean that the time of having carried out is short more, therefore can preferentially replace.
Summary of the invention
According to an aspect of the present invention, proposed a kind of method of replacing at the cache blocks of shared buffer memory device, described method comprises step: by color indicia, write down each cache blocks and belong to program on which processor respectively; Number, the priority of the program on each processor and the system resource that program consumed on each processor of the cache blocks that the program on each processor of writing down is shared; And when needs carry out the cache blocks replacement, according to the number of the shared cache blocks of the program on each processor of above-mentioned record, the priority of program on each processor and the some or all of information in the system resource that program consumed on each processor, select the cache blocks that is used to replace.
According to another aspect of the present invention, proposed a kind of system that replaces at the cache blocks of shared buffer memory device, described system comprises: be used for by color indicia, write down the device that each cache blocks belongs to the program on which processor respectively; Be used to write down number, the priority of the program on each processor and the device of the system resource that program consumed on each processor of the shared cache blocks of program on each processor; And be used for when needs carry out the cache blocks replacement, according to the number of the shared cache blocks of the program on each processor of above-mentioned record, the priority of program on each processor and the some or all of information in the system resource that program consumed on each processor, select the device of the cache blocks that is used to replace.
According to the present invention, when replacing cache blocks, can guarantee the fairness between the distinct program.
Description of drawings
By below in conjunction with the description of the drawings, and along with understanding more comprehensively to of the present invention, other purposes of the present invention and effect will become clear more and easy to understand, wherein:
Fig. 1 schematically shows the environment 100 that can realize the embodiment of the invention therein;
Fig. 2 schematically shows the example of a buffer;
Fig. 3 schematically shows the operating position of the cache blocks of buffer;
Fig. 4 schematically shows the circuit structure diagram according to realization color indicia of an embodiment of the invention and color statistics;
Fig. 5 shows the process flow diagram of method that is used to replace cache blocks according to an embodiment of the invention.
Fig. 6 shows the system that replaces according to the cache blocks at the shared buffer memory device of one embodiment of the present invention.
In all above-mentioned accompanying drawings, identical label represents to have identical, similar or corresponding feature or function.
Embodiment
The present invention is applicable to the transaction internal memory technical field, below explanation will be example with the running environment of transaction internal memory, that is: the program of moving on the processor comprises some affairs, affairs use the shared buffer memory device to store the intermediateness data, cache blocks is replaced and is occurred in the affairs operational process, the identification number of color indicia indication affairs.Certainly, it should be appreciated by those skilled in the art, the invention is not restricted to this, but affairs can be abstracted into more generally notion program, because affairs are parts of program.
Fig. 1 schematically shows the environment 100 that the present invention can realize therein, and this environment is supported the transaction internal memory technology.
As shown in Figure 1, described environment 100 comprises software section 200, hardware components 300 and operating system 400.
Wherein, hardware components 300 comprises some processors 310,320,330 and 340, some buffers 350,360,370 and 380, and the network 390 of connection processing device and buffer.
In other words, in hardware components shown in Figure 1 300, buffer 350,360,370 and 380 is shared by processor 310,320,330 and 340, processor 310,320,330 and 340 any one in can access cache device 350,360,370 and 380.
Certainly, it will be understood by those of skill in the art that buffer 350,360,370 also can be connected by bus with 340 with processor 310,320,330 with 380, even can connect by direct link.
Those skilled in the art should be appreciated that also it is 4 shown in the figure that the number of buffer and processor is not necessarily leaveed no choice but, and can be other value.
In yet another embodiment of the present invention, the relation of buffer and processor is fixed.For example, buffer 350 is fixed to and can only be used by processor 310 and 320; Buffer 360 is fixed to and can only be used by processor 320 and 330; Buffer 370 is fixed to and can only be used by processor 330 and 340; And buffer 380 is fixed to and can only be used by processor 310 and 340.
Software section 200 comprises thread 210,220,230,240,250,260,270,280, each thread can comprise a plurality of affairs, for example as shown in the figure, thread 210 comprise affairs 2101,2102,2103 ..., thread 280 comprises affairs 2801,2802,2803.
Thread 210,220,230,240,250,260,270,280 can belong to same process, also can belong to different processes.
In environment 100, the execution of thread 210,220,230,240,250,260,270,280 walks abreast, and the execution of a plurality of affairs in each thread is serials.
Certainly, it is 8 shown in the figure that the number that it will be understood by those of skill in the art that thread is not necessarily leaveed no choice but, and can be other value.And it is 3 shown in the figure that the number of the affairs in each thread is also not necessarily leaveed no choice but, and can be other value.
An embodiment according to this present invention, buffer 350,360,370 and 380 can be used for the intermediateness data of each affairs in the record thread 210,220,230,240,250,260,270,280, comprises the memory address of affairs read data, the memory address of transaction write data and the data that will write.
Fig. 2 schematically shows the example of a buffer 20.This buffer 20 for example is a buffer 350,360,370 or 380.
This buffer 20 is one 4 road set associative buffers.Wherein, group comprises 4 cache blocks (each cache blocks belong to respectively in 4 tunnel some), and this buffer 20 comprises 128 groups altogether.
Can be addressed to a group by index 21.Selector switch 23 is selected 1 cache blocks according to label 22 from selected group.
For a person skilled in the art, be appreciated that how 4 road set associative buffers work, how promptly can understand to 4 road set associative buffers and write data and from 4 road set associative buffer sense datas.Therefore purpose is not for simplicity just carried out too much description here to this.Should be appreciated that simultaneously real system can use the set associative buffer of any way and group number, even the buffer that uses complete association or directly shine upon, the present invention does not also mind which type of buffer of use.
Fig. 3 schematically shows the operating position of the partial buffering piece of the buffer 20 among Fig. 2.
Wherein for example, when the color indicia of certain cache blocks equals 1 (" color=1 "), illustrate that this cache blocks distributed to first affairs; Similarly, " color=2 " show that corresponding cache blocks distributed to second affairs; And illustrate that when also not having color indicia this cache blocks also do not distribute to any affairs.
Fig. 4 schematically shows the circuit structure diagram according to realization color indicia of an embodiment of the invention and color statistics.
As shown in Figure 4, this circuit 40 comprises and searches element arrays 42, counter array 44 and address decoder part 46.Wherein search element arrays 42 comprise N search element 42-1,42-2 ..., 42-N, wherein N equals the number of cache blocks.That is to say that each cache blocks has one and searches element.Each searches element can to come addressing with the address of cache blocks.Search element 42-1,42-2 ..., among the 42-N each comprises color indicia register, significant notation register and a comparer.For example, search element 42-1 and comprise color indicia register 421-1, significant notation register 422-1 and comparer 423-1, search element 42-2 and comprise color indicia register 421-2, significant notation register 422-2 and comparer 423-2, ..., search element 42-N and comprise color indicia register 421-N, significant notation register 422-N and comparer 423-N.
Wherein, color indicia register 421-1,421-2 ..., the 421-N color indicia that is used to store corresponding cache blocks.According to one embodiment of the invention, each color indicia register can be stored 3 bits, that is to say, can support 2 altogether
3=8 kinds of colors.In other words, every cache blocks can have a kind of color in 8 kinds of colors, and correspondingly, this shared buffer memory device can be supported 8 affairs simultaneously.
Significant notation register 422-1,422-2 ..., 422-N is used to store the significant notation of corresponding color indicia.That is, significant notation register 422-1 is used to store the significant notation of the color indicia of color indicia register 421-1; Significant notation register 422-2 is used to store the significant notation of the color indicia of color indicia register 421-2; Significant notation register 422-N is used to store the significant notation of the color indicia of color indicia register 421-N.
For example, be designated as at 1 o'clock, illustrate that the color indicia in the corresponding color indicia register is effective as criterion.Be designated as at 0 o'clock as criterion, illustrate that the color indicia in the corresponding color indicia register is invalid.In other words, be designated as at 1 o'clock, illustrate that corresponding cache blocks is used as criterion.Be designated as at 0 o'clock as criterion, illustrate that corresponding cache blocks is not used, though perhaps be used, idle again now.
Comparer 423-1,423-2 ..., have description below the acting on of 423-N.
The address of the cache blocks that address signal line 401 indicates to visit, the address of searching element that promptly will visit.
The reading signal lines 402 effectively current operation of expression is read operation.Read operation is read by the color indicia register of the data appointment in the address signal line 401 and the content in the significant notation register, and from output signal line 408 output content corresponding.
The write signal line 403 effectively current operation of expression is a write operation.
The data that write in the line value signal 404 are data (color indicia) of write operation.
Write operation writes content corresponding in by the color indicia register of the data appointment in the address signal line 401 and significant notation register.
Write operation will cause the corresponding color counter in the counter array 44 to increase by 1.
In illustrated embodiment of the present invention, counter array 44 comprise 8 color counter 44-1,44-2 ..., 44-8.When a color is written in the color indicia register, just increase by 1 with the value of the corresponding color counter of this color.
Invalid signals line 405 is effective, illustrates that current what carry out is invalid operation.Invalid operation deactivates this cache blocks by the significant notation in the significant notation register of corresponding cache blocks being deactivated (for example, significant notation is set to zero), that is to say, selects this cache blocks to be used for replacing.Wherein, unlike the flush operation, invalid operation does not write back to the data in the cache blocks in the internal memory.
Invalid operation has two kinds of patterns:
1) a given address deactivates this address corresponding cache piece.What at this moment, transmit on the address signal line 401 is exactly this address.
2) a given color deactivates the cache blocks that all have this color.This operation is called invalid specific color cache blocks operation.What at this moment, transmit on the chrominance signal line 406 is exactly this color.At this moment, comparer 423-1,423-2 ..., 423-N compares the data on the chrominance signal line 406 with the color indicia in the corresponding color indicia register.If hit, then with the significant notation zero setting in the corresponding significant notation register.Simultaneously, this invalid operation will cause the corresponding color counter in the counter array 44 to put 0.
Statistics reading signal lines 407 represents that effectively current operation is the value in the corresponding color counter that reads in the counter array 44.At this moment, export by the value that color counter of chrominance signal line 406 indications from output signal line 408.
Sum up, in embodiments of the present invention, mainly contain the operation of following type:
1. read the significant notation of color indicia He this color indicia correspondence of a cache blocks.Address on the address signal line 401 is the address of this cache blocks at this moment.At this moment, from output signal line 408 output be this selection cache blocks search color indicia and significant notation the element.
2. write the significant notation of color indicia He this color indicia correspondence of a cache blocks.Address on the address signal line 401 is the address of this cache blocks at this moment.At this moment, the searching in the color indicia register in the element of cache blocks that value on the line value signal 404 is written to this selection will be write.Simultaneously, the significant notation of searching the significant notation register in the element of the cache blocks that will select of write operation is arranged to effectively.In addition, write operation makes that corresponding color counter increases by 1 in the counter array 44.
3. read total count value of certain color indicia.Readout in the corresponding color counter from counter array 44.
4. deactivate specific cache blocks, promptly deactivate the significant notation in the significant notation register of searching element of specific cache blocks.In embodiments of the present invention, invalid operation will deactivate the cache blocks that all have certain color.Significant notation in the corresponding significant notation register of invalid operation is set to invalid (for example putting 0).Simultaneously, this invalid operation will cause the corresponding color counter in the counter array 44 to put 0.
In embodiments of the present invention, address signal line 401, reading signal lines 402, write signal line 403, the data that write on line value signal 404, invalid signals line 405, chrominance signal line 406 and the statistics reading signal lines 407 come from operating system 400, and the signal of output signal line 408 outputs to operating system 400.
Fig. 5 shows the process flow diagram of method that is used to replace cache blocks according to an embodiment of the invention.
At first, at step S501,, write down each cache blocks and belong to which affairs respectively by color indicia.Described and how to have write down each cache blocks and belong to which affairs respectively with reference to figure 4.
Then, at step S503, write down the number of the cache blocks that each office has, and write down the system resource that each affairs takies.The number that how to write down the cache blocks that each office has has been described with reference to figure 4.
Described system resource comprises from one or more of following selection:
The number of the some or all of instruction that affairs have been carried out in a period of time,
The memory size that affairs take in a period of time,
Affairs in a period of time processor utilization and
Once or the state of the affairs of just on a processor, moving, for example sleep or active.
Can be by being hardware instruction counter of each affairs increase, write down the number of the some or all of instruction that each affairs carried out.Can add up the memory consumption situation and the processor utilization of affairs by in operating system, adding software counter.And the state of affairs and priority can directly obtain from operating system.Those skilled in the art needs to understand, and the method that obtains above-mentioned information is varied, and majority has been the general knowledge of this area.The present invention does not pay close attention to the above-mentioned information that how to obtain.Of the present invention is to utilize above-mentioned information to select the method for cache blocks.
Then,, carry out at needs under the situation of replacement of cache blocks,, need to select the cache blocks of replacing according to situation at step S505.The number of the cache blocks that definition office takies is N, and the number of instructions that affairs have been carried out is I, and priority is P, and consumes memory is M, and processor utilization is R, and state is S, utilizes following formula to calculate a numerical value that is used for comparison of each affairs
value＝α×N+β×I+γ×P+λ×M+ε×R+τ×S
α wherein, beta, gamma, λ, ε, τ is the nonnegative number smaller or equal to 1, and satisfies alpha+beta+γ+λ+ε+τ=1.α, beta, gamma, λ, ε, the concrete value of τ depends on different applied environment (below provided some examples).Select the method for cache blocks to comprise: a given threshold value, select described numerical value to be greater than or less than office's corresponding cache piece of this threshold value; Perhaps the described numerical value to each affairs sorts, and selects described numerical value maximum or minimum office's corresponding cache piece to replace.
Below illustrate.
Having only under the situation of enlivening affairs, selecting to take the maximum office's corresponding cache piece of cache blocks and be used for replacing.Summary be the reasons are as follows.Under the situation that allows affairs to switch, have only affairs to enliven at every turn.Because the affairs of switching away generally will wait the long time just can switch back, therefore, select to take the maximum office's corresponding cache piece of cache blocks and be used to replace proper.Correspond to above-mentioned formula, value α=1, β=0, γ=0, λ=0, ε=0, τ=0.Then to the described numerical ordering of each affairs, select office's corresponding cache piece of described numerical value maximum to replace and get final product.
Have at the same time under a plurality of situations of enlivening affairs, select to take the minimum office's corresponding cache piece of cache blocks and be used for replacing.Summary be the reasons are as follows.Under the situation that does not allow affairs to switch, have a plurality of affairs of enlivening simultaneously.At this moment, owing to take affairs and will finish soon, therefore, select to belong to and take the minimum office's corresponding cache piece of cache blocks and be used to replace proper with more number cache blocks.Correspond to above-mentioned formula, value α=1, β=0, γ=0, λ=0, ε=0, τ=0.Then to the described numerical ordering of each affairs, select office's corresponding cache piece of described numerical value minimum to replace and get final product.
At the computation-intensive affairs, office's corresponding cache piece of selecting to carry out minimum instruction is used for replacing.Because at the computation-intensive affairs, just can not be with shared cache blocks how much determine whether replacing certain affairs.Correspond to above-mentioned formula, value α=0, β=1, γ=0, λ=0, ε=0, τ=0.Then to the described numerical ordering of each affairs, select office's corresponding cache piece of described numerical value minimum to replace and get final product.
In an embodiment of the invention, at step S503, perhaps before step S505, also comprise step: the type that writes down each instruction of having carried out.
If wherein access memory instructs the ratio that accounts for all instructions of having carried out greater than a threshold value, these affairs are data-intensive affairs so, otherwise are exactly the computation-intensive affairs.
In an embodiment of the invention, the span of this threshold value is 20%-40%.
In an embodiment of the invention, at step S503, perhaps before step 505, also comprise step: the effective significant notation of record each cache blocks of expression.
In this embodiment, the significant notation that comprises those cache blocks of selecting that deactivate record at the step S505 that selects the cache blocks that is used for replacing.Can adopt above-described invalid specific color cache blocks to operate the significant notation of those cache blocks of selecting that deactivate record.
Fig. 6 shows the system that replaces according to the cache blocks at the shared buffer memory device of one embodiment of the present invention.
Described system 600 comprises: be used for by color indicia, write down the device 610 that each cache blocks belongs to the program on which processor respectively; Be used to write down number, the priority of the program on each processor and the device 620 of the system resource that program consumed on each processor of the shared cache blocks of program on each processor; And be used for when needs carry out the cache blocks replacement, according to the number of the shared cache blocks of the program on each processor of above-mentioned record, the priority of program on each processor and the some or all of information in the system resource that program consumed on each processor, select the device 630 of the cache blocks that is used to replace.
In an embodiment of the invention, this system 600 also comprises: be used to write down the device 640 of the effective significant notation of each cache blocks of expression, and the device 630 that is used to select the cache blocks that is used to replace comprises the device 6301 of the significant notation of those cache blocks of selecting that are used to deactivate record.
Wherein, described system resource comprises from one or more of following selection:
The number of the some or all of instruction that the program on the processor has been carried out in a period of time,
The memory size that program on the processor takies in a period of time,
Program on the processor in a period of time processor utilization and
Once or the state of the program of just on a processor, moving.
Wherein, the described time period is meant the working time of affairs, and described affairs are meant the affairs in the transaction internal memory technology.
Wherein, having only under the situation of enlivening affairs, selecting in the described buffer the highest cache blocks of colorfulness to replace, colorfulness is defined as in whole buffer the quantity of the cache blocks identical with cache blocks color.
Wherein, have at the same time under a plurality of situations of enlivening affairs, select the cache blocks that colorfulness is minimum in the described buffer to replace, colorfulness is defined as in whole buffer the quantity of the cache blocks identical with cache blocks color.
Wherein, under the situation of computation-intensive affairs, the cache blocks of selecting the minimum office of consume system resources to take is replaced.
In an embodiment of the invention, system 600 also comprises: the device 650 that is used to write down the type of each instruction of having carried out, if wherein the access memory instruction accounts for the ratio of all instructions of having carried out greater than a threshold value, these affairs are data-intensive affairs so, otherwise are exactly the computation-intensive affairs.
In an embodiment of the invention, the span of described threshold value is 20%～40%.
Should be noted that for the present invention is more readily understood top description has been omitted to be known for a person skilled in the art and may to be essential some ins and outs more specifically for realization of the present invention.
The purpose that instructions of the present invention is provided is in order to illustrate and to describe, rather than is used for exhaustive or limits the invention to disclosed form.For those of ordinary skill in the art, many modifications and changes all are conspicuous.Those skilled in the art be also to be understood that the mode that can pass through software, hardware, firmware or their combination, realize the method and apparatus in the embodiment of the invention.For example, the present invention can be implemented as a kind of computer program, comprises the program code that is stored on the computer-readable medium, and it carries out the method described in the embodiment of the invention when being carried out by computing machine.
Therefore; selecting and describing embodiment is in order to explain principle of the present invention and practical application thereof better; and those of ordinary skills are understood, under the prerequisite that does not break away from essence of the present invention, all modifications and change all fall within protection scope of the present invention defined by the claims.
Claims (17)
1. method of replacing at the cache blocks of shared buffer memory device, described method comprises step:
By color indicia, write down each cache blocks and belong to program on which processor respectively;
Number, the priority of the program on each processor and the system resource that program consumed on each processor of the cache blocks that the program on each processor of writing down is shared; And
When needs carry out the cache blocks replacement, according to the number of the shared cache blocks of the program on each processor of above-mentioned record, the priority of program on each processor and the some or all of information in the system resource that program consumed on each processor, select the cache blocks that is used to replace.
2. method according to claim 1 also comprises step:
The effective significant notation of record each cache blocks of expression, and
The step of selecting the cache blocks that is used to replace comprises the significant notation of those cache blocks of selecting that deactivate record.
3. method according to claim 1, wherein said system resource comprise from one or more of following selection:
The number of the some or all of instruction that the program on the processor has been carried out in a period of time,
The memory size that program on the processor takies in a period of time,
Program on the processor in a period of time processor utilization and
Once or the state of the program of just on a processor, moving.
4. method according to claim 3, the wherein said time period is meant the working time of affairs, described affairs are meant the affairs in the transaction internal memory technology.
5. method according to claim 4, wherein having only under the situation of enlivening affairs, select in the described buffer the highest cache blocks of colorfulness to replace, colorfulness is defined as in whole buffer the quantity of the cache blocks identical with cache blocks color.
6. method according to claim 4, wherein have at the same time under a plurality of situations of enlivening affairs, select the cache blocks that colorfulness is minimum in the described buffer to replace, colorfulness is defined as in whole buffer the quantity of the cache blocks identical with cache blocks color.
7. method according to claim 4, wherein under the situation of computation-intensive affairs, the cache blocks of selecting the minimum office of consume system resources to take is replaced.
8. method according to claim 7 also comprises step:
Write down the type of each instruction of having carried out,
If wherein access memory instructs the ratio that accounts for all instructions of having carried out greater than a threshold value, these affairs are data-intensive affairs so, otherwise are exactly the computation-intensive affairs.
9. method according to claim 8, the span of wherein said threshold value is 20%～40%.
10. system that replaces at the cache blocks of shared buffer memory device, described system comprises:
Be used for by color indicia, write down the device that each cache blocks belongs to the program on which processor respectively;
Be used to write down number, the priority of the program on each processor and the device of the system resource that program consumed on each processor of the shared cache blocks of program on each processor; And
Be used for when needs carry out the cache blocks replacement, according to the number of the shared cache blocks of the program on each processor of above-mentioned record, the priority of program on each processor and the some or all of information in the system resource that program consumed on each processor, select the device of the cache blocks that is used to replace.
11. system according to claim 10 also comprises:
Be used to write down the device of the effective significant notation of each cache blocks of expression, and
The device that is used to select the cache blocks that is used to replace comprises the device of the significant notation of those cache blocks of selecting that are used to deactivate record.
12 systems according to claim 10, wherein said system resource comprise from one or more of following selection:
The number of the some or all of instruction that the program on the processor has been carried out in a period of time,
The memory size that program on the processor takies in a period of time,
Program on the processor in a period of time processor utilization and
Once or the state of the program of just on a processor, moving.
13. system according to claim 12, the wherein said time period is meant the working time of affairs, and described affairs are meant the affairs in the transaction internal memory technology.
14. system according to claim 13, wherein having only under the situation of enlivening affairs, select in the described buffer the highest cache blocks of colorfulness to replace, colorfulness is defined as in whole buffer the quantity of the cache blocks identical with cache blocks color.
15. system according to claim 13, wherein have at the same time under a plurality of situations of enlivening affairs, select the cache blocks that colorfulness is minimum in the described buffer to replace, colorfulness is defined as in whole buffer the quantity of the cache blocks identical with cache blocks color.
16. system according to claim 13, wherein under the situation of computation-intensive affairs, the cache blocks of selecting the minimum office of consume system resources to take is replaced.
17. system according to claim 16 also comprises:
Be used to write down the device of the type of each instruction of having carried out,
If wherein access memory instructs the ratio that accounts for all instructions of having carried out greater than a threshold value, these affairs are data-intensive affairs so, otherwise are exactly the computation-intensive affairs.
18. system according to claim 17, the span of wherein said threshold value is 20%～40%.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100839478A CN101571836A (en) | 2008-04-29 | 2008-04-29 | Method and system for replacing cache blocks |
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| CN102486719A (en) * | 2010-12-06 | 2012-06-06 | 普天信息技术研究院有限公司 | Smart memory card and method for writing things thereof |
| CN103246566A (en) * | 2012-02-03 | 2013-08-14 | 腾讯科技（深圳）有限公司 | Resource monitoring method and device for application program |
| WO2015035928A1 (en) * | 2013-09-16 | 2015-03-19 | 华为技术有限公司 | Method and apparatus for dividing cache |
| CN104620231A (en) * | 2012-08-17 | 2015-05-13 | 华为技术有限公司 | Cache coherent handshake protocol for in-order and out-of-order networks |
| CN104731980A (en) * | 2015-04-17 | 2015-06-24 | 吉林大学 | Method and device for management of cache pages |
| CN104750561A (en) * | 2015-04-15 | 2015-07-01 | 苏州中晟宏芯信息科技有限公司 | Dynamic release method and system of register file cache resources and processor |
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| CN114138685A (en) * | 2021-12-06 | 2022-03-04 | 海光信息技术股份有限公司 | Cached resource allocation method and device, electronic device and storage medium |
| CN119271579A (en) * | 2024-12-05 | 2025-01-07 | 北京开源芯片研究院 | Cache replacement method, device, electronic device and medium based on reinforcement learning |
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| CN102486719B (en) * | 2010-12-06 | 2015-04-15 | 普天信息技术研究院有限公司 | Intelligent memory card and transaction-writing method thereof |
| CN102486719A (en) * | 2010-12-06 | 2012-06-06 | 普天信息技术研究院有限公司 | Smart memory card and method for writing things thereof |
| CN103246566B (en) * | 2012-02-03 | 2017-12-01 | 腾讯科技（深圳）有限公司 | The resource monitoring method and device of application program |
| CN103246566A (en) * | 2012-02-03 | 2013-08-14 | 腾讯科技（深圳）有限公司 | Resource monitoring method and device for application program |
| CN104620231A (en) * | 2012-08-17 | 2015-05-13 | 华为技术有限公司 | Cache coherent handshake protocol for in-order and out-of-order networks |
| CN104620231B (en) * | 2012-08-17 | 2017-08-25 | 华为技术有限公司 | The relevant Handshake Protocol of the caching of orderly and disordered networks |
| WO2015035928A1 (en) * | 2013-09-16 | 2015-03-19 | 华为技术有限公司 | Method and apparatus for dividing cache |
| CN104750561A (en) * | 2015-04-15 | 2015-07-01 | 苏州中晟宏芯信息科技有限公司 | Dynamic release method and system of register file cache resources and processor |
| CN104731980A (en) * | 2015-04-17 | 2015-06-24 | 吉林大学 | Method and device for management of cache pages |
| CN105740445A (en) * | 2016-02-02 | 2016-07-06 | 贵州大学 | A database query method and device |
| CN114138685A (en) * | 2021-12-06 | 2022-03-04 | 海光信息技术股份有限公司 | Cached resource allocation method and device, electronic device and storage medium |
| CN114138685B (en) * | 2021-12-06 | 2023-03-10 | 海光信息技术股份有限公司 | Cache resource allocation method and device, electronic device and storage medium |
| CN119271579A (en) * | 2024-12-05 | 2025-01-07 | 北京开源芯片研究院 | Cache replacement method, device, electronic device and medium based on reinforcement learning |
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