CN101571810B - Method for implementing program, method for verifying program result, devices and system - Google Patents

Abstract

The invention discloses a method for executing a program, a method for verifying a program result, a device and a system, and belongs to the field of computers. The method for executing a program includes: obtaining instruction information from a text file of a source program; establishing a serial queue according to the instruction information; constructing a parallel timing diagram according to the serial queue; executing in parallel according to the parallel timing diagram the source program. The device for executing the program includes: an acquisition module, an establishment module, a construction module and an execution module. The device for verifying program results includes: a creation module, a first setting module, a second setting module, a mapping module, a first judging module and a second judging module. A system for executing a program includes means for executing the program and means for verifying the results of the program. The invention can improve the efficiency of developing programs and facilitate scheduling and deployment of programs.

Description

Method for executing program, method, device and system for verifying program result

technical field

The invention relates to the computer field, in particular to a method for executing a program, a method, a device and a system for verifying the result of the program.

Background technique

PLC (Programmable Logic Controller, Programmable Logic Controller) adopts a cyclic scanning execution method. This method is divided into three phases: input sampling, user program execution and putting into operation. Completing the above three stages is called a scan cycle. Among them, the programs running on the PLC are serially executed in accordance with the execution mode of cyclic scanning.

Since the PLC hardware has a certain limit on the length of the scan cycle, when performing relatively complex control functions, the method of serially executing the program cannot execute the entire program in a single scan cycle, and the programmer must divide the original complete program into Multi-segment, the control function is completed by executing each segment of the program independently, or the program is written separately on multiple PLCs that communicate with each other, and each PLC executes its own program to cooperate to complete the control function.

In the process of realizing the present invention, the inventor finds that there are at least the following problems in the prior art:

In the existing method of serially executing programs, when performing relatively complex control functions, the complete program must be divided into multiple sections or written on multiple PLCs, which greatly affects the efficiency of programmers in developing programs, and brings great difficulties for debugging and Deployment procedures are inconvenient.

Contents of the invention

In order to improve the efficiency of program development and facilitate debugging and deployment of programs, the embodiments of the present invention provide a method for executing a program, a method, a device, and a system for verifying an execution result. Described technical scheme is as follows:

A method of executing a program, the method comprising:

Sequentially scan the instructions in the text file of the source program;

Read the name of the instruction, the operand of the instruction, the delimiter to which the instruction belongs, and the program block to which the instruction belongs;

calculating the execution time of said delimiter;

Obtain the storage space and read/write attributes of the operand;

The name of the instruction, the operand of the instruction, the delimiter and the program block to which the instruction belongs, the execution time of the delimiter, the storage space of the operand and the read-write attribute are used as the instruction information;

Create a serial queue;

From the main program block of the program block of the instruction information as an entry, sequentially scan the instructions included in the delimiter in the instruction information;

adding the delimiter as a node to the serial queue, wherein the execution time of the delimiter is used as the weight of the node;

Judging whether the instruction is to call a CALL instruction, if the instruction is a CALL instruction, then jump into the program block called by the CALL instruction, and scan the instructions included in the delimiter in the program block;

storing the nodes in the serial queue into a parallel sequence diagram;

In the serial queue, the pointer 1 is set to point to the team head node, and the pointer 2 is set to point to the next node of the node pointed to by the pointer 1;

According to the storage space and the read-write attribute of the operand, it is judged whether there is a data dependency relationship between the node pointed to by the pointer 1 and the node pointed to by the pointer 2, and if there is, in the parallel sequence diagram, the node pointed by the pointer 1 A directed edge is added between the node pointed to by the pointer 2 and the node pointed to by the pointer 2, and the direction is that the node pointed to by the pointer 1 points to the node pointed to by the pointer 2, and in the serial queue, the pointer 2 points to next node;

If it does not exist, in the serial queue, reset the pointer 2 to point to the next node;

Executing the source program in parallel according to the parallel sequence diagram;

Wherein, the source program is composed of one or more program blocks, the program block is composed of one or more delimiters, and the delimiter is composed of one or more instructions.

A device for executing a program, the device includes an acquisition module, an establishment module, a construction module and an execution module:

The acquisition module includes a first scanning unit, a reading unit, a calculation unit and a first acquisition unit;

The first scanning unit is used to sequentially scan the instructions in the text file of the source program;

The reading unit is configured to read the name of the instruction, the operand of the instruction, the delimiter to which the instruction belongs, and the program block to which the instruction belongs;

The calculation unit is used to calculate the execution time of the delimiter;

The first acquiring unit is configured to acquire the storage space and read/write attributes of the operand;

The name of the instruction, the operand of the instruction, the delimiter and the program block to which the instruction belongs, the execution time of the delimiter, the storage space of the operand and the read-write attribute are used as the instruction information;

The building module includes a building unit, a second scanning unit, an adding unit and a judging unit;

The establishment unit is used to establish a serial queue;

The second scanning unit is configured to sequentially scan the instructions included in the delimiter in the instruction information from the main program block of the instruction information program block as an entry;

The adding unit is configured to add the delimiter as a node to the serial queue, wherein the execution time of the delimiter is used as the weight of the node;

The judging unit is used to judge whether the instruction is a call CALL instruction, if the instruction is a CALL instruction, then jump into the program block called by the CALL instruction, and scan the instructions included in the delimiter in the program block ;

The construction module includes a storage unit, a first setting unit and a first judging unit;

The storage unit is used to store the nodes in the serial queue into a parallel sequence diagram;

The first setting unit is configured to set the pointer 1 to point to the queue head node in the serial queue, and set the pointer 2 to point to the node next to the node pointed to by the pointer 1;

The first judging unit is configured to judge whether there is a data dependency relationship between the node pointed to by the pointer 1 and the node pointed to by the pointer 2 according to the storage space and the read/write attribute of the operand, and if so, in the parallel sequence In the figure, a directed edge is added between the node pointed to by the pointer 1 and the node pointed to by the pointer 2, and the direction is that the node pointed to by the pointer 1 points to the node pointed to by the pointer 2, and in the serial queue , reset the pointer 2 to point to the next node; if it does not exist, reset the pointer 2 to point to the next node in the serial queue;

The execution module is configured to execute the source program in parallel according to the parallel sequence diagram.

A method of verifying program results, the method comprising:

Create a Petri net model based on the parallel sequence diagram;

Initial flag is set in the first storehouse node in described Petri net model;

Set the pointer to point to the first node in the program execution sequence;

Mapping the node pointed by the pointer to the corresponding transition node in the Petri net model;

Judging whether the initial flag exists in the front library node of the transition node, if not, returning the error message of the program result;

If yes, move the initial flag into the back library node of the transition node, judge whether there are other nodes in the program execution sequence, if yes, set the pointer to point to the next node, if not, return the program result is correct Information.

An apparatus for verifying program results, the apparatus comprising:

Create a module for creating a Petri net model based on a parallel sequence diagram;

The first setting module is used to set the initial sign in the first library node in the Petri net model;

The second setting module is used to set the pointer to point to the first node of the program execution sequence;

A mapping module, configured to map the node pointed to by the pointer to the corresponding transition node in the Petri net model;

The first judging module is used to judge whether the initial flag exists in the front library node of the transition node, and if not, return the information that the program result is wrong;

The second judging module is used to move the initial flag into the back library node of the transition node when the judging result of the first judging module is yes, and judge whether there are other nodes in the program execution sequence, if yes , set the pointer to point to the next node, if not, return the information that the program result is correct.

A system for executing a program, the system comprising means for executing the program and means for verifying the results of the program:

The device for executing the program includes an acquisition module, an establishment module, a construction module and an execution module;

The acquisition module includes a first scanning unit, a reading unit, a calculation unit and a first acquisition unit;

The first scanning unit is used to sequentially scan the instructions in the text file of the source program;

The reading unit is configured to read the name of the instruction, the operand of the instruction, the delimiter to which the instruction belongs, and the program block to which the instruction belongs;

The calculation unit is used to calculate the execution time of the delimiter;

The first acquiring unit is configured to acquire the storage space and read/write attributes of the operand;

The name of the instruction, the operand of the instruction, the delimiter and the program block to which the instruction belongs, the execution time of the delimiter, the storage space of the operand and the read-write attribute are used as the instruction information;

The building module includes a building unit, a second scanning unit, an adding unit and a judging unit;

The establishment unit is used to establish a serial queue;

The second scanning unit is configured to sequentially scan the instructions included in the delimiter in the instruction information from the main program block of the instruction information program block as an entry;

The adding unit is configured to add the delimiter as a node to the serial queue, wherein the execution time of the delimiter is used as the weight of the node;

The judging unit is used to judge whether the instruction is a call CALL instruction, if the instruction is a CALL instruction, then jump into the program block called by the CALL instruction, and scan the instructions included in the delimiter in the program block ;

The construction module includes a storage unit, a first setting unit and a first judging unit;

The storage unit is used to store the nodes in the serial queue into a parallel sequence diagram;

The first setting unit is configured to set the pointer 1 to point to the queue head node in the serial queue, and set the pointer 2 to point to the node next to the node pointed to by the pointer 1;

The first judging unit is configured to judge whether there is a data dependency relationship between the node pointed to by the pointer 1 and the node pointed to by the pointer 2 according to the storage space and the read/write attribute of the operand, and if so, in the parallel sequence In the figure, a directed edge is added between the node pointed to by the pointer 1 and the node pointed to by the pointer 2, and the direction is that the node pointed to by the pointer 1 points to the node pointed to by the pointer 2, and in the serial queue , reset the pointer 2 to point to the next node; if it does not exist, reset the pointer 2 to point to the next node in the serial queue;

The execution module is configured to execute the source program in parallel according to the parallel sequence diagram;

Wherein, the source program is composed of one or more program blocks, the program block is composed of one or more delimiters, and the delimiter is composed of one or more instructions;

The device for verifying program results includes a creation module, a first setting module, a second setting module, a mapping module, a first judging module and a second judging module;

The creation module is used to create a Petri net model according to the parallel sequence diagram;

The first setting module is used to set an initial flag in the first library node in the Petri net model;

The second setting module is used to set the pointer to point to the first node of the program execution sequence;

The mapping module is configured to map the node pointed by the pointer to the corresponding transition node in the Petri net model;

The first judging module is used to judge whether the initial flag exists in the front library node of the transition node, and if not, return the error message of the program result;

The second judging module is configured to move the initial flag into the back library node of the transition node when the judging result of the first judging module is yes, and judge whether there are other nodes in the program execution sequence, If yes, set the pointer to point to the next node, if no, return information that the program result is correct.

By obtaining instruction information from the text file of the source program, a serial queue is established according to the instruction information, a parallel sequence diagram is constructed according to the serial queue, and the source program is executed in parallel according to the parallel sequence diagram, so that the entire program can be executed in one scan cycle. For the source program, it is not necessary to divide the source program into multiple segments and execute it separately, or write the source program on different PLCs and each PLC executes it independently, which improves the efficiency of developing the source program and facilitates debugging and deployment of the source program.

Description of drawings

FIG. 1 is a flowchart of a method for executing a program provided in Embodiment 1 of the present invention;

FIG. 2 is a flow chart of a method for executing a program provided by Embodiment 2 of the present invention;

Fig. 3 is a schematic diagram of a serial queue provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a first parallel timing diagram provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of a second parallel timing diagram provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram of a third parallel timing diagram provided by an embodiment of the present invention;

Fig. 7 is a schematic diagram of connected components provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of a new parallel sequence diagram provided by an embodiment of the present invention;

FIG. 9 is a flow chart of a method for verifying program results provided by Embodiment 3 of the present invention;

FIG. 10 is a schematic diagram of a fourth parallel timing diagram provided by an embodiment of the present invention;

Fig. 11 is a schematic diagram of a Petri net model provided by an embodiment of the present invention;

Fig. 12 is a schematic diagram of a simplified Petri net model provided by an embodiment of the present invention;

Fig. 13 is a schematic diagram of a device for executing a program provided by Embodiment 4 of the present invention;

FIG. 14 is a schematic diagram of a device for verifying program results provided by Embodiment 5 of the present invention;

Fig. 15 is a schematic diagram of a system for executing a program provided by Embodiment 6 of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Example 1

As shown in Figure 1, an embodiment of the present invention provides a method for executing a program, including:

101: Obtain instruction information from the text file of the source program;

Wherein, for the detailed process of obtaining instruction information from the text file of the source program, refer to 201 of Embodiment 2, which will not be repeated here.

102: Establish a serial queue according to the instruction information;

Wherein, for the detailed process of establishing the serial queue according to the instruction information, refer to 202 of Embodiment 2, which will not be repeated here.

103: Construct a parallel sequence diagram according to the serial queue;

Wherein, for the detailed process of constructing the parallel sequence diagram according to the serial queue, refer to 203 of Embodiment 2, which will not be repeated here.

104: Execute the source program in parallel according to the parallel sequence diagram;

Wherein, according to the parallel sequence diagram, refer to 205 of Embodiment 2 for the detailed process of executing the source program in parallel, which will not be repeated here.

Wherein, in this embodiment, according to the parallel sequence diagram, the source program is executed in parallel, so that the entire source program can be executed within one scan cycle.

In the embodiment of the present invention, by obtaining instruction information from the text file of the source program, a serial queue is established according to the instruction information, a parallel sequence diagram is constructed according to the serial queue, and the source program is executed in parallel according to the parallel sequence diagram, so that in a The entire source program can be executed within the scan cycle, without the need to divide the source program into multiple segments for separate execution, or write the source program on different PLCs and execute each PLC independently, which improves the efficiency of source program development and facilitates debugging and deployment of source programs .

Example 2

As shown in Figure 2, an embodiment of the present invention provides a method for executing a program, including:

201: Scan the text file of the source program to obtain instruction information;

Wherein, the source program is composed of one or more program blocks, the program block is composed of one or more Networks (delimiters), and the Network is composed of one or more instructions.

Specifically, sequentially scan each line of instructions in the text file of the source program, read the program block to which the instruction belongs, the Network to which the instruction belongs, the line number of the instruction in the Network to which the instruction belongs, the name of the instruction, and the operand of the instruction; obtain the storage of the operand Space, analyze the read and write properties of the operand; estimate the execution time of the instruction, sum the execution time of the instructions included in the Network, and obtain the execution time of the Network, the program block, the Network to which it belongs, the line number of the instruction, and the instruction The name, the operand of the instruction, the execution time, the storage space of the operand and the read/write attribute of the operand are used as the instruction information, and the instruction information is stored.

Wherein, the method for obtaining the storage space of the operand in this embodiment is specifically: reading the storage type of the operand, and searching for the storage type from the mapping relationship between the storage type and the starting base address according to the storage type of the operand The starting base address of the occupied storage area, calculate the upper bound offset and lower bound offset of the operand in the storage area according to the name of the operand, and calculate the starting base address and the calculated upper bound offset The sum of the shift amount and the lower bound offset is obtained to obtain the upper bound address and lower bound address of the storage space where the operand is located.

Wherein, in this embodiment, a starting base address is artificially assigned to the storage area occupied by the storage type, and the principle of allocation of the starting base address is to ensure that the storage areas occupied by each storage type cannot overlap. Table 1 shows the mapping relationship between the storage type and the starting base address.

Next, use specific examples to illustrate how to obtain the storage space of the operand. For example, for the operand SM2, read the storage type of the operand as SM, and look up the starting base address of the storage area where the SM is located from Table 1 according to the storage type SM. It is 2000, where it needs to be explained that: the 2 in the operand SM2 means that the operand occupies the third byte of the storage area where the SM is located, and the upper bound offset of the operand in the storage area where the SM is located is calculated according to the above description The amount is 15 and the lower bound offset is 23, and the starting base address 2000 of the search and the calculated upper bound offset 15 and lower bound offset 23 are respectively summed to obtain the upper bound address of the storage space where the operand is located is 2015 And the lower bound address is 2023. In addition, it should be noted that: the meaning of 2.2 in the operand SM2.2 is that the operand occupies the third bit of the third byte of the storage area where the SM is located, so its upper bound offset and lower bound offset are both is 18, the starting base address is summed with the upper bound offset and the lower bound offset respectively, and the upper bound address and the lower bound address of the storage space where SM2.2 is located are both 2018.

In addition, it should be noted that since the CALL instruction carries the called program block, when obtaining the instruction information of the CALL instruction, the called program block is also used as the operand of the CALL instruction, but the operand does not have the occupied storage space and read Write attributes, for example, CALL SBR1 (program block), use the program block name SBR1 as the operand of the CALL instruction.

Table 1

storage type Starting base address I 0 Q 200 AI 400 ... ... SM 2000 ... ...

Next, a specific implementation will be used to describe the source program shown below. Scan the source program to obtain instruction information:

Scan this section of source program sequentially, the first scanned instruction is the name part of this section of source program, until the fifth line of instruction LD SM0.0 is scanned, read the program block OB1 to which this instruction belongs, the Network to which it belongs, namely Network 1, The line number 1 of the instruction in Network 1, the operand SM0.0 of the instruction; the estimated execution time of the instruction is 0.8us; the upper bound address of the storage space where the operand SM0.0 is located is 2000 and the lower bound address is 2000; It is explained that this instruction needs to read the operand SM0.0 from the corresponding storage space first, and then operate on it, so according to the above description, it is analyzed that the read and write attribute of the operand SM0.0 is read; Program block OB1, Network 1, the instruction is in the line number 1 of Network 1, the operand SM0.0, the execution time is 0.8us, the upper bound address of the storage space where the operand SM0.0 is located is 2000 and the lower bound address is 2000, and the operand SM0.0 The read and write attribute of the instruction is used as the information of the instruction, and the information of the instruction is stored in Table 2; the entire source program is scanned according to the above method, and the instruction information of each instruction is obtained, and stored in Table 2, and then in Table 2, The execution time of the instructions included in each Network is summed to obtain the execution time of each Network, and the execution time of the Network is included in the instruction information.

Table 2

202: Start scanning the instruction information from the main program block of the instruction information, and establish a serial queue;

Among the program blocks included in the source program, there is a program block as the main program block, that is, the MAIN function.

Specifically, a serial queue is established. In the stored instruction information, the main program block is used as the entry, and the instructions included in the Network in the instruction information table are sequentially scanned, and the scanned Network is added to the serial queue as a node, and the scan is judged. Whether the instruction is a CALL instruction, if it is a CALL instruction, jump into the program block called by the CALL instruction, and start scanning instructions from the first Network of the jump-in program block, repeat the above scanning process until the stored instructions are scanned Information, get the serial queue of the entire source program.

For example, in 201, Table 2 for storing instruction information is obtained, start scanning Table 2 from the main program segment OB1, when Network1 is scanned, Network1 is added to the serial queue as a node, and Network2 is used as a node when Network2 is scanned Add to the serial queue. When Network3 is scanned, Network3 will be added to the serial queue as a node. When the third line of command CALLOB2 in Network3 is scanned, it will jump into the program block OB2 called by the CALL command, and start from the program block OB2. When a Network starts scanning, it scans Network1, and adds the scanned Network1 as a node to the serial queue, and the serial queue of the above source program is obtained as shown in Figure 3.

Wherein, in this embodiment, the execution time of the Network is used as the weight of the node.

203: Construct a parallel sequence diagram according to the serial queue;

Specifically, store all nodes included in the serial queue into the parallel sequence diagram, in the serial queue, set pointer 1 to point to the queue head node, set pointer 2 to point to the next node of the node pointed to by pointer 1; according to the operand Storage space and read/write attributes, determine whether there is a data dependency between the node pointed to by pointer 1 and the node pointed to by pointer 2, and if so, in the parallel sequence diagram, add a To the edge, the direction is that the node pointed to by pointer 1 points to the node pointed by pointer 2. At the same time, in the serial queue, reset pointer 2 to point to the next node; if it does not exist, reset pointer 2 to point to the next node in the serial queue One node; scan the serial queue according to the above method, until pointer 2 exceeds the end of the serial queue, reset pointer 1 to point to the next node, pointer 2 to the next node of the node pointed to by pointer 1, and repeat the above scanning process , scan the serial queue according to the above method, until the pointer 1 exceeds the tail of the serial queue, a parallel sequence diagram is constructed.

Among them, the data dependency means that during program execution, multiple instructions perform read and write operations on the same storage space, and determine the sequence relationship between these instructions. For example, for the two instructions of the source program, that is, instruction +I VW2, VW0 and instruction +I VW4, VW2, from the instruction information stored in Table 2, it is found that the storage space of the operand VW2 of the previous instruction is 20016-20031 and The read and write attribute is read, and the storage space of the operand VW2 of the next instruction is found to be 20016~20031, and the read and write attribute is read first and then write, so these two instructions both perform read operations on the storage space corresponding to VW2, so this There is a data dependency between the two instructions. In the present embodiment, any two instructions between the two nodes have a data dependency relationship, then it can be considered that the two nodes have a data dependency relationship, for example, in the source program, the instruction +I VW2, VW0 belongs to the node OB1-Network1, Instruction +I VW4, VW2 belongs to the node OB1-Network2, so there is a data dependency between these two nodes.

For example, scan the serial queue shown in Figure 3, store the nodes OB1-Network1, node OB1-Network2, node OB1-Network3, and node OB2-Network1 in the serial queue into the parallel sequence diagram, and set pointer 1 to point to the node OB1-Network1 and pointer 2 point to the node OB1-Network2. According to the storage space and read-write attributes of the operand, it is judged that there is a data dependency between the node OB1-Network1 and the node OB1-Network2. Because the instruction LDSM0.0 in the node OB1-Network1 The instruction LD SM0.0 in the node OB1-Network2 both reads and writes the storage space of the operand SM0.0, so there is a data dependency between the two instructions, so there is a data dependency between the node OB1-Network1 and the node OB1-Network2 Relationship, in the parallel sequence diagram, add a directed edge between the node OB1-Network1 and the node OB1-Network2, the direction is from the node OB1-Network1 to the node OB1-Network2, and at the same time, in the serial queue, reset the pointer 2 to point to The next node is the node OB1-Network3. It is judged that there is a data dependency between the node OB1-Network1 and the node OB1-Network3. In the parallel sequence diagram, a directed edge is added between the node OB1-Network1 and the node OB1-Network3, and the direction is From the node OB1-Network1 to the node OB1-Network3, reset the pointer 2 to point to the next node OB2-Network1, judge that there is no data dependency between the node OB1-Network1 and the node OB2-Network1, reset the pointer 2 to point down One node, at this time pointer 2 exceeds the end of the queue, reset pointer 1 to point to the next node, which is node OB1-Network2, and pointer 2 to point to the next node of the node pointed to by pointer 1, which is OB1-Network3, repeat the above scanning process, according to the above Method until the pointer 1 exceeds the end of the queue, at this time the entire parallel sequence diagram of the source program is constructed as shown in Figure 4.

204: Optionally, remove redundant edges from the parallel sequence graph;

Among them, as shown in Figure 4, the node OB1-Network1 precedes the node OB1-Network2, and the node OB1-Network2 precedes the node OB1-Network3, so it implies that the node OB1-Network1 precedes the node OB1-Network3, so the node OB1 in the figure The directed edge between -Network1 and node OB1-Network3 is a redundant edge.

Specifically, the nodes in the parallel sequence diagram are traversed through the topological sorting algorithm, the traversed nodes are added to the queue, the successor nodes of the traversed nodes are read, and the predecessor nodes of the successor nodes are searched from the queue , if it exists, mark the directed edge between the predecessor node and the successor node as a redundant edge, and add the node being traversed to the queue, and traverse the next node through the topological sorting algorithm; if it does not exist, it will be The traversed nodes are added to the queue, and the next node is traversed through the topological sorting algorithm, and all redundant edges in the parallel sequence graph are marked according to the above method, and the marked redundant edges are removed from the parallel sequence graph.

For example, to traverse the parallel sequence diagram shown in Figure 4 through the topology sorting algorithm, first traverse the node OB1-Network1, and read the successor nodes of node OB1-Network1, that is, node OB1-Network2 and node OB1-Network3, because the queue at this time is Empty, so there is no predecessor node of node OB1-Network2 and node OB1-Network3 in the queue, the node OB1-Network1 is added to the queue, the next node traversed by the topology sorting algorithm is the node OB1-Network2, and the node OB1 is read -The successor node of Network2 is the node OB1-Network3, among which, the predecessor nodes of the node OB1-Network3 include the node OB1-Network1 and the node OB1-Network2, find out the existence of the node OB1-Network1 from the queue, and mark the node OB1-Network1 and the node The directed edges between OB1-Network3 are redundant edges. Mark all the redundant edges in the parallel sequence diagram according to the above method, remove the redundant edges from the parallel sequence diagram, and obtain the parallel sequence diagram shown in Figure 5.

Wherein, removing redundant edges in the parallel sequence graph can improve the efficiency of scheduling the parallel sequence graph and executing the source program.

205: Schedule the parallel sequence diagram obtained in 204, and execute the source program in parallel.

Specifically, any of the following methods can be used to schedule the parallel sequence diagram and execute the source program in parallel, including:

In the first method, a shared task queue, a master CPU and multiple slave CPUs are first set up, wherein the master CPU is responsible for maintaining the shared queue and assigning tasks to the slave CPUs. The method is specifically as follows: the master CPU decomposes the parallel sequence diagram into multiple connected components, stores each connected component as a task in the shared queue, the master CPU assigns a task to each slave CPU, and the slave CPU executes the tasks in the task. Node, if there is a slave CPU that executes the assigned tasks, the master CPU reassigns tasks for it, if each task in the shared queue is assigned to the slave CPU and all tasks are executed from the CPU, the entire source program is also is executed.

Wherein, in this embodiment, the main CPU may decompose the parallel sequence graph into multiple connected components through a breadth-first algorithm.

For example, first set up a shared queue, one master CPU and two slave CPUs, and then the master CPU uses the breadth-first algorithm to graph the parallel timing sequence shown in Figure 6 into multiple connected components, that is, the connected component 1 shown in Figure 7 , Connected component 2 and Connected component 3, take Connected component 1, Connected component 2 and Connected component 3 as task 1, Task 2 and Task 3 respectively, and store Task 1, Task 2 and Task 3 in the shared queue, the main CPU first Assign task 1 and task 2 to two slave CPUs. When a slave CPU completes the assigned task, the master CPU assigns task 3 to the slave CPU. When the two slave CPUs complete the task, the entire source The program is executed.

In the second method, first set up a shared task queue, master CPU, multiple slave CPUs, and set a task list for each slave CPU, where the master CPU is responsible for maintaining the shared queue and assigning tasks to the slave CPUs, and the slave CPUs will execute each The result is returned to the main CPU. The method is specifically divided into the following steps:

1: The main CPU decomposes the parallel sequence graph into multiple connected components;

For example, if one master CPU and two slave CPUs are set, the master CPU first decomposes the parallel timing diagram shown in Figure 6 into three connected components, namely connected component 1, connected component 2 and connected component 3 as shown in Figure 7 .

2: For a connected component, the main CPU will find out the critical path (a path with the largest weight) from the connected component according to the weight of the node, and traverse the nodes of the critical path until there are multiple predecessor nodes or the successor node is multiple nodes; for convenience of description, this node is referred to as the first stop node.

For example, for the three connected components shown in Figure 7, it is assumed that the weight of each node in the figure is 1, and the main CPU targets a connected component, assuming connected component 2, and finds out that the critical path from connected component 2 is node 3 , node 4, node 5, node 6, node 7 and node 10, and traverse the nodes in the critical path until a node 3 with two successor nodes is traversed, and node 3 is called the first stop node.

3: If the first stop node is a node with multiple predecessor nodes, the main CPU will divide the other nodes from the traversed nodes except the first stop node from the connected component, and use the divided nodes as The task is put into a task list of a slave CPU, which is executed by the slave CPU; if the first stop node is a node with multiple successor nodes, the master CPU will divide the traversed nodes from the connected component, and divide the divided The node is put into the task list of a slave CPU as a task, and is executed by the slave CPU;

Among them, when the number of decomposed connected components is more than the number of slave CPUs, the main CPU repeatedly assigns tasks to each of the remaining slave CPUs according to two steps 2 to 3, when the number of decomposed connected components is less than or When it is equal to the number of slave CPUs, the master CPU divides tasks from each of the remaining connected components repeatedly according to two steps of 2 to 3.

For example, the first stop node, i.e. node 3, is a node with two successor nodes, the traversed node 3 is divided from the connected component 2, and the divided node 3 is put into a task list from the CPU as a task. Execute from the CPU, divide tasks from connected component 1 according to steps 2 and 3, and assign the divided tasks to another slave CPU.

5: The main CPU forms all connected components into a new parallel sequence diagram;

Specifically, if the number of decomposed connected components is more than the number of slave CPUs, the master CPU will form a new parallel sequence graph from the connected components of the divided nodes and the connected components of the undivided nodes, if the decomposed connected components When the number is less than or equal to the number of slave CPUs, the master CPU will be divided into connected components of nodes to form a new parallel sequence diagram;

For example, the main CPU forms the connected component 2 of the divided task and the connected component 3 not divided into a new parallel sequence diagram as shown in FIG. 8 .

6: The main CPU finds the critical path from the new parallel sequence diagram according to the weight of the node, and traverses the critical path until a node with multiple predecessor nodes or multiple successor nodes is traversed. For the convenience of explanation, the node called the second stop node;

For example, the main CPU finds out that the critical path is node 4, node 5, node 6, node 7 and node 10 from the new parallel sequence diagram shown in Figure 8, and traverses the critical path until it finds two predecessor nodes. node 10, and node 10 is called the second stop node.

7: If the second stop node is a node with multiple predecessor nodes, the main CPU will divide other nodes from the traversed nodes except the second stop node from the new parallel sequence diagram, and divide the divided The node is used as a task, and the task is assigned to the slave CPU that can minimize the overhead; if the second stop node is a node with multiple successor nodes, the master CPU divides the traversed nodes from the new parallel sequence diagram , take the divided nodes as tasks, and assign the task to the slave CPU that can minimize the overhead.

Wherein, the main CPU divides all nodes in the new parallel sequence diagram repeatedly according to steps 6 and 7, and when the slave CPU finishes executing all tasks, the entire source program is also executed.

For example, the main CPU traverses the critical path formed by node 4, node 5, node 6, node 7 and node 10, until finding node 10 with two predecessor nodes, node 10 is called the second stop node, and Among the traversed nodes, the nodes other than the second stop node are divided from the new parallel sequence diagram, that is, node 4, node 5, node 6 and node 7 are divided, and the divided nodes are used as tasks, and the Tasks are assigned to the slave CPUs that minimize overhead. Wherein, when the master CPU divides all the nodes in the new parallel sequence diagram and executes all the tasks of the slave CPU, the entire source program is executed.

Among them, in step 7, after the master CPU divides the tasks, it needs to first find out the slave CPU that can minimize the overhead, specifically: the master CPU reads the predecessor node of the first node of the task, from each slave CPU list Find the predecessor node, if the predecessor node exists in a slave CPU list, take the slave CPU with the most current tasks as the slave CPU that can minimize the overhead, if the predecessor node does not exist in all slave CPU lists If the node is trending, the slave CPU with the least current task is taken as the slave CPU that can minimize the overhead.

In addition, it should be noted that when the slave CPU executes the first node of the task, if the execution of the node requires the execution result of the predecessor node of the node, the slave CPU requests the result from the master CPU. If there is this result, then return the result to the slave CPU, if not, then the predecessor node has not been executed by other slave CPUs, at this time, the slave CPU still needs to wait until the predecessor node is executed, the master The CPU receives the result returned from other slave CPUs, and then returns the result to the slave CPU. Wherein, in the process of executing the source program, the communication mode between the master CPU and the slave CPU is master-slave mode.

In addition, it should be noted that: when the slave CPU executes the first node of the source program, if the execution of the node requires the result of the execution of the predecessor node of the node, the slave CPU of the execution task can also execute the result of the predecessor node. The slave CPU of the trend node requests the result. If the slave CPU of the predecessor node has the result, the result will be returned. If not, the result will be returned after the predecessor node is executed and the result is obtained. . Wherein, in the process of executing the source program, this communication mode between the slave CPU and the slave CPU is called peer-to-peer mode.

What has been explained above is the execution process of the scheduling algorithm under the master-slave mode. The scheduling method proposed in the present invention is also applicable to the CPU full peer-to-peer mode. The CPUs can communicate with each other in pairs.

Wherein, in this embodiment, the parallel timing diagram is scheduled, and the source program is executed in parallel, so that the entire source program can be executed in one scan cycle, so that the source program does not need to be divided into multiple segments to be executed separately, and the source program does not need to be written in on multiple PLCs.

In the embodiment of the present invention, by scanning the text file of the source program, instruction information is acquired, the instruction information is scanned, a serial queue is established, a parallel timing diagram is constructed according to the serial queue, the parallel timing diagram is scheduled, and the source program is executed in parallel, so that The entire source program can be executed in one scan cycle, without the need to divide the source program into multiple segments for separate execution or write the source program on different PLCs, which improves the efficiency of source program development and facilitates debugging and deployment of source programs.

Example 3

The embodiment of the present invention provides a method for verifying program results. In Embodiment 2, the CPU records the execution time of each node of the source program, sorts the nodes included in the source program according to the time, and obtains the sequence in which the nodes are executed That is, the program execution sequence. This embodiment verifies the program execution sequence to determine whether the result of executing the source program in Embodiment 2 is correct. As shown in Figure 9, the method includes:

301: Convert each node in the parallel sequence diagram into a transition node in the Petri net model;

Among them, the parallel sequence diagram is the parallel sequence diagram obtained in Example 2. The Petri net model is composed of two types of nodes, transition (Transition) and place (Place), and the nodes directly connected before and after the transition node are all library nodes. The connected nodes are all transition nodes. The transition node is used to represent an action in the system or an event involving state change, and the library node is used to represent the specific conditions involved in the occurrence of the event, including preconditions and postconditions. Among them, in this embodiment, the library nodes directly connected before and after the transition nodes in the Petri net model are respectively referred to as front library nodes and back library nodes. It is used to store the post-conditions of the occurrence of the transition node. When a transition node occurs, the preconditions stored in the front library node of the transition node are moved into the back library node of the transition node, or the postconditions stored in the back library node of the transition node are moved into the front library node of the transition node node.

Wherein, in this embodiment, the nodes in the parallel sequence diagram are used as the transition nodes in the Petri net model, specifically, the one-to-one mapping relationship between the nodes in the parallel sequence diagram and the transition nodes in the Petri net model is established, according to the established The mapping relation of converts the nodes in the parallel sequence graph into transition nodes in the Petri net model.

302: Connect transition nodes in the Petri net model according to the topology structure of the parallel sequence diagram;

Specifically, in the Petri net model, the front-storage node is added before the transition node, the back-storage node is added after the transition node, and the front-storage node and the transition node are connected, as well as the transition node and the back-storage node. The topology structure of the parallel sequence diagram is Referring to the object, add a virtual transition node between the two adjacent storage nodes in the Petri net model, connect the front storage node and the virtual transition node, and the virtual transition node and the back storage node, thus connecting all the transition nodes in the Petri net model .

For example, convert the nodes in the parallel sequence diagram shown in Figure 10 into transition nodes in the Petri net model, add front-storage nodes and back-storage nodes before and after the transition nodes, and connect the front-storage nodes and transition nodes and transition nodes respectively. Nodes and post-base nodes, taking the parallel sequence diagram shown in Figure 10 as a reference object, add a virtual transition node between two consecutive adjacent library nodes, respectively connect the front-base node and the virtual transition node, and the virtual transition node and After the library node, the Petri net model shown in Figure 11 is obtained.

303: Petri net model of simplified connection;

Specifically, in the Petri net model, the virtual transition node, the front bank node of the virtual transition node and the back bank node of the virtual transition node are combined into a pool point representation.

For example, in the Petri net model shown in Figure 11, the virtual transition node, the front library node of the virtual transition node and the back library node of the virtual transition node are merged into one library node, and as shown in Figure 12, Petri net model.

304: Set an initial flag in the first library node of the simplified Petri net model;

Wherein, in this embodiment, the initial flag is used as the condition for executing the transition node. When the transition node is executed, the initial flag must be stored in the previous library node, otherwise, an execution error occurs.

305: After executing 304, set the pointer to point to the first node in the program execution sequence;

306: Map the node pointed by the pointer to the corresponding transition node in the Petri net model;

307: Judging whether there is an initial flag in the front library node of the transition node, if it exists, execute 308, otherwise, the operation ends, and the error message of the program result is returned;

For example, set the initial state X in the first library node of the Petri net model shown in Figure 11, for the program execution sequence that is node A, node B, node C and node D, first set the pointer to point to node A, set the node A is mapped to transition node A in the Petri net model, and it is judged that the former storage node of transition node A has an initial mark X, and 308 is executed.

308: Execute the transition node, that is, move the initial mark of the front library node of the transition node into the back library node. When there are other nodes in the program execution sequence, reset the pointer to point to the next node, and return to 306, otherwise, return Program results correct information.

For example, move the initial mark X into the back library node of transition node A, reset the pointer to point to node B, and return 306.

Wherein, in this embodiment, if the returned result is information that the program result is wrong, the result of executing the source program in embodiment 2 is incorrect; if the returned result is information that the program result is correct, then the result of executing the source program in embodiment 2 correct.

In the embodiment of the present invention, the Petri net model is constructed through the parallel sequence diagram, and according to the Petri net model, it is verified whether the program execution sequence is correct, so as to determine whether the execution result of the source program is correct.

Example 4

As shown in the figure, an embodiment of the present invention provides an apparatus for executing a program, including:

An acquisition module 401, configured to acquire instruction information from the text file of the source program;

A building module 402, configured to set up a serial queue according to the acquired instruction information;

A construction module 403, configured to construct a parallel sequence diagram according to the established serial queue;

The execution module 404 is configured to execute the source program in parallel according to the constructed parallel sequence diagram.

Wherein, the acquisition module 401 specifically includes:

The first scanning unit is used to sequentially scan the instructions in the text file of the source program;

The reading unit is used to read the name and operand of the instruction, the Network to which the instruction belongs, and the program block to which it belongs;

Computing unit, used to calculate the execution time of the Network;

The first acquisition unit is used to acquire the storage space and read/write attributes of the operand;

Use the name of the instruction, the operand of the instruction, the Network to which the instruction belongs and the program block to which it belongs, the execution time of the Network, the storage space of the operand, and the read and write attributes as the instruction information;

The building module 402 specifically includes:

Establishing a unit for establishing a serial queue;

The second scanning unit is used to be an entry from the main program block of the program block of the instruction information, and sequentially scans the instructions included in the Network in the instruction information;

The addition unit is used to add the scanned Network as a node to the serial queue, wherein the execution time of the Network is used as the weight of the node;

Judging unit, for judging whether the scanned instruction is a CALL instruction, if the scanned instruction is a CALL instruction, jump into the program block called by the CALL instruction, and scan the instructions included in the Network in the called program block;

The construction module 403 specifically includes:

The storage unit is used to store the nodes in the serial queue into the parallel timing diagram;

The first setting unit is used to set the pointer 1 to point to the queue head node in the serial queue, and set the pointer 2 to point to the next node of the node pointed to by the pointer 1;

The first judging unit is used to judge whether there is a data dependency relationship between the node pointed to by pointer 1 and the node pointed to by pointer 2. To the edge, the direction is that the node pointed to by pointer 1 points to the node pointed by pointer 2. In the serial queue, reset pointer 2 to point to the next node; if it does not exist, reset pointer 2 to point to the next node in the serial queue ;

Optionally, the execution module 404 specifically includes:

a first decomposition unit, configured to decompose the parallel sequence graph into connected components;

The first assignment unit is used to assign the decomposed connected components to the CPU, and the CPU executes the nodes of the assigned connected components;

Optionally, the execution module 404 specifically includes

The second decomposition unit is used to decompose the parallel sequence graph into connected components;

The first search unit is used to find the critical path of the connected component according to the weight of the node;

The division unit is used to divide the nodes from the connected components according to the key path searched, and assign the divided nodes to the CPU, and the CPU executes the divided nodes;

A composition unit for composing connected components into a new parallel sequence graph;

A search unit is used to find a critical path from the new parallel sequence diagram;

A separation unit is used to separate nodes from the new parallel sequence diagram according to the critical path to be found, assign the separated nodes to CPUs, and execute the separated nodes by the CPUs;

Among them, the division unit specifically includes:

The first traversal subunit is used for traversing the key path of the search until a node with multiple predecessor nodes or multiple successor nodes is traversed. For the convenience of description, this node is called the first stop node;

The first division subunit is used to divide the nodes traversed except the first stop node from the connected components if the first stop node is a node with multiple predecessor nodes, and assign the divided nodes to the CPU;

The second division subunit is used to divide the traversed nodes from the connected components if the first stop node is a node with multiple successor nodes, and distribute the divided nodes to the CPU;

The separation unit specifically includes:

The second traversal subunit is used to traverse the found critical path until a node with multiple predecessor nodes or multiple successor nodes is traversed. For the convenience of description, this node is called the second stop node;

The third dividing subunit is used to divide the nodes in the traversed nodes except the second stopping node from the new parallel sequence diagram if the second stop node is a node with multiple predecessor nodes, and divide the divided nodes Nodes are assigned to CPUs that minimize overhead;

The fourth division subunit is used to divide the traversed nodes from the new parallel sequence diagram if the second stop node is a node with multiple successor nodes, and allocate the divided nodes to the CPU that can minimize the overhead;

Further, the device for executing the program also includes:

The traversal module is used to traverse the nodes in the parallel sequence diagram through the topology sorting algorithm, add the traversed nodes to the queue, and read the successor nodes of the traversed nodes;

The search module is used to find out whether there is a predecessor node of the successor node from the queue. If it exists, mark the directed edge between the predecessor node and the successor node as a redundant edge, add the node being traversed to the queue, and pass the topology The sorting algorithm traverses the next node; if it does not exist, the node being traversed is added to the queue, and the next node is traversed through the topological sorting algorithm;

Removal module for removing redundant edges from parallel timing diagrams.

Wherein, in this embodiment, according to the parallel sequence diagram, the source program is executed in parallel, so that the entire source program can be executed within one scan cycle.

In the embodiment of the present invention, by obtaining instruction information from the text file of the source program, scanning the instruction information, establishing a serial queue, constructing a parallel timing diagram according to the serial queue, and executing the source program in parallel according to the parallel timing diagram, so that Execute the entire source program in one scan cycle, without dividing the source program into multiple segments for separate execution or writing the source program on different PLCs, each PLC executes it independently, which improves the efficiency of source program development and facilitates debugging and deployment of source programs .

Example 5

As shown in the figure, an embodiment of the present invention provides a device for verifying program results, including:

Creating module 501, for creating a Petri net model according to the parallel sequence diagram;

The first setting module 502 is used to set the initial sign in the first library node in the created Petri net model;

The second setting module 503 is used to set the pointer to point to the first node in the program execution sequence after the initial flag is set by the first setting module 502;

A mapping module 504, configured to map the node pointed to by the pointer to the corresponding transition node in the Petri net model;

The first judging module 505 is used to judge whether there is an initial mark in the front library node of the transition node of the mapping, if not, then return the information that the program result is wrong;

The second judging module 506 is used for when the result of judging by the first judging module 505 is yes, move the initial flag into the back library node of the transition node of the mapping, judge whether there are other nodes in the program execution sequence, and if so, set the pointer Point to the next node, if not, return the information that the program result is correct.

Wherein, the creation module 501 specifically includes:

A conversion unit is used to convert the nodes in the parallel sequence graph into transition nodes in the Petri net model;

The connection unit is used to connect the transition nodes in the Petri net model according to the topology of the parallel sequence diagram;

Simplification unit, used to simplify the Petri net model.

In the embodiment of the present invention, a Petri net model is constructed by constructing a parallel sequence diagram, and according to the Petri net model, it is verified whether the program execution sequence is correct, so as to obtain whether the execution result of the source program is correct.

Example 6

As shown in Figure 15, an embodiment of the present invention provides a system for executing programs, including:

The device 601 for executing the program is used to obtain instruction information from the text file of the source program; establish a serial queue according to the obtained instruction information; construct a parallel sequence diagram according to the established serial queue; and construct a parallel sequence diagram according to the constructed parallel sequence diagram, Execute the source program in parallel;

The device 602 for verifying program results is used to create a Petri net model according to the constructed parallel sequence diagram; set the initial flag in the first library node in the created Petri net model; set the pointer to point to the first in the program execution sequence Node; map the node pointed to by the pointer to the corresponding transition node in the created Petri net model; judge whether there is an initial mark in the front library node of the mapped transition node, and if so, move the initial mark into the back library node of the mapped transition node ; If not, return the information that the program result is wrong; judge whether there are other nodes in the program execution sequence, if yes, set the pointer to point to the next node, if not, return the correct information of the program result.

Wherein, in this embodiment, according to the parallel sequence diagram, the source program is executed in parallel, so that the entire source program is executed within one scan cycle.

In the embodiment of the present invention, by obtaining instruction information from the text file of the source program, a serial queue is established according to the instruction information, a parallel sequence diagram is constructed according to the serial queue, and the source program is executed in parallel according to the parallel sequence diagram, so that in Execute the entire source program in one scan cycle, without dividing the source program into multiple segments for separate execution or writing the source program on different PLCs, each PLC executes it independently, which improves the efficiency of source program development and facilitates debugging and deployment of source programs .

All or part of the technical solutions provided by the above embodiments can be realized by software programming, and the software program is stored in a readable storage medium, such as a hard disk, an optical disk or a floppy disk in a computer.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (13)

1. A method for executing a program, characterized in that the method comprises: Sequentially scan the instructions in the text file of the source program; Read the name of the instruction, the operand of the instruction, the delimiter to which the instruction belongs, and the program block to which the instruction belongs; calculating the execution time of said delimiter; Obtain the storage space and read/write attributes of the operand; The name of the instruction, the operand of the instruction, the delimiter and the program block to which the instruction belongs, the execution time of the delimiter, the storage space of the operand and the read-write attribute are used as the instruction information; Create a serial queue; From the main program block of the program block of the instruction information as an entry, sequentially scan the instructions included in the delimiter in the instruction information; adding the delimiter as a node to the serial queue, wherein the execution time of the delimiter is used as the weight of the node; Judging whether the instruction is to call a CALL instruction, if the instruction is a CALL instruction, then jump into the program block called by the CALL instruction, and scan the instructions included in the delimiter in the program block; storing the nodes in the serial queue into a parallel sequence diagram; In the serial queue, the pointer 1 is set to point to the team head node, and the pointer 2 is set to point to the next node of the node pointed to by the pointer 1; According to the storage space and the read-write attribute of the operand, it is judged whether there is a data dependency relationship between the node pointed to by the pointer 1 and the node pointed to by the pointer 2, and if there is, in the parallel sequence diagram, the node pointed by the pointer 1 A directed edge is added between the node pointed to by the pointer 2 and the node pointed to by the pointer 2, and the direction is that the node pointed to by the pointer 1 points to the node pointed to by the pointer 2, and in the serial queue, the pointer 2 points to next node; If it does not exist, in the serial queue, reset the pointer 2 to point to the next node; Executing the source program in parallel according to the parallel sequence diagram; Wherein, the source program is composed of one or more program blocks, the program block is composed of one or more delimiters, and the delimiter is composed of one or more instructions. 2. The method according to claim 1, characterized in that, according to the serial queue, after constructing a parallel sequence diagram, the method further comprises: traversing the nodes in the parallel sequence diagram through a topological sorting algorithm, adding the traversed nodes to the queue, and reading the successor nodes of the traversed nodes; Find whether there is a predecessor node of the successor node from the queue, if it exists, mark the directed edge between the predecessor node and the successor node as a redundant edge, and the node being traversed Join the queue, and traverse the next node through the topological sorting algorithm; If it does not exist, the node being traversed is added to the queue, and the next node is traversed by the topology sorting algorithm; Redundant edges are removed from the parallel timing graph. 3. The method according to claim 1, wherein said executing said source program in parallel according to said parallel sequence diagram specifically comprises: decomposing the parallel timing graph into connected components; The connected components are assigned to a CPU, and the nodes of the connected components are executed by the CPU. 4. The method according to claim 1, wherein said executing said source program in parallel according to said parallel sequence diagram specifically comprises decomposing the parallel timing graph into connected components; Finding the critical path of the connected component according to the weight of the node; dividing nodes from the connected components according to the critical path, allocating the divided nodes to a CPU, and executing the divided nodes by the CPU; Composing the connected components into a new parallel sequence graph; Finding a critical path from the new parallel sequence diagram according to the weights of the nodes; According to the found critical path, separate nodes from the new parallel sequence diagram, assign the separated nodes to the CPU, and execute the separated nodes by the CPU. 5. A method for verifying program results, characterized in that the method comprises: Create a Petri net model based on the parallel sequence diagram; Initial flag is set in the first storehouse node in described Petri net model; Set the pointer to point to the first node in the program execution sequence; Mapping the node pointed by the pointer to the corresponding transition node in the Petri net model; Judging whether the initial flag exists in the front library node of the transition node, if not, returning the error message of the program result; If yes, move the initial flag into the back library node of the transition node, judge whether there are other nodes in the program execution sequence, if yes, set the pointer to point to the next node, if not, return the program result is correct Information. 6. the method for claim 5, is characterized in that, described according to parallel timing diagram, creates Petri net model, specifically comprises: Converting the nodes in the parallel sequence diagram into transition nodes in the Petri net model; According to the topology structure of the parallel sequence diagram, connect the transition nodes in the Petri net model; Simplify the Petri net model. 7. A device for executing a program, characterized in that the device includes an acquisition module, an establishment module, a construction module and an execution module: The acquisition module includes a first scanning unit, a reading unit, a calculation unit and a first acquisition unit; The first scanning unit is used to sequentially scan the instructions in the text file of the source program; The reading unit is configured to read the name of the instruction, the operand of the instruction, the delimiter to which the instruction belongs, and the program block to which the instruction belongs; The calculation unit is used to calculate the execution time of the delimiter; The first acquiring unit is configured to acquire the storage space and read/write attributes of the operand; The name of the instruction, the operand of the instruction, the delimiter and the program block to which the instruction belongs, the execution time of the delimiter, the storage space of the operand and the read-write attribute are used as the instruction information; The building module includes a building unit, a second scanning unit, an adding unit and a judging unit; The establishment unit is used to establish a serial queue; The second scanning unit is configured to sequentially scan the instructions included in the delimiter in the instruction information from the main program block of the instruction information program block as an entry; The adding unit is configured to add the delimiter as a node to the serial queue, wherein the execution time of the delimiter is used as the weight of the node; The judging unit is used to judge whether the instruction is a call CALL instruction, if the instruction is a CALL instruction, then jump into the program block called by the CALL instruction, and scan the instructions included in the delimiter in the program block ; The construction module includes a storage unit, a first setting unit and a first judging unit; The storage unit is used to store the nodes in the serial queue into a parallel sequence diagram; The first setting unit is configured to set the pointer 1 to point to the queue head node in the serial queue, and set the pointer 2 to point to the node next to the node pointed to by the pointer 1; The first judging unit is configured to judge whether there is a data dependency relationship between the node pointed to by the pointer 1 and the node pointed to by the pointer 2 according to the storage space and the read/write attribute of the operand, and if so, in the parallel sequence In the figure, a directed edge is added between the node pointed to by the pointer 1 and the node pointed to by the pointer 2, and the direction is that the node pointed to by the pointer 1 points to the node pointed to by the pointer 2, and in the serial queue , reset the pointer 2 to point to the next node; if it does not exist, reset the pointer 2 to point to the next node in the serial queue; The execution module is configured to execute the source program in parallel according to the parallel sequence diagram; Wherein, the source program is composed of one or more program blocks, the program block is composed of one or more delimiters, and the delimiter is composed of one or more instructions. 8. The device of claim 7, further comprising: The traversal module is used to traverse the nodes in the parallel sequence diagram through a topology sorting algorithm, add the traversed nodes to the queue, and read the successor nodes of the traversed nodes; A search module, configured to search from the queue whether there is a predecessor node of the successor node, and if so, mark the directed edge between the predecessor node and the successor node as a redundant edge, and convert all The node being traversed is added to the queue, and the next node is traversed by the topological sorting algorithm; if it does not exist, the node being traversed is added to the queue, and the next node is traversed by the topological sorting algorithm; A removal module, configured to remove redundant edges from the parallel sequence graph. 9. The device according to claim 7, wherein the execution module specifically comprises: a first decomposing unit, configured to decompose the parallel sequence graph into connected components; A first allocating unit, configured to allocate the connected components to a CPU, and the CPU executes the nodes of the connected components. 10. The device according to claim 7, wherein the execution module specifically includes a second decomposing unit, configured to decompose the parallel sequence graph into connected components; a first search unit, configured to search for the critical path of the connected component according to the weight of the node; A dividing unit, configured to divide nodes from the connected components according to the critical path, assign the divided nodes to a CPU, and execute the divided nodes by the CPU; a composition unit, configured to form the connected components into a new parallel sequence diagram; a finding unit, configured to find a critical path from the new parallel sequence diagram according to the weights of the nodes; A separating unit is configured to separate nodes from the new parallel sequence diagram according to the found critical path, assign the separated nodes to the CPU, and execute the separated nodes by the CPU. 11. A device for verifying program results, characterized in that the device comprises: Create a module for creating a Petri net model based on a parallel sequence diagram; The first setting module is used to set the initial sign in the first library node in the Petri net model; The second setting module is used to set the pointer to point to the first node of the program execution sequence; A mapping module, configured to map the node pointed to by the pointer to the corresponding transition node in the Petri net model; The first judging module is used to judge whether the initial flag exists in the front library node of the transition node, and if not, return the information that the program result is wrong; The second judging module is used to move the initial flag into the back library node of the transition node when the judging result of the first judging module is yes, and judge whether there are other nodes in the program execution sequence, if yes , set the pointer to point to the next node, if not, return the information that the program result is correct. 12. The device according to claim 11, wherein the creation module specifically comprises: A mapping unit, configured to convert the nodes in the parallel sequence diagram into transition nodes in the Petri net model; a connection unit, configured to connect transition nodes in the Petri net model according to the topology of the parallel sequence diagram; A simplification unit is used to simplify the Petri net model. 13. A system for executing a program, characterized in that said system comprises means for executing the program and means for verifying the result of the program: The device for executing the program includes an acquisition module, an establishment module, a construction module and an execution module; The acquisition module includes a first scanning unit, a reading unit, a calculation unit and a first acquisition unit; The first scanning unit is used to sequentially scan the instructions in the text file of the source program; The reading unit is configured to read the name of the instruction, the operand of the instruction, the delimiter to which the instruction belongs, and the program block to which the instruction belongs; The calculation unit is used to calculate the execution time of the delimiter; The first acquiring unit is configured to acquire the storage space and read/write attributes of the operand; The name of the instruction, the operand of the instruction, the delimiter and the program block to which the instruction belongs, the execution time of the delimiter, the storage space of the operand and the read-write attribute are used as the instruction information; The building module includes a building unit, a second scanning unit, an adding unit and a judging unit; The establishment unit is used to establish a serial queue; The second scanning unit is configured to sequentially scan the instructions included in the delimiter in the instruction information from the main program block of the instruction information program block as an entry; The adding unit is configured to add the delimiter as a node to the serial queue, wherein the execution time of the delimiter is used as the weight of the node; The judging unit is used to judge whether the instruction is a call CALL instruction, if the instruction is a CALL instruction, then jump into the program block called by the CALL instruction, and scan the instructions included in the delimiter in the program block ; The construction module includes a storage unit, a first setting unit and a first judging unit; The storage unit is used to store the nodes in the serial queue into a parallel sequence diagram; The first setting unit is configured to set the pointer 1 to point to the queue head node in the serial queue, and set the pointer 2 to point to the node next to the node pointed to by the pointer 1; The first judging unit is configured to judge whether there is a data dependency relationship between the node pointed to by the pointer 1 and the node pointed to by the pointer 2 according to the storage space and the read/write attribute of the operand, and if so, in the parallel sequence In the figure, a directed edge is added between the node pointed to by the pointer 1 and the node pointed to by the pointer 2, and the direction is that the node pointed to by the pointer 1 points to the node pointed to by the pointer 2, and in the serial queue , reset the pointer 2 to point to the next node; if it does not exist, reset the pointer 2 to point to the next node in the serial queue; The execution module is configured to execute the source program in parallel according to the parallel sequence diagram; Wherein, the source program is composed of one or more program blocks, the program block is composed of one or more delimiters, and the delimiter is composed of one or more instructions; The device for verifying program results includes a creation module, a first setting module, a second setting module, a mapping module, a first judging module and a second judging module; The creation module is used to create a Petri net model according to the parallel sequence diagram; The first setting module is used to set an initial flag in the first library node in the Petri net model; The second setting module is used to set the pointer to point to the first node of the program execution sequence; The mapping module is configured to map the node pointed by the pointer to the corresponding transition node in the Petri net model; The first judging module is used to judge whether the initial flag exists in the front library node of the transition node, and if not, return the error message of the program result; The second judging module is configured to move the initial flag into the back library node of the transition node when the judging result of the first judging module is yes, and judge whether there are other nodes in the program execution sequence, If yes, set the pointer to point to the next node, if no, return information that the program result is correct.

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