CN101557272A - Method and device for interleaving high-order modulated HS-DSCH in TD-SCDMA system HSOPA - Google Patents

Abstract

The invention discloses a method for interleaving high-order modulated HS-DSCH, a method for modulating the HS-DSCH at high order and a device for interleaving the high-order modulated HS-DSCH in a TD-SCDMA system HSDPA. The technical scheme is as follows: the method for interleaving high-order modulated HS-DSCH comprises the following steps: one input bit sequence is divided into n groups of bit data, wherein the n is larger than or equal to 3; n interleavers which have same interleave depth are adopted for processing the n groups of bit data, wherein each group of bit data is independently interleaved in the corresponding interleaver; and the bite data of the n interleavers are merged into one output bit sequence. The invention is applied to the field of mobile communications.

Description

The HS-DSCH deinterleaving method and the device of high order modulation in the TD-SCDMA system HSDPA

Technical field

The present invention relates to the HS-DSCH deinterleaving method and the device of high order modulation in a kind of TD-SCDMA system HSDPA, relate in particular to the individual interleaver of a kind of employing n (n 〉=3) walk abreast the HS-DSCH deinterleaving method and the device to high order modulation of interleaving treatment.

Background technology

Along with increasing of mobile multi-media service, the transmission rate of 3-G (Generation Three mobile communication system) 2Mb/s can not meet the demands, and the mobile communication system that development has bigger capacity and bigger Bit Transmission Rate becomes inevitable.Therefore, WCDMA (Wideband Code Division Multiple Access, Wideband Code Division Multiple Access (WCDMA)), CDMA2000 and TD-SCDMA (Time Division-Synchronous CodeDivision Multiple Access, TD SDMA) all strengthens carrying out technology, with the higher service rate of development, (back three generations's mobile communication) applied business of more B3G is provided.In the 3GPP standard, the HSDPA (High Speed Downlink Packet Access, high speed downlink packet inserts) of WCDMA and TD-SCDMA has been proposed to be applicable to based on the UMTS standard.In the 3GPP2 of another standardization body, similar techniques is also arranged, they are CDMA20001X EV-DO and EV-DV.

HSDPA is a kind of enhanced scheme that 3GPP Release 5 proposes, and main purpose is the high speed support to Packet data service, and obtains lower time delay, higher throughput of system and stronger QoS and guarantee.From technical standpoint, HSDPA strengthens air interface by introducing high speed descending sharing channel (HS-DSCH), and strengthens corresponding functional entity in UTRAN.From bottom, mainly be that introducing Adaptive Modulation and Coding (AMC) and H-ARQ (hybrid ARQ) technology increase data throughout.

The HARQ system introduces a FEC subsystem in the ARQ system, be used for correcting the error pattern of frequent appearance to reduce number of retransmissions, promptly in the error correcting capability scope, automatically correct a mistake, exceed the error correction scope and then require transmitting terminal to resend data, this has increased the reliability and the efficiency of transmission of system.That is to say that the channel condition that H-ARQ can adapt to moment automatically provides trickle data rate adjustment, select a suitable modulation and coded system then to obtain according to the channel condition that UE measures or network terminal determines by AMC.AMC according to the change of channel quality condition, adjusts modulation and coded system in the scope of system constraint.In an AMC system, the user who sits pretty (normally those users very near apart from the base station) can be endowed higher modulation and coded system (such as 16QAM and 1/2Turbo encoding rate); And the user's (normally those are in the user of cell boarder) who is in unfavorable position can be endowed lower modulation and coded system (such as QPSK and 1/2Turbo encoding rate).In the AMC system, the base station remains unchanged for each user's transmitted power, for position user preferably, channel condition is good, and system can provide the data service of two-forty to it, increase overall system throughput, and at utmost strengthen the transmittability of Packet data service, improve power system capacity, need to introduce higher code rate and more high-order modulating (as 32QAM, 64QAM, 256QAM).

At present in the standard, the HSDPA technology of TD-SCDMA system is only supported two kinds of modulation system QPSK (Quadrature Phase Shift Keying) and 16QAM (16 rank quadrature amplitude modulation), corresponding HS-DSCH deinterleaving method can only be supported QPSK and 16QAM, can't support high-order modulating such as 32QAM, the HSDPA of 64QAM or 256QAM etc.

Summary of the invention

The objective of the invention is to address the above problem, the HS-DSCH deinterleaving method of high order modulation in a kind of TD-SCDMA system HSDPA is provided, can't realize the problem that high-order modulating interweaves to overcome in the existing HSDPA system HS-DSCH deinterleaving method.

Another object of the present invention is to provide the method for high order modulation HS-DSCH in a kind of TD-SCDMA system HSDPA, made HSDPA support 32QAM, 64QAM or the contour contrast system of 256QAM.

Another object of the present invention is to provide the HS-DSCH interlaced device of high order modulation in a kind of TD-SCDMA system HSDPA, can't realize the problem that high-order modulating interweaves to overcome in the existing HSDPA system HS-DSCH interlaced device.

Technical scheme of the present invention is: the present invention has disclosed the HS-DSCH deinterleaving method of high order modulation in a kind of TD-SCDMA system HSDPA, comprising:

The bit sequence of an input is divided into n group Bit data, wherein n 〉=3;

Adopt n the identical interleaver of interleave depth that described n group Bit data is carried out parallel processing, the individual interleaving in the interleaver of correspondence of every group of Bit data wherein;

The bit sequence of an output is merged in the Bit data output of a described n interleaver.

The HS-DSCH deinterleaving method of high order modulation in the above-mentioned TD-SCDMA system HSDPA, wherein, adopt the data interlacing process of block interleaver to comprise:

Line by line the input bit sequence is write in the matrix, dummy bits is filled into the relevant position of matrix;

Carry out between this matrix column and replace;

Read the output bit sequence of block interleaver the matrix between row after the displacement by row, the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

The HS-DSCH deinterleaving method of high order modulation in the above-mentioned TD-SCDMA system HSDPA, wherein, this deinterleaving method is handled the high order modulation of 32QAM, 64QAM or 256QAM.

The present invention has disclosed the method for high order modulation HS-DSCH in a kind of TD-SCDMA system HSDPA in addition, comprising:

HS-DSCH is carried out the multipling channel cataloged procedure, and comprising the interleaving procedure to high order modulation, this interleaving procedure comprises:

The bit sequence of an input is divided into n group Bit data, wherein n 〉=3;

Adopt n the identical interleaver of interleave depth that described n group Bit data is carried out parallel processing, the individual interleaving in the interleaver of correspondence of every group of Bit data wherein;

The bit dateout of a described n interleaver is merged into the bit sequence of an output;

Terminal receives HS-SCCH message, indicates the resource allocation conditions of next HS-DSCH transmission;

Terminal is measured accordingly and is carried out the demultiplexing decode procedure, comprising with the described deinterleaving processing procedure opposite to the interleaving treatment of high order modulation;

According to HS-DSCH resource allocation conditions and measurement result, terminal produces a channel quality indication;

The channel quality indication that produces reports to the base station on corresponding ascending control channel.

The method of high order modulation HS-DSCH in the above-mentioned TD-SCDMA system HSDPA, wherein, adopt the data interlacing process of block interleaver to comprise:

Line by line the input bit sequence is write in the matrix, dummy bits is filled into the relevant position of matrix;

Carry out between this matrix column and replace;

Read the output bit sequence of block interleaver the matrix between row after the displacement by row, the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

The method of high order modulation HS-DSCH in the above-mentioned TD-SCDMA system HSDPA, wherein, this high order modulation comprises the high order modulation of 32QAM, 64QAM or 256QAM.

The present invention has also disclosed the HS-DSCH interlaced device of high order modulation in a kind of TD-SCDMA system HSDPA, comprising:

The input grouping module is divided into n group Bit data, wherein n 〉=3 with the bit sequence of an input;

The interleaver group comprises n the interleaver that interleave depth is identical, and each interleaver carries out parallel processing to one group of Bit data wherein, the individual interleaving in the interleaver of correspondence of every group of Bit data wherein;

Output merges module, the Bit data output of this n interleaver is merged into the bit sequence of an output.

The HS-DSCH interlaced device of high order modulation in the above-mentioned TD-SCDMA system HSDPA, wherein, this interleaver further comprises:

The matrix input unit, the bit sequence of input is write in the matrix line by line, is filled into the relevant position of matrix with dummy bits;

Permute unit between row is carried out replacement operator between matrix column;

The matrix output unit is read the output bit sequence by row the matrix between these row behind the permute unit, and the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

The HS-DSCH interlaced device of high order modulation in the above-mentioned TD-SCDMA system HSDPA, wherein, the high order modulation that this device is handled comprises the high order modulation of 32QAM, 64QAM or 256QAM.

The present invention contrasts prior art following beneficial effect: the present invention is divided into n group (n 〉=3) by the bit sequence with input, adopt n the identical interleaver of interleave depth that this n group Bit data is carried out the parallel processing of individual interleaving, the bit sequence of an output is merged in the output of this n interleaver.The contrast prior art, the present invention makes the HSDPA system support 32QAM, 64QAM or the contour contrast system of 256QAM amended HS-DSCH deinterleaving method, realizes the control to high-order modulating, has effectively improved system peak transmission rate and band efficiency.

Description of drawings

Fig. 1 is the flow chart of a preferred embodiment of the HS-DSCH deinterleaving method of high order modulation in the TD-SCDMA system HSDPA of the present invention.

Fig. 2 is the flow chart of the data interlacing process of block interleaver.

Fig. 3 A is the schematic diagram at the block interleaver of QPSK modulation, and Fig. 3 B is that Fig. 3 C is the schematic diagram at the block interleaver of high order modulation at the schematic diagram of the block interleaver of 16QAM modulation.

Fig. 4 is the flow chart of a preferred embodiment of the method for high order modulation HS-DSCH in the TD-SCDMA system HSDPA of the present invention.

Fig. 5 is the flow chart that the deinterleaving method with high order modulation of the present invention is applied to HS-DSCH is carried out the multipling channel cataloged procedure.

Fig. 6 is the schematic diagram of a preferred embodiment of the HS-DSCH interlaced device of high order modulation in the TD-SCDMA system HSDPA of the present invention.

Fig. 7 is the schematic diagram of block interleaver.

Embodiment

The invention will be further described below in conjunction with drawings and Examples.

Fig. 1 shows the flow process of a preferred embodiment of the HS-DSCH deinterleaving method of high order modulation in the TD-SCDMA system HSDPA of the present invention.Fig. 3 C is the schematic diagram at the block interleaver of high order modulation.Please be detailed description below simultaneously referring to Fig. 1 and Fig. 3 C to each step in this method.

Step S10: the bit sequence of an input is divided into 4 groups of Bit datas.

Seeing also Fig. 3 C, is the bit sequence S with an input in the present embodiment ₁, S ₂..., S _RBe divided into 4 groups of Bit data: S ₁, S ₅..., S _R-3S ₂, S ₆..., S _R-2S ₃, S ₇..., S _R-1S ₄, S ₈... S _R

Step S12: adopt 4 identical interleavers of interleave depth that 4 groups of Bit datas are carried out parallel processing, wherein every group of Bit data individual interleaving in the interleaver of correspondence.

Seeing also Fig. 3 C, is the block interleaver 300～303 that adopts 4 interleave depths identical (R2 * 30) in the present embodiment.300 couples of S of block interleaver wherein ₁, S ₅..., S _R-3This group Bit data carry out individual interleaving, 301 couples of S of block interleaver ₂, S ₆..., S _R-2This group Bit data carry out individual interleaving, 302 couples of S of block interleaver ₃, S ₇..., S _R-1This group Bit data carry out individual interleaving, 303 couples of S of block interleaver ₄, S ₈... S _RThis group Bit data carry out individual interleaving.

Step S 14: the bit sequence of the Bit data output of 4 interleavers being merged into an output.

See also Fig. 3 C, the Bit data of block interleaver 300 is output as v in the present embodiment ₁, v ₅... v _R-3, the Bit data of block interleaver 301 is output as v ₂, v ₆..., v _R-2, the Bit data of block interleaver 302 is output as v ₃, v ₇..., v _R-1, the Bit data of block interleaver 303 is output as v ₄, v ₈..., v _RV is merged in the Bit data output of these 4 interleavers ₁, v ₂... v _RBit sequence.

Above-mentioned deinterleaving method can be handled for example contour contrast system of 32QAM, 64QAM or 256QAM.In step S12, adopting the data interlacing process of block interleaver is prior art.Fig. 3 A is the schematic diagram at the block interleaver of QPSK modulation, and Fig. 3 B is that Fig. 3 A and 3B all are parts of prior art at the schematic diagram of the block interleaver of 16QAM modulation.Be modulated to the data interlacing process that example (coming down to a block interleaver is example) illustrates block interleaver with QPSK below.Fig. 2 shows the flow process of the data interlacing process of block interleaver.Please be detailed description below simultaneously referring to Fig. 2 and Fig. 3 A to each step of data interleaving process.

Step S120: the bit sequence with an input writes in the matrix line by line, simultaneously dummy bits is filled into the relevant position of matrix.

Matrix is the matrix of R2 * 30, and promptly columns is 30, and each row of matrix are according to being 0,1,2 by left-to-right order number consecutively ..., 29.Matrix line number R2 is the smallest positive integral R2 that satisfies R≤R2 * 30, and each row of matrix is 0,1,2 according to order number consecutively from top to bottom ..., R2-1.Wherein R is the bit number of input bit sequence.

In the present embodiment with input bit sequence S ₁, S ₂..., S _RWrite in the matrix of R2 * 30 first bit y ₁Insert 0 row, 0 row:

$\left[\begin{array}{ccccc}{y}_1& y_2& {\mathrm{<figure-callout\; id="3"\; label="y"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">y</figure-callout>}}_3& \&CenterDot;\&CenterDot;\&CenterDot;& y_{30}\\ y_{31}& y_{32}& y_{33}& \&CenterDot;\&CenterDot;\&CenterDot;& y_{60}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& & \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& & \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& & \&CenterDot;\\ {\mathrm{<figure-callout\; id="30"\; label="y"\; filenames="A20081003576400161.png,A20081003576400162.png"\; state="\{\{state\}\}">y</figure-callout>}}_{30\&CenterDot;(R2-1)+1}& {\mathrm{<figure-callout\; id="30"\; label="y"\; filenames="A20081003576400161.png,A20081003576400162.png"\; state="\{\{state\}\}">y</figure-callout>}}_{30\&CenterDot;(R2-1)+2}& {\mathrm{<figure-callout\; id="30"\; label="y"\; filenames="A20081003576400161.png,A20081003576400162.png"\; state="\{\{state\}\}">y</figure-callout>}}_{30\&CenterDot;(R2-1)+3}& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{<figure-callout\; id="30"\; label="y"\; filenames="A20081003576400161.png,A20081003576400162.png"\; state="\{\{state\}\}">y</figure-callout>}}_{30\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2}\end{array}\right]$

Y wherein _k=S _k, k=1,2 ..., R, if R＜30 * R2 then uses dummy bits at position k=R+1, R+2 ..., fill among 30 * R2.These dummy bits need be deleted from matrix output after executing between follow-up row displacement.

Step S122: carry out between matrix column and replace.

Based on the pattern＜P2 in the last table (j)〉j ∈ 0,1 ..., 29} carries out between matrix column and replaces, and wherein P2 (j) is the initial column position of j permutating column.Bit note behind the column permutation is made y ' _k

$\left[\begin{array}{ccccc}{y^{\&prime;}}_1& {y^{\&prime;}}_{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2+1}& {y^{\&prime;}}_{2\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2+1}& \&CenterDot;\&CenterDot;\&CenterDot;& {y^{\&prime;}}_{29\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2+1}\\ {y^{\&prime;}}_2& {y^{\&prime;}}_{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2+2}& {y^{\&prime;}}_{2\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2+2}& \&CenterDot;\&CenterDot;\&CenterDot;& {y^{\&prime;}}_{29\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2+2}\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& & \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& & \&CenterDot;\\ \&CenterDot;& \&CenterDot;& \&CenterDot;& & \&CenterDot;\\ {y^{\&prime;}}_{R2}& {y^{\&prime;}}_{2\&CenterDot;R2}& {y^{\&prime;}}_{3\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2}& \&CenterDot;\&CenterDot;\&CenterDot;& {y^{\&prime;}}_{30\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A20081003576400162.png,A20081003576400163.png"\; state="\{\{state\}\}">R</figure-callout>}2}\end{array}\right]$

Step S124: read the output bit sequence of block interleaver the matrix between row after the displacement by row, the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

Read the output bit sequence of block interleaver the matrix of R2 * 30 between row after the displacement by row, the dummy bits of filling up before the displacement in the matrix input between row in the output need delete, i.e. corresponding bit y _k, the bit y ' of k＞R _kNeed deletion from output.Bit after interweave with the second time that the process time slot is correlated with is designated as v ₁, v ₂, v ₃... v _R, v wherein ₁Correspondence is deleted the bit y ' of backpointer k minimum _k, v ₂Correspondence is deleted the bit y ' that backpointer k second is little _k, by that analogy.

Above-mentioned at QPSK, for 16QAM, see also Fig. 3 B, second independently interleaver and first interleaver concurrent working.For these two interleavers, R2 need be chosen for the smallest positive integral that satisfies R≤60 * R2.The output bit that obtains from bit scramble operation according to bit to giving two interleavers respectively: bit s _kAnd s _K+1Be admitted to first interleaver, bit s _K+2And s _K+3Be admitted to second interleaver, wherein k mod 4=1.Bit after the interleaver output also according to bit to recombinating: bit v _kAnd v _K+1Obtain bit v from first interleaver _K+2And v _K+3Obtain from second interleaver, wherein k mod 4=1.

For Fig. 3 C, consider compatible existing HS-DSCH 16QAM deinterleaving method, multiplexing existing interleaver, the data of input are divided into 4 groups, every group of individual interleaving, adopt the interleaver parallel processing of 4 same interlace degree of depth, consider 4 interleavers, then total line number R2 of its interleaver is expressed as R2≤120 * R2, be divided into 4 the tunnel through the bit after the scrambling, first via bit is imported first interleaver, second interleaver of the second road bit input, the 3rd interleaver of Third Road bit input input, the four road bit is imported the 4th interleaver.Through after interweaving, the Bit data of first interleaver, second interleaver, the 3rd interleaver and the 4th interleaver is merged into a bit sequence.

Fig. 4 is the flow process of a preferred embodiment of the method for high order modulation HS-DSCH in the TD-SCDMA system HSDPA of the present invention.Seeing also Fig. 4, is the detailed description to each step in this method below.

Step S401: HS-DSCH is carried out interleaving treatment and the high order modulation that the multipling channel cataloged procedure comprises high order modulation.

HS-DSCH carries out the multipling channel cataloged procedure and sees also Fig. 5, comprises additional CRC, code block segmentation, and chnnel coding is mixed automatic repeat requests, bit scramble, high order modulation block interleaving, high-order modulation constellation rearrangement and physical channel mapping.

Additional CRC (CRC) is meant: in the TTI of each HS-DSCH, it is 24 CRC check bit that transmission block all needs to calculate with additional length, and obtaining exporting bit is b _Im1, b _Im2, b _Im3... b _ImB

Code block segmentation is meant: have only a transmission block on the HS-DSCH, input bit b _Im1, b _Im2, b _Im3... b _ImBDirectly mapping, the output bit is o _Ir1, o _Ir2, o _Ir3... o _IrK

Chnnel coding is meant: use 1/3 convolutional encoding to input bit o _Ir1, o _Ir2, o _Ir3... o _IrKEncode, obtain exporting bit c _I1, c _I2, c _I3... c _IE

Physical layer HARQ function is meant: the effect of HARQ function is that the total bit number on the HS-PDSCH of total bit number behind the coding and carrying HS-DSCH is complementary, and the HARQ function is controlled by redundancy versions (RV) parameter.Definite bit set of HARQ function output is decided by the input bit number, output bit number and RV parameter.The HARQ function comprises two leg speed rates coupling and a virtual bumper composition, and the output bit is w ₁, w ₂, w ₃... w _R

Bit scramble is meant: the method for the bit scramble method of HS-DSCH and the DCH of general service is identical.

The high order modulation block interleaving is meant: in the TDD system, all bits in the whole Transmission Time Interval are carried out the high order modulation block interleaving, carry out multiplexing to the parallel interleaver of 16QAM.Fig. 3 A has provided the deinterleaving method when HS-DSCH uses QPSK, and Fig. 3 B has provided the deinterleaving method when HS-DSCH uses 16QAM, and Fig. 3 C has provided the deinterleaving method when HS-DSCH uses high order modulation.

High-order modulation constellation rearrangement is meant: only at 16QAM, 32QAM, 64QAM and 256QAM high-order modulating, can be with reference to 3GPP, and for the QPSK modulation, this function is transparent.

The physical channel mapping is meant: data bit is mapped on the physical channel.

Wherein the data interlacing of high order modulation is described in detail in top embodiment, do not repeated them here.

Step 402: terminal receives HS-SCCH message, indicates the resource allocation conditions of next HS-DSCH (high speed descending sharing channel) transmission.

UE (terminal) receives HS-SCCH, HS-SCCH is separated physical process handle, and extracts the HS-DSCH control information, obtains a transmission block size indication information high position or low level and modulation system indication information, thereby obtains the high-order modulating of HS-DSCH.

Step 403: the deinterleaving processing that the demultiplexed channel decode procedure comprises high order modulation is measured and carried out to terminal accordingly.

UE receives HS-DSCH according to the control information of HS-SCCH on the time interval of distributing, the HS-DSCH data are carried out corresponding channel measurement, according to the transmission block of HS-SCCH size indication information and modulation system indication information the data on the HS-DSCH are carried out demodulation and demultiplexed channel decode procedure and comprise that the deinterleaving of high order modulation handles.Deinterleaving processing procedure and aforesaid interleaving treatment just in time are two opposite processes.

Step 404: according to HS-DSCH resource allocation conditions and measurement result, terminal produces a channel quality indication (CQI).

Step 405: the CQI of generation reports to NodeB (base station) at corresponding ascending control channel (HS-SICH).HS-DSCH deinterleaving method in the present embodiment is modified, and makes it be supported 32QAM, the contour contrast system of 64QAM or 256QAM.

Fig. 6 shows the principle of the HS-DSCH interlaced device of high order modulation in the TD-SCDMA system HSDPA of the present invention.See also Fig. 6, interlaced device comprises that input grouping module 600, interleaver group, the output be made up of jointly first interleaver 601, second interleaver 602, the 3rd interleaver 603 and the 4th interleaver 604 merge module 605.

Input grouping module 600 is divided into 4 groups of input bit data with the bit sequence of an input, wherein first group of input bit data enters first interleaver 601 and carries out interleaving treatment, obtain first group of output Bit data, second group of input bit data enters second interleaver 602 and carries out interleaving treatment, obtain second group of output Bit data, the 3rd group of input bit data enter the 3rd interleaver 603 and carry out interleaving treatment, obtain the 3rd group of output Bit data, the 4th group of input bit data enter the 4th interleaver 604 and carry out interleaving treatment, obtain the 4th group of output Bit data.These four groups output Bit datas merge the bit sequence of merging into an output in the module 605 in output.

The inside principle of first interleaver 601, second interleaver 602, the 3rd interleaver 603 and the 4th interleaver 604 all is prior aries.For each interleaver wherein, comprise permute unit 71 and matrix output unit 72 between matrix input unit 70, row.Wherein matrix input unit 70 is that the bit sequence that will import writes in the matrix line by line, is filled into the relevant position of matrix with dummy bits.Permute unit 71 is used to carry out replacement operator between matrix column between row.Matrix output unit 72 is read the output bit sequence by row the postrun matrix of permute unit between row, the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

Above-mentioned concrete ins and outs are described in detail in top embodiment, do not repeat them here.

The handled high order modulation of above-mentioned interlaced device comprises the high order modulation of 32QAM, 64QAM or 256QAM.

Inventive point of the present invention is multiplexing to existing interleaving mode, for example to multiplexing, multiplexing etc. to the 16QAM interleaving mode of QPSK interleaving mode.

The foregoing description provides to those of ordinary skills and realizes or use of the present invention; those of ordinary skills can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.

Claims (9)

1, the HS-DSCH deinterleaving method of high order modulation in a kind of TD-SCDMA system HSDPA comprises:

The bit sequence of an input is divided into n group Bit data, wherein n 〉=3;

Adopt n the identical interleaver of interleave depth that described n group Bit data is carried out parallel processing, the individual interleaving in the interleaver of correspondence of every group of Bit data wherein;

The bit sequence of an output is merged in the Bit data output of a described n interleaver.

2, the HS-DSCH deinterleaving method of high order modulation in the TD-SCDMA system HSDPA according to claim 1 is characterized in that, adopts the data interlacing process of block interleaver to comprise:

Line by line the input bit sequence is write in the matrix, dummy bits is filled into the relevant position of matrix;

Carry out between this matrix column and replace;

Read the output bit sequence of block interleaver the matrix between row after the displacement by row, the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

3, the HS-DSCH deinterleaving method of high order modulation in the TD-SCDMA system HSDPA according to claim 1 is characterized in that this deinterleaving method is handled the high order modulation of 32QAM, 64QAM or 256QAM.

4, the method for high order modulation HS-DSCH in a kind of TD-SCDMA system HSDPA comprises:

HS-DSCH is carried out the multipling channel cataloged procedure, and comprising the interleaving procedure to high order modulation, this interleaving procedure comprises:

The bit sequence of an input is divided into n group Bit data, wherein n 〉=3;

Adopt n the identical interleaver of interleave depth that described n group Bit data is carried out parallel processing, the individual interleaving in the interleaver of correspondence of every group of Bit data wherein;

The bit dateout of a described n interleaver is merged into the bit sequence of an output;

Terminal receives HS-SCCH message, indicates the resource allocation conditions of next HS-DSCH transmission;

Terminal is measured accordingly and is carried out the demultiplexing decode procedure, comprising with the described deinterleaving processing procedure opposite to the interleaving treatment of high order modulation;

According to HS-DSCH resource allocation conditions and measurement result, terminal produces a channel quality indication;

The channel quality indication that produces reports to the base station on corresponding ascending control channel.

5, the method for high order modulation HS-DSCH in the TD-SCDMA system HSDPA according to claim 4 is characterized in that, adopts the data interlacing process of block interleaver to comprise:

Line by line the input bit sequence is write in the matrix, dummy bits is filled into the relevant position of matrix;

Carry out between this matrix column and replace;

Read the output bit sequence of block interleaver the matrix between row after the displacement by row, the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

6, the method for high order modulation HS-DSCH in the TD-SCDMA system HSDPA according to claim 4 is characterized in that this high order modulation comprises the high order modulation of 32QAM, 64QAM or 256QAM.

7, the HS-DSCH interlaced device of high order modulation in a kind of TD-SCDMA system HSDPA comprises:

The input grouping module is divided into n group Bit data, wherein n 〉=3 with the bit sequence of an input;

The interleaver group comprises n the interleaver that interleave depth is identical, and each interleaver carries out parallel processing to one group of Bit data wherein, the individual interleaving in the interleaver of correspondence of every group of Bit data wherein;

Output merges module, the Bit data output of this n interleaver is merged into the bit sequence of an output.

8, the HS-DSCH interlaced device of high order modulation in the TD-SCDMA system HSDPA according to claim 7 is characterized in that this interleaver further comprises:

The matrix input unit, the bit sequence of input is write in the matrix line by line, is filled into the relevant position of matrix with dummy bits;

Permute unit between row is carried out replacement operator between matrix column;

The matrix output unit is read the output bit sequence by row the matrix between these row behind the permute unit, and the dummy bits of filling up before the displacement in the matrix input between row in the output need be deleted.

9, the HS-DSCH interlaced device of high order modulation in the TD-SCDMA system HSDPA according to claim 7 is characterized in that, the high order modulation that this device is handled comprises the high order modulation of 32QAM, 64QAM or 256QAM.

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