CN101556830A - Shift register and grid electrode driving device thereof - Google Patents
Shift register and grid electrode driving device thereof Download PDFInfo
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- CN101556830A CN101556830A CNA2008101037830A CN200810103783A CN101556830A CN 101556830 A CN101556830 A CN 101556830A CN A2008101037830 A CNA2008101037830 A CN A2008101037830A CN 200810103783 A CN200810103783 A CN 200810103783A CN 101556830 A CN101556830 A CN 101556830A
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Abstract
The invention relates to a shift register and a grid electrode driving device thereof. The shift register comprises six thin film transistors directly fabricated on an array substrate; a capacitor is arranged between the grid electrode and the source electrode of the first thin film transistor; the drain electrode of the first thin film transistor is connected with the output end of a first clock signal; the grid electrode of the second thin film transistor is connected with the grid electrode of the third thin film transistor; the grid electrode of the fourth thin film transistor is connected with the drain electrode thereof; the drain electrode of the fourth thin film transistor is connected with the output end of a shift initial signal or the output end of the preceding grade, and the source electrode of the fourth thin film transistor is connected with the grid electrode of the first thin film transistor; the grid electrode of the fifth thin film transistor is connected with the output end of the first clock signal; and the grid electrode of the sixth thin film transistor is connected with the output end of a second clock signal. The invention keeps the invalid state of the output end of the current grade, ensures that grid lines can not drift and can not be affected by other noise voltages connected with the grid lines and guarantees that the shift register is in a reliable invalid state and can not result in misoperation.
Description
Technical field
The present invention relates to the shift register and the gate drive apparatus thereof of a kind of shift register and gate drive apparatus thereof, particularly a kind of LCD.
Background technology
Characteristics such as that Thin Film Transistor-LCD (TFT-LCD) has is in light weight, thin thickness and power consumption are little are widely used in the devices such as mobile phone, display, televisor.
For display image, the matrix of lining by line scan that TFT-LCD arranges with m * n point shows.The TFT-LCD driver mainly comprises gate drivers and data driver, data driver latchs the video data and the clock signal timing of input in proper order, convert the data line that is input to liquid crystal panel after the simulating signal to, gate drivers is changed the clock signal of input by shift register, switch to unlatching/shutoff voltage, be applied in turn on the grid line of liquid crystal panel.In active matrix thin film transistor liquid crystal display (TFT-LCD) (AMTFT-LCD), the shift register in the gate drivers is used to produce the sweep signal of scanning grid line, and the shift register in the data driver is used to select the data line module.
In the prior art shift register, shift register is connected and composed by several grades (stage), and start signal is connected to input end in the first order, according to output signal at different levels, selects several grid lines in order.In the shift register work, require its all other times beyond effective (inable) state at different levels all to keep invalid (disable) state, but the prior art shift register makes grid line floating (floating), influenced by noise voltage, the at different levels of shift register can not keep disarmed state, and operation leads to errors.Fig. 4 is the structural representation of prior art shift register, comprise four thin film transistor (TFT)s, wherein the drain electrode of the first film transistor M1 connects clock signal output terminal CKV, capacitor C b is set between grid and the source electrode, source electrode is connected with the drain electrode of the second thin film transistor (TFT) M2, and is connected with output terminal OUTn at the corresponding levels; The source electrode of the second thin film transistor (TFT) M2 is connected with power supply negative terminal VSS, and grid is connected with the grid of the 3rd thin film transistor (TFT) M3, and is connected with next stage output terminal OUTn+1; The source electrode of the 3rd thin film transistor (TFT) M3 is connected with power supply negative terminal VSS, and drain electrode is connected with the grid of the first film transistor M1 and the source electrode of the 4th thin film transistor (TFT) M4 respectively; The drain electrode of the 4th thin film transistor (TFT) M4 is connected with its grid, and is connected with upper level output terminal OUTn-1.As shown in Figure 4, when the first film transistor M1 and the second thin film transistor (TFT) M2 were the disarmed state of closing, grid line can occur floating, therefore, the influence of other noise voltage that is subjected to linking to each other with grid line, shift register can not keep disarmed state, and the operation that leads to errors.
Prior art prevents faulty operation in order to keep shift register disarmed state at different levels, the general method that adopts the extra feed circuit of increase, but this method directly causes cost to rise.
Summary of the invention
The purpose of this invention is to provide a kind of shift register and gate drive apparatus thereof, effectively overcome technological deficiencies such as the existing floating operation that leads to errors of shift register grid.
To achieve these goals, the invention provides a kind of shift register, comprise six thin film transistor (TFT)s that directly are deposited on the array base palte, wherein six thin film transistor (TFT)s are respectively:
The first film transistor is provided with electric capacity between its grid and the source electrode, and its drain electrode is connected with first clock signal output terminal, and its source electrode is connected with output terminal at the corresponding levels;
Second thin film transistor (TFT), its grid is connected with the next stage output terminal, and its drain electrode is connected with output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal;
The 3rd thin film transistor (TFT), its grid are connected with the next stage output terminal with the grid of second thin film transistor (TFT) respectively, and its drain electrode is connected with the transistorized grid of the first film, and its source electrode is connected with power supply negative terminal;
The 4th thin film transistor (TFT), its grid is connected with its drain electrode, and its drain electrode is connected with displacement start signal output terminal or upper level output terminal, and its source electrode is connected with the drain electrode of transistorized grid of the first film and the 3rd thin film transistor (TFT) respectively;
The 5th thin film transistor (TFT), its grid is connected with first clock signal output terminal, and its drain electrode is connected with drain electrode with the grid of the 4th thin film transistor (TFT) respectively, and its source electrode is connected with output terminal at the corresponding levels;
The 6th thin film transistor (TFT), its grid is connected with the second clock signal output part, and its drain electrode is connected with output terminal at the corresponding levels with the source electrode of the 5th thin film transistor (TFT), and its source electrode is connected with power supply negative terminal VSS.
To achieve these goals, the present invention also provides a kind of gate drive apparatus, comprise displacement start signal output terminal and five shift registers, wherein five shift registers are connected with power supply negative terminal, first clock signal output terminal and second clock signal output part respectively, and in described five shift registers, first shift register is connected with displacement start signal output terminal, has first output terminal; Second shift register is connected with first output terminal of first shift register, and its second output terminal is connected with described first shift register; The 3rd shift register is connected with second output terminal of second shift register, and its 3rd output terminal is connected with described second shift register; The 4th shift register is connected with the 3rd output terminal of the 3rd shift register, and its 4th output terminal is connected with described the 3rd shift register; The 5th shift register is connected with the 4th output terminal of the 4th shift register, has the 5th output terminal.
The present invention proposes a kind of shift register and gate drive apparatus that directly is deposited on the array base palte, the high level of exporting successively by first clock signal output terminal and second clock signal output part has effectively kept the disarmed state of output terminal at the corresponding levels, grid line can not occur floating, the also influence of other noise voltage that can not be subjected to linking to each other with grid line, shift register keeps disarmed state reliably, and operation can not lead to errors.Adopt the technical scheme that increases extra feed circuit to compare with prior art in order to prevent faulty operation, the present invention need not increase extra feed circuit, has characteristics such as cost is low.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 a is the equivalent circuit diagram of a kind of structure of shift register of the present invention;
Fig. 1 b is the equivalent circuit diagram of the another kind of structure of shift register of the present invention;
Fig. 2 is the working timing figure of shift register of the present invention;
Fig. 3 is the structural representation of gate drive apparatus of the present invention;
Fig. 4 is the structural representation of prior art shift register.
Embodiment
Fig. 1 a is the equivalent circuit diagram of a kind of structure of shift register of the present invention, and Fig. 1 b is the equivalent circuit diagram of the another kind of structure of shift register of the present invention.As Fig. 1 a, shown in Fig. 1 b, the agent structure of shift register of the present invention comprises six thin film transistor (TFT)s and corresponding input/output terminal, six thin film transistor (TFT)s are respectively the first film transistor T 1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4, the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6, input/output terminal is respectively output terminal OUTn at the corresponding levels, upper level output terminal OUTn-1, next stage output terminal OUTn+1, the first clock signal output terminal CKV1, second clock signal output part CKV2, displacement start signal output terminal STV and power supply negative terminal VSS.
Particularly, capacitor C b is set between the grid of the first film transistor T 1 and the source electrode, its drain electrode is connected with the first clock signal output terminal CKV1, and its source electrode is connected with output terminal OUTn at the corresponding levels; The grid of the second thin film transistor (TFT) T2 is connected with the grid of the 3rd thin film transistor (TFT) T3, and connects next stage output terminal OUTn+1, and its drain electrode is connected with the source electrode of the first film transistor T 1, and connects output terminal OUTn at the corresponding levels, and its source electrode is connected with power supply negative terminal VSS; The grid of the 3rd thin film transistor (TFT) T3 is connected with the grid of the second thin film transistor (TFT) T2, and connection next stage output terminal OUTn+1, its drain electrode is connected with the grid of the first film transistor T 1 and the source electrode of the 4th thin film transistor (TFT) T4 respectively, and its source electrode is connected with power supply negative terminal VSS; The grid of the 4th thin film transistor (TFT) T4 is connected with its drain electrode, its drain electrode is connected with the drain electrode of the 5th thin film transistor (TFT) T5 respectively, and connecting displacement start signal output terminal STV or upper level output terminal OUTn-1, its source electrode is connected with the grid of the first film transistor T 1 and the drain electrode of the 3rd thin film transistor (TFT) T3 respectively; The grid of the 5th thin film transistor (TFT) T5 is connected with the first clock signal output terminal CKV1, and its drain electrode is connected with drain electrode with the grid of the 4th thin film transistor (TFT) T4 respectively, and its source electrode is connected with the drain electrode of the 6th thin film transistor (TFT) T6, and connects output terminal OUTn at the corresponding levels; The grid of the 6th thin film transistor (TFT) T6 is connected with second clock signal output part CKV2, and its drain electrode is connected with the source electrode of the 5th thin film transistor (TFT) T5, and connects output terminal OUTn at the corresponding levels, and its source electrode is connected with power supply negative terminal VSS.Because the above-mentioned thin film transistor (TFT) of the present invention directly is deposited on the array base palte, therefore above-mentioned source electrode is relative with drain electrode, corresponding source electrode can be arranged to drain electrode in actual the use, and corresponding drain electrode is arranged to source electrode.
Fig. 2 is the working timing figure of shift register of the present invention.As Fig. 1 a and shown in Figure 2, for the shift register that is positioned at first position, at first the first clock signal output terminal CKV1 exports high level (second clock signal output part CKV2 is a low level), because the grid of the 5th thin film transistor (TFT) T5 is connected with the first clock signal output terminal CKV1, so the 5th thin film transistor (TFT) T5 starts, the source electrode of the 5th thin film transistor (TFT) T5 and drain electrode conducting; Because the drain electrode of the 5th thin film transistor (TFT) T5 is connected with displacement start signal output terminal STV, the source electrode of the 5th thin film transistor (TFT) T5 is connected with output terminal OUTn at the corresponding levels, and the start signal output terminal STV that is shifted this moment is output as low level, so output terminal OUTn at the corresponding levels also is a low level, keep disarmed state.In this process, because next stage output terminal OUTn+1 is a low level, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are in cut-off state; Because second clock signal output part CKV2 is a low level, the 6th thin film transistor (TFT) T6 is in cut-off state.
The high level (the first clock signal output terminal CKV1 is a low level) of second clock signal output part CKV2 output subsequently, because the grid of the 6th thin film transistor (TFT) T6 is connected with second clock signal output part CKV2, so the 6th thin film transistor (TFT) T6 starts, the source electrode of the 6th thin film transistor (TFT) T6 and drain electrode conducting; Because the drain electrode of the 6th thin film transistor (TFT) T6 is connected with output terminal OUTn at the corresponding levels, the source electrode of the 6th thin film transistor (TFT) T6 is connected with power supply negative terminal VSS, so output terminal OUTn at the corresponding levels also is a low level, keeps disarmed state.In this process, displacement start signal output terminal STV is output as high level, because the grid of the 4th thin film transistor (TFT) T4 is connected with its drain electrode, so the 4th thin film transistor (TFT) T4 then starts, the source electrode of the 4th thin film transistor (TFT) T4 and drain electrode conducting, the source electrode of the 4th thin film transistor (TFT) T4 also is a high level, because this moment, output terminal OUTn at the corresponding levels was a low level, so be in source electrode and the charging of the capacitor C b between the low level output terminal OUTn at the corresponding levels of the 4th thin film transistor (TFT) T4 of high level.Because next stage output terminal OUTn+1 is a low level, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are in cut-off state.
The high level of first clock signal output terminal CKV1 output subsequently (second clock signal output part CKV2 and displacement start signal output terminal STV are low level), then the 5th thin film transistor (TFT) T5 is in conducting state, the 4th thin film transistor (TFT) T4 is in cut-off state, the electric charge of capacitor C b accumulation makes the grid of the first film transistor T 1 be in high level, 1 startup of the first film transistor T, the source electrode of the first film transistor T 1 is exported by output terminal OUTn at the corresponding levels with drain electrode conducting, the high level of first clock signal output terminal CKV1 output.In this process, because next stage output terminal OUTn+1 is a low level, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are in cut-off state; Because second clock signal output part CKV2 is a low level, the 6th thin film transistor (TFT) T6 is in cut-off state.
After this, displacement start signal output terminal STV is a low level always, second clock signal output part CKV2 exports high level (the first clock signal output terminal CKV1 is a low level), and the 6th thin film transistor (TFT) T6 starts, the source electrode of the 6th thin film transistor (TFT) T6 and drain electrode conducting; Because the drain electrode of the 6th thin film transistor (TFT) T6 is connected with output terminal OUTn at the corresponding levels, the source electrode of the 6th thin film transistor (TFT) T6 is connected with power supply negative terminal VSS, so output terminal OUTn at the corresponding levels also is a low level, keeps disarmed state.In this process, because next stage output terminal OUTn+1 is a high level, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are in conducting state, the source electrode of the second thin film transistor (TFT) T2 makes output terminal OUTn at the corresponding levels be connected with power supply negative terminal VSS with the drain electrode conducting, further guaranteed the low level of output terminal OUTn at the corresponding levels, the source electrode of the 3rd thin film transistor (TFT) T3 and drain electrode conducting make source electrode and the discharge of the capacitor C b between the low level output terminal OUTn at the corresponding levels of the 4th thin film transistor (TFT) T4.Therefore, no matter whether the first film transistor T 1 and the second thin film transistor (TFT) T2 are in and draw (pull-up) or drop-down (pull-down), and output terminal OUTn at the corresponding levels all keeps disarmed state.
For the shift register that is positioned at second position and later position thereof, its principle of work and aforementioned process are basic identical, different is, because the grid of the 4th thin film transistor (TFT) T4 is connected with upper level output terminal OUTn-1, when upper level output terminal OUTn-1 output high level, the 4th thin film transistor (TFT) T4 starts, make source electrode and the charging of the capacitor C b between the low level output terminal OUTn at the corresponding levels of the 4th thin film transistor (TFT) T4 that is in high level, and realize high level output at the corresponding levels constantly at the next one.
As Fig. 1 b, shown in Figure 2, at first the first clock signal output terminal CKV1 exports high level (second clock signal output part CKV2 is a low level), the 5th thin film transistor (TFT) T5 starts, its source electrode and drain electrode conducting, because the drain electrode of the 5th thin film transistor (TFT) T5 is connected with low level upper level output terminal, so output terminal at the corresponding levels also is a low level, keep disarmed state.In this process, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 6th thin film transistor (TFT) T6 are in cut-off state.
The high level (the first clock signal output terminal CKV1 is a low level) of second clock signal output part CKV2 output subsequently, the 6th thin film transistor (TFT) T6 starts, its source electrode and drain electrode conducting, because the source electrode of the 6th thin film transistor (TFT) T6 is connected with power supply negative terminal VSS, so output terminal at the corresponding levels also is a low level, keep disarmed state.In this process, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are in cut-off state.
Afterwards, the first clock signal output terminal CKV1 exports high level (second clock signal output part CKV2 is a low level), the 5th thin film transistor (TFT) T5 starts, its source electrode and drain electrode conducting, because upper level output terminal output this moment high level, and the drain electrode of the 5th thin film transistor (TFT) T5 is connected with the upper level output terminal, so the high level of upper level output terminal output is exported by output terminal at the corresponding levels.In this process, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 6th thin film transistor (TFT) T6 are in cut-off state.
After this, the upper level output terminal is a low level always, and second clock signal output part CKV2 exports high level (the first clock signal output terminal CKV1 is a low level), the 6th thin film transistor (TFT) T6 starts, its source electrode and drain electrode conducting, output terminal at the corresponding levels is a low level, keeps disarmed state.In this process, the second thin film transistor (TFT) T2 and the 3rd thin film transistor (TFT) T3 are in conducting state, have further guaranteed the low level of output terminal at the corresponding levels, make source electrode and the discharge of the capacitor C b between the low level output terminal at the corresponding levels of the 4th thin film transistor (TFT) T4 simultaneously.Therefore, no matter whether the first film transistor T 1 and the second thin film transistor (TFT) T2 are in and draw (pull-up) or drop-down (pull-down), and output terminal at the corresponding levels all keeps disarmed state.
The course of work of other displacement register can draw by structure shown in Fig. 1 b and working timing figure shown in Figure 2, repeats no more.
From technique scheme of the present invention as can be seen, the high level that shift register of the present invention is exported successively by the first clock signal output terminal CKV1 and second clock signal output part CKV2 has effectively kept the disarmed state of output terminal, grid line can not occur floating, the also influence of other noise voltage that can not be subjected to linking to each other with grid line, shift register keeps disarmed state reliably, and operation can not lead to errors.
Shift register of the present invention can be realized by 5 masking process or 4 masking process in the LCD (Liquid Crystal Display) array technology, by vacant part outside the substrate active region or substrate edges place alignment film transistor, then it directly is deposited on the array base palte.
Fig. 3 is the structural representation of gate drive apparatus of the present invention.As shown in Figure 3, the agent structure of gate drive apparatus comprises five shift registers, displacement start signal output terminal STV, the first clock signal output terminal CKV1, second clock signal output part CKV2 and power supply negative terminal VSS, each shift register respectively with power supply negative terminal VSS, the first clock signal output terminal CKV1 is connected with second clock signal output part CKV2, wherein each shift register is connected with power supply negative terminal VSS and is used to receive gate off voltage, each shift register is connected with second clock signal output part CKV2 with the first clock signal output terminal CKV1 and is used to receive first clock signal and second clock signal, further, the first shift register SFT1 is connected with the second output terminal OUT2 of the second shift register SFT2, be used to receive second output signal of the second shift register SFT2, the first output terminal OUT1 of the first shift register SFT1 is connected with the second shift register SFT2 simultaneously, is used for exporting first output signal to the second shift register SFT2.Two shift register SFT2 are connected with the 3rd output terminal OUT3 of the 3rd shift register SFT3, be used to receive the 3rd output signal of the 3rd shift register SFT3, the second output terminal OUT2 of the second shift register SFT2 is connected with the 3rd shift register SFT3 simultaneously, is used for exporting second output signal to the 3rd shift register SFT3.The 3rd shift register SFT3 is connected with the 4th output terminal OUT4 of the 4th shift register SFT4, be used to receive the 4th output signal of the 4th shift register SFT4, the 3rd output terminal OUT3 of the 3rd shift register SFT3 is connected with the 4th shift register SFT4 simultaneously, is used for exporting the 3rd output signal to the 4th shift register SFT4.The 4th shift register SFT4 is connected with the 5th output terminal OUT5 of the 5th shift register SFT5, be used to receive the 5th output signal of the 5th shift register SFT5, the 4th output terminal OUT4 of the 4th shift register SFT4 is connected with the 5th shift register SFT5 simultaneously, is used for exporting the 4th output signal to the 5th shift register SFT5.The 5th output terminal OUT5 of the 5th shift register SFT5 is connected with the 4th shift register SFT4, is used for exporting the 5th output signal to the 4th shift register SFT4.
Displacement start signal output terminal STV at first exports initial pulse, the first shift register SFT1 receives first clock signal and second clock signal from the first clock signal output terminal CKV1 and second clock signal output part CKV2 respectively afterwards, first clock signal is a high level pulse, the second clock signal is in the high level arteries and veins of and then first clock signal, have the present invention first shift register SFT1 work of structure shown in Fig. 1 a, the course of work repeats no more; The first output terminal OUT1 of the first shift register SFT1 is after the second shift register SFT2 exports first output signal, the second shift register SFT2 receives first clock signal and second clock signal from the first clock signal output terminal CKV1 and second clock signal output part CKV2 respectively, the second clock signal is a high level pulse, first clock signal is a high level pulse of second clock signal and then, the present invention second shift register SFT2 work with structure shown in Fig. 1 b, repeat above-mentioned flow process, just realized lining by line scan of LCD.
It should be noted that at last: above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (2)
1. a shift register is characterized in that, comprises six thin film transistor (TFT)s that directly are deposited on the array base palte, and wherein six thin film transistor (TFT)s are respectively:
The first film transistor is provided with electric capacity between its grid and the source electrode, and its drain electrode is connected with first clock signal output terminal, and its source electrode is connected with output terminal at the corresponding levels;
Second thin film transistor (TFT), its grid is connected with the next stage output terminal, and its drain electrode is connected with output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal;
The 3rd thin film transistor (TFT), its grid are connected with the next stage output terminal with the grid of second thin film transistor (TFT) respectively, and its drain electrode is connected with the transistorized grid of the first film, and its source electrode is connected with power supply negative terminal;
The 4th thin film transistor (TFT), its grid is connected with its drain electrode, and its drain electrode is connected with displacement start signal output terminal or upper level output terminal, and its source electrode is connected with the drain electrode of transistorized grid of the first film and the 3rd thin film transistor (TFT) respectively;
The 5th thin film transistor (TFT), its grid is connected with first clock signal output terminal, and its drain electrode is connected with drain electrode with the grid of the 4th thin film transistor (TFT) respectively, and its source electrode is connected with output terminal at the corresponding levels;
The 6th thin film transistor (TFT), its grid is connected with the second clock signal output part, and its drain electrode is connected with output terminal at the corresponding levels with the source electrode of the 5th thin film transistor (TFT), and its source electrode is connected with power supply negative terminal VSS.
2. gate drive apparatus that comprises the described shift register of claim 1, it is characterized in that, comprise displacement start signal output terminal and five shift registers, wherein five shift registers are connected with power supply negative terminal, first clock signal output terminal and second clock signal output part respectively, and in described five shift registers, first shift register is connected with displacement start signal output terminal, has first output terminal; Second shift register is connected with first output terminal of first shift register, and its second output terminal is connected with described first shift register; The 3rd shift register is connected with second output terminal of second shift register, and its 3rd output terminal is connected with described second shift register; The 4th shift register is connected with the 3rd output terminal of the 3rd shift register, and its 4th output terminal is connected with described the 3rd shift register; The 5th shift register is connected with the 4th output terminal of the 4th shift register, has the 5th output terminal.
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| KR100797522B1 (en) * | 2002-09-05 | 2008-01-24 | 삼성전자주식회사 | Shift register and liquid crystal display having the same |
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| CN100377258C (en) * | 2003-06-04 | 2008-03-26 | 友达光电股份有限公司 | shift register circuit |
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| CN102081969A (en) * | 2009-12-01 | 2011-06-01 | 群康科技(深圳)有限公司 | Shift register circuit and two-way transmission gate drive circuit |
| CN102081969B (en) * | 2009-12-01 | 2014-06-25 | 群康科技(深圳)有限公司 | Shift register circuit and two-way transmission gate drive circuit |
| CN102110420B (en) * | 2009-12-24 | 2013-07-10 | 北京京东方光电科技有限公司 | Array substrate and shift register arranged thereon |
| CN102568401A (en) * | 2010-12-21 | 2012-07-11 | 上海天马微电子有限公司 | Shift unit, shift device and liquid crystal display |
| CN102568401B (en) * | 2010-12-21 | 2015-02-18 | 上海天马微电子有限公司 | Shift unit, shift device and liquid crystal display |
| CN103646636A (en) * | 2013-12-18 | 2014-03-19 | 合肥京东方光电科技有限公司 | Shift register, grid drive circuit and display device |
| CN103646636B (en) * | 2013-12-18 | 2015-11-25 | 合肥京东方光电科技有限公司 | Shift register, gate driver circuit and display device |
| CN112885279A (en) * | 2021-01-22 | 2021-06-01 | 中山大学 | GOA circuit with protection transistor and control method thereof |
| CN112885279B (en) * | 2021-01-22 | 2022-04-22 | 中山大学 | GOA circuit with protection transistor and its control method |
| CN113808653A (en) * | 2021-09-07 | 2021-12-17 | 深圳知微创新技术有限公司 | Shift register unit circuit and shift register |
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|---|---|
| CN101556830B (en) | 2011-06-15 |
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