CN101548386B - Insulated gate field effect transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides an insulated gate field effect transistor and a method of manufacturing the same. When in useAn IGFET capable of being turned off when a reverse voltage is applied thereto, comprising: n is a radical of⁺A first drain region (6), N of the type^-A second drain region (7) of type, a first body region (8) of type P, and a P^-A second body region (9) of N-type, a first source region (10a) of N-type and a second body region of N-type⁺And a second source region (10b) of the type. A gate insulating film (5) and a gate electrode (4) are disposed in a trench (11) formed on a semiconductor substrate (1). A source (3) and a first source region (10a) of N-type and N⁺A second source region (10b) of the type ohmic-contacted with P^-The first body region (9) of type is in Schottky barrier contact.

Description

Insulated gate field effect transistor and manufacturing method thereof

technical field

The present invention relates to vertical insulated gate field effect transistors (hereinafter referred to as IGFETs) such as MOSFETs and methods of manufacturing the same. the

Background technique

A MOSFET, which is a type of IGFET with a large current capacity, is used as a switch of a circuit or the like. The source electrode of a typical MOSFET is in ohmic contact with the source region (sourceregion) and in ohmic contact with the body region (base region). Therefore, in addition to generating a current path between the drain electrode and the source through the channel of the body region, a parasitic diode or body diode or built-in diode based on the PN junction between the drain region and the body region is also generated. the current path. When the MOSFET is an N-channel type, when the potential of the drain is higher than the potential of the source, the parasitic diode is reverse-biased, and no current path is formed therethrough. However, depending on the requirements of circuits using MOSFETs, the potential of the drain may become lower than the potential of the source. In this case, the parasitic diode is forward biased and current flows here. When a MOSFET is used as a switch of an inverter circuit (DC-AC conversion circuit), it is very advantageous because a regenerative current can flow through a parasitic diode. the

However, there are also circuits that require blocking the current flow through the parasitic diode. In order to meet this requirement, it is known that an external diode having a polarity (direction) opposite to that of the parasitic diode can be connected in series with the MOSFET. Since this external diode functions as a reverse flow blocking diode, when the potential of the drain becomes lower than the potential of the source, current is prevented from flowing to the MOSFET. However, when the external diode is formed on the same semiconductor substrate as the MOSFET, the size of the semiconductor substrate inevitably increases and the cost of the semiconductor device increases. Also, when the external diode and the MOSFET are separately formed on different semiconductor substrates, the circuit combining the MOSFET and the external diode becomes large and expensive. Also, since the same current as the MOSFET flows through the external diode, power loss occurs here. Also, in the case of connecting an external diode in series with the MOSFET, when the potential of the drain is lower than that of the source, that is, when a reverse voltage is applied to the MOSFET, the current of the MOSFET cannot be controlled. the

In order to solve the problem caused by the external diode, Japanese Patent Application Laid-Open No. Hei 7-15009 (Patent Document 1) discloses a MOSFET having a planar structure in which the source and the body region are in Schottky contact. FIG. 1 shows a MOSFET with a planar structure according to the technical idea of Patent Document 1, and FIG. 2 shows an equivalent circuit of the MOSFET in FIG. 1 . the

The MOSFET with a planar structure shown in FIG. 1 includes a silicon semiconductor substrate 1', a drain 2', a source 3', a gate electrode 4', and a gate insulating film 5'. The semiconductor substrate 1' comprises: a first drain region 6' of high impurity concentration made of N ⁺ type semiconductor, a second drain region (or drift region) 7' of low impurity concentration made of N ^- type semiconductor, a P The first body region (or base region) 8' with high impurity concentration composed of P ^- type semiconductor, the second body region (or base region) 9' composed of P-type semiconductor with low impurity concentration, and the second body region (or base region) 9' composed of N ⁺ type semiconductor The source region 10' having a high impurity concentration has first and second main surfaces 1a', 1b' opposite to each other. The drain 2' is in ohmic contact with the first drain region 6' on the second main surface 1b', the source 3' is in ohmic contact with the N ⁺ type source region 10' on the first main surface 1a', and is in ohmic contact with the P ^- Type of the second body region 9' Schottky contact. The gate 4' faces the P-type first body region 8' and the P ^- type second body region 9' through the gate insulating film 5'.

When a voltage is applied between the drain/source in such a way that the potential of the drain 2' of FIG. 1 becomes higher than that of the source 3', and between the gate 4' and the source 3', the MOSFET can When the voltage is applied, as shown by the dotted line in Figure 1, an N-type channel 13' is formed on the surface of the first body region 8' and the second body region 9', and the leakage current is in the drain 2', the first drain region 6', the second drain region 7', the channel 13', the N ⁺ type source region 10' and the source 3'.

As shown in the equivalent circuit of FIG. 2 , besides the FET switch Q1 , the MOSFET of FIG. 1 also has first and second PN junction diodes D1 and D2 and a Schottky barrier diode D3 . The first diode D1 is a parasitic (built-in) diode based on the PN junction between the N ^- type second drain region 7' and the P-type first body region 8', and the second PN junction diode D2 is based on the ^P- A parasitic (built-in) diode of the PN junction between the second body region 9' of N+ type and the source region 10' of N ⁺ type. The Schottky barrier diode D3 is a diode based on the Schottky junction between the source 3' and the P ^- type second body region 9'. The first PN junction diode D1 has a reverse-biased polarity when the potential of the drain 2' is higher than the potential of the source 3', and is connected in antiparallel to the FET switch Q1. The second PN junction diode D2 has a polarity opposite to that of the first PN junction diode D1, and is connected in series with the first PN junction diode D1. In the conventional typical MOSFET that does not have the Schottky barrier diode D3, because the part of the Schottky barrier diode D3 is in a short-circuit state, the second PN junction diode D2 does not have any function, and in the equivalent circuit Not shown. The Schottky barrier diode D3 has a polarity opposite to that of the first PN junction diode D1, is connected in series with the first PN junction diode D1, and is connected in parallel with the second PN junction diode D2.

In the MOSFETs shown in Figures 1 and 2, when the potential of the drain 2' is higher than that of the source 3', the first PN junction diode D1 becomes reverse biased, and the Schottky barrier diode D3 becomes positive to a biased state and thus be able to perform the same work as a typical off-the-shelf MOSFET. Conversely, when the potential of the drain 2' is lower than the potential of the source 3', since the Schottky barrier diode D3 and the second PN junction diode D2 become reverse-biased, the flow through the MOSFET channel can be blocked. The reverse current of the part other than the track 11'. the

However, the conventional MOSFET of the planar structure in FIG. 1 has the following problems. the

(1) By the potential difference (about 0.2V) based on the Schottky barrier between the source electrode 3' and the P ^- type second body region 9', the potential change of the P ^- type second body region 9' be higher than the potential of the N ⁺ -type source region 10 ′. Therefore, when the potential of the drain 2' is higher than that of the source 3', electron injection from the N ⁺ -type source region 10' to the P ^- -type second body region 9' occurs. The current flowing between the drain 2' and the source 3' due to the injection of electrons becomes a leakage current. Since the withstand voltage between the drain and the source is determined based on the magnitude of the leakage current, when the above leakage current increases, the withstand voltage between the drain and the source will decrease.

(2) The aforementioned leakage current is suppressed by reducing the impurity concentration of the portion of the N ⁺ -type source region 10 ′ adjacent to the second body region 9 ′. Since the N ⁺ -type source region 10 ′ is formed by impurity diffusion, the N-type impurity concentration of the N ⁺ -type source region 10 ′ increases from the first main surface 1 a ′ toward the second main surface 1 b ′ of the semiconductor substrate 1 ′. Gradually decreases. Therefore, it is conceivable to lower the impurity concentration of the portion of the N ⁺ -type source region 10 ′ adjacent to the second body region 9 ′ by forming the N ⁺ -type source region 10 ′ deeply. However, when the N ⁺ type source region 10' is formed deeply, the first and second body regions 8', 9' must also be formed deeply. When the first and second body regions 8', 9' and the source region 10' are formed deeply, the lateral diffusion of P-type and N-type impurities occurs, and the surface area of the above-mentioned regions must increase, and the semiconductor substrate 1' The area (chip area) becomes, for example, approximately 1.7 times that of a conventional MOSFET having a typical planar structure that does not have a Schottky barrier diode, and miniaturization cannot be achieved. In addition, when the first and second body regions 8', 9' and the source region 10' are formed deeply, from the surface of the second drain region 7' exposed to the first main surface 1a' to the N ⁺ type The distance of the first drain region 6 ′ is, for example, approximately 1.5 times that of a conventional MOSFET having a typical planar structure that does not have a Schottky barrier diode. Thus, when the MOSFET with the planar structure of the Schottky barrier diode of FIG. The on-resistance of a typical planar MOSFET with a base barrier diode is, for example, approximately four times. Therefore, a MOSFET having a planar structure as shown in FIG. 1 has not been put into practical use.

Patent Document 1: Japanese Patent Application Publication No. Hei 7-15009

Contents of the invention

The problem to be solved by the present invention is the miniaturization of the IGFET in the form of schottky contact between the source and the body region and the problem that the on-resistance cannot be reduced. Therefore, an object of the present invention is to provide an IGFET capable of solving the above-mentioned problems. the

In order to solve the above problems, the present invention provides an insulated gate field effect transistor, which is characterized in that it has:

A semiconductor substrate having a first main surface and a second main surface extending parallel to the first main surface, and having at least one pair of grooves extending from the first main surface toward the second main surface ( trench);

The first drain region of the first conductivity type has a surface exposed on the second main surface of the semiconductor substrate, and has a thickness smaller than the interval between the second main surface and the trench;

The second drain region is adjacent to the first drain region, has a thickness equal to or greater than the interval between the first drain region and the trench, and has a first conductivity type impurity concentration lower than that of the first drain region;

The first body region of the second conductivity type is connected to the second drain region between the pair of trenches so that the second drain region is not exposed on the first main surface of the semiconductor substrate. configured adjacent to, and also adjacent to the aforementioned trench, and having a first impurity concentration;

The second body region of the second conductivity type is arranged between the pair of trenches, is adjacent to the first body region, and has a surface exposed on the first main surface of the semiconductor substrate, and having a second impurity concentration lower than the aforementioned first impurity concentration;

The source region of the first conductivity type is arranged between the pair of trenches, is adjacent to the second body region, is also adjacent to the trench, and has a exposed face;

a drain electrode in ohmic contact with the first drain region in the second main surface of the semiconductor substrate;

The source electrode is in ohmic contact with the above-mentioned source region in the above-mentioned first main surface of the above-mentioned semiconductor substrate, and is in Schottky contact with the above-mentioned second body region;

a gate insulating film formed on a wall surface of the aforementioned trench; and

The gate electrode is arranged in the trench and faces at least the channel-forming portion of the semiconductor substrate via the insulating film. the

Furthermore, it is preferable that the second drain region is adjacent to the trench. the

In addition, it is preferable that the source region is configured to include: a first source region adjacent to the second body region and also adjacent to the trench, and having a surface exposed on the first main surface of the semiconductor substrate; and a second source region. The second source region is adjacent to the first source region, has a higher impurity concentration than the first source region, and has a surface exposed on the first main surface of the semiconductor substrate. the

In addition, it is preferable that the thickness of the second drain region is smaller than the thickness from the first main surface of the semiconductor substrate to a PN junction between the second drain region and the first body region. the

In addition, it is preferable that the first body region has a first portion separated from the trench and a second portion adjacent to the trench, and the second portion has a second conductivity type impurity concentration higher than that of the first portion. high. the

In addition, it is preferable that the above-mentioned first and second body regions are regions where minority carrier lifetimes are shortened by irradiation with electron beams. the

In addition, it is preferable to further include: a gate control circuit for selectively supplying a gate control signal for bringing the drain and the source into a conduction state to the gate; When the potential of the drain is higher than that of the source, when the drain and the source are in a non-conductive state, the source and the gate are short-circuited; the second auxiliary switch unit is When the potential of the drain is lower than that of the source, when the drain and the source are brought into a non-conductive state, the drain and the gate are short-circuited. In addition, in this application, the gate control circuit, the first auxiliary switch unit, and the second auxiliary switch unit are regarded as a part of the insulated gate field effect transistor. the

In addition, in order to manufacture an insulated gate field effect transistor, preferably have the following steps:

A step of preparing a semiconductor substrate, wherein the semiconductor substrate has a first main surface and a second main surface facing each other, and has a first conductive type first surface arranged so as to be exposed on the second main surface. a drain region, a second drain region adjacent to the first drain region and having an impurity concentration of the first conductivity type lower than that of the first drain region, and a second drain region adjacent to the second drain region and also adjacent to the trench. Conductive type first body region;

A step of forming a trench, wherein the trench has a depth from the first main surface of the semiconductor substrate to the second drain region or into the second drain region; A step of forming a gate insulating film; a step of forming at least one pair of trenches having a depth from the first main surface of the semiconductor substrate to the second drain region or into the second drain region; Before or after the above-mentioned trench, the impurity of the first conductivity type is selectively diffused from the above-mentioned first main surface of the above-mentioned semiconductor substrate at a concentration within a range in which the conductivity type does not invert to form a second body region of the second conductivity type The process, wherein the second body region of the second conductivity type is adjacent to the first body region and has a lower impurity concentration of the second conductivity type than the first body region; before or after forming the trench, from the A step of selectively diffusing impurities of the first conductivity type on the first main surface of the semiconductor substrate to form a source region adjacent to the second body region; a step of forming a drain, wherein the drain is located on the second main body and a process of forming a source electrode, wherein the source electrode is in ohmic contact with the source region and in Schottky contact with the second body region on the first main surface. the

In addition, it is preferable that the source region includes: a first source region adjacent to the second body region and having the first conductivity type; a second source region adjacent to the first source region and having a surface, and has a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the above-mentioned first source region. the

In addition, it is preferable to further include: implanting ions of a second conductivity type impurity into the channel forming portion of the first body region through the trench, and forming a layer having a higher density than other portions on the channel forming portion of the first body region. The second conductivity type impurity concentration part of the process. the

Furthermore, it is preferable to further include a step of irradiating at least the first and second body regions with electron beams in order to shorten the lifetime of minority carriers in the first and second body regions. the

The effect of the invention

The insulated gate field effect transistor (IGFET) of the present invention has the following effects. the

(1) Since the channel is formed in the longitudinal direction along the trench, it is not necessary to expose the second drain region (drift region) on the first main surface on the source side of the semiconductor substrate. It is therefore not necessary to form the first body region by selective diffusion of impurities. As a result, the problem of excessive lateral expansion of the body region due to lateral diffusion of impurities during the selective diffusion of the body region (base region) of the conventional planar structure IGFET does not occur. Accordingly, it is possible to reduce the size of the IGFET. the

(2) Because it is a structure in which the second drain region (drift region) is not exposed on the first main surface of the semiconductor substrate between the paired trenches, the thickness of the second drain region can be made larger than that in FIG. The existing IGFET becomes smaller and the on-resistance of the IGFET can be reduced. That is, according to the present invention, the distance between the channel and the first drain region can be shortened, and the on-resistance of the IGFET can be reduced. the

Description of drawings

FIG. 1 is a cross-sectional view showing a conventional MOSFET. the

FIG. 2 is an equivalent circuit diagram of the MOSFET shown in FIG. 1 . the

Fig. 3 is a cross-sectional view showing an IGFET according to Embodiment 1 of the present invention. the

FIG. 4 is a plan view showing the first main surface of the third semiconductor substrate in FIG. 3 . the

FIG. 5 is a circuit diagram showing an equivalent circuit of the IGFET of FIG. 3 and a driving circuit thereof. the

FIG. 6 is a cross-sectional view showing the semiconductor substrate at the start of fabrication of the IGFET of FIG. 3 . the

FIG. 7 is a cross-sectional view showing a state where a P-type first body region is formed on the semiconductor substrate of FIG. 6 . the

FIG. 8 is a cross-sectional view showing a semiconductor substrate in which trenches are formed. the

9 is a cross-sectional view showing a semiconductor substrate in which a gate insulating film and a gate electrode are formed in a trench. the

FIG. 10 is a cross-sectional view showing a state where a P ^- -type second body region is formed on the semiconductor substrate of FIG. 9 .

11 is a cross-sectional view showing a state where an N-type first source region is formed on the semiconductor substrate of FIG. 10 . the

12 is a cross-sectional view showing a state where an N ⁺ -type second source region is formed on the semiconductor substrate of FIG. 11 .

Fig. 13 is a cross-sectional view showing an IGFET according to Embodiment 2 of the present invention. the

14 is a cross-sectional view for explaining a method of forming a P-type impurity-implanted region on a semiconductor substrate. the

15 is a cross-sectional view for explaining a method of irradiating an electron beam to a semiconductor substrate. the

Fig. 16 is a cross-sectional view showing an IGFET according to Embodiment 3 of the invention. the

FIG. 17 is a plan view showing a semiconductor substrate having grooves in a deformed pattern. the

FIG. 18 is a plan view showing a semiconductor substrate having grooves in another deformed pattern. the

Detailed ways

Embodiments of the present invention will be described below with reference to FIGS. 3 to 18 . In addition, in FIGS. 3-18, the part which has substantially the same function as FIG. 1 and FIG. 2 is attached|subjected with the same reference numeral. However, in order to distinguish between FIG. 1 and FIG. 3 , superscripts are added to the reference symbols in FIG. 1 , and subscripts are not added to the reference symbols in FIG. 3 . the

Example 1

The vertical IGFET of Embodiment 1 of the present invention shown in FIG. 3 , that is, the vertical IGFET, has: a semiconductor substrate 1 , a drain 2 , a source 3 , a gate 4 , and a gate insulating film 5 . The semiconductor substrate 1 can also be called a semiconductor chip, and has: a first drain region 6 with a high impurity concentration composed of an N ⁺ type silicon semiconductor; a second drain region 7 with a low impurity concentration composed of an N ⁻ type silicon semiconductor; The first body region (base region) 8 made of P ^- type silicon semiconductor; the second body region 9 of low impurity concentration made of P-type silicon semiconductor; the first source of relatively low impurity concentration made of N-type silicon semiconductor The region 10a, and the second source region 10b with high impurity concentration composed of N ⁺ type silicon semiconductor, also have: a trench (groove) 11 extending from the first main surface 1a of the semiconductor substrate 1 toward the second main surface 1b .

The first drain region 6 of N ⁺ type (first conductivity type) has a surface exposed on the second main surface 1b of the semiconductor substrate 1, and has a relatively high N-type impurity concentration (for example, 1×10 ¹⁹ cm ^{− 3} to 1×10 ²⁰ cm ^-3 ), and has a first thickness T1 smaller than the distance between the second main surface of the semiconductor substrate 1 and the trench 11 .

The N ^- type second drain region 7 is also called a drift region, it is arranged adjacent to the first drain region 6, and has a lower impurity concentration than that of the first drain region 6 in order to realize a high withstand voltage of the IGFET. (for example, 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁷ cm ^-3 ), and has a second thickness T2. The second thickness T2 is set to be greater than or equal to the distance T0 between the trench 11 and the first drain region 6 (greater than or equal to T0 ). The second drain region 7 is not exposed on the first main surface 1 a of the semiconductor substrate 1 between the pairs of trenches 11 facing each other.

Furthermore, in this embodiment, the second drain region 7 is not only not exposed on the first main surface 1a of the semiconductor substrate 1 between the paired trenches 11, but also on the first main surface 1a of the semiconductor substrate 1. The entire surface 1a is not exposed. However, as shown by the dashed-dotted line in FIG. 4, the second drain region 7 can be deformed so as to be in a portion other than between the paired trenches 11 of the main surface 1a of the semiconductor substrate 1, that is, to be in the Among the plurality of grooves 11 , the outermost grooves are exposed. In addition, the first and second body regions 8, 9, and the first and second Two source regions 10a, 10b. Carriers in the second drain region 7 having a low impurity concentration are accelerated by the electric field. Therefore, the second drain region 7 functions in the same manner as a known high-resistance collector region of a bipolar transistor. the

Each of the plurality of trenches 11 extends from the first main surface 1a of the semiconductor substrate 1 toward the second main surface 1b, and slightly penetrates into the N ⁻ -type second drain region 7 . The depth of the trench 11 is set from the first main surface 1a to the N ^- type second drain region 7, or from the first main surface 1a to the N ^- type second drain region 7 and the N ⁺ -type first drain region Between zone 6. Furthermore, the groove 11 extends perpendicularly with respect to the first and second main faces 1a, 1b which are parallel to each other. In this embodiment, the semiconductor substrate 1 has a plurality of IGFET units, and it can be clearly seen from FIG. 4 that a plurality of trenches 11 are provided to divide the plurality of IGFET units. FIG. 3 specifically shows a pair of trenches 11 and an IGFET cell between them.

The P-type first body region 8 can also be called a base region, which is arranged adjacent to the N-type second drain region 7 and also adjacent to the trench 5 . More specifically, the first body region 8 of this embodiment is formed by the overall diffusion of P-type impurities from the first main surface 1 a of the semiconductor substrate 1 . Therefore, the second drain region 7 covers the first body region 8 between all pairs of trenches 11 . Therefore, the second drain region 7 is not exposed on the first main surface 1 a of the semiconductor substrate 1 between the pair of trenches 11 . The first body region 8 is also formed outside (substrate outer peripheral side) of the plurality of trenches 11 of the semiconductor substrate 1 . However, it is also possible to selectively form the first body region 8 in such a manner that it is not provided partially or entirely outside the plurality of trenches 11 (substrate outer peripheral side) of the semiconductor substrate 1, and the first body region 8 may be formed outside the plurality of trenches 11. (Substrate Outer Perimeter Side) The second drain region 7 is exposed on the first main surface 1 a of the semiconductor substrate 1 . the

The PN junction 12 between the first body region 8 and the second drain region 7 extends parallel to the first and second main surfaces 1 a , 1 b of the semiconductor substrate 1 . A first PN junction diode D1 shown in FIG. 5 is formed through the PN junction 12 . The thickness from the first main surface 1 a of the semiconductor substrate 1 to the PN junction 12 is set to be thicker than the thickness T2 of the second drain region 7 . In other words, the thickness T2 of the second drain region 7 is thinner than the thickness from the first main surface 1 a of the semiconductor substrate 1 to the PN junction 12 . In this embodiment, since the first body region 8 is formed by the overall diffusion of P-type impurities from the first main surface 1a of the semiconductor substrate 1, the impurity concentration of the first body region 8 increases from the first main surface 1a side to It gradually decreases toward the second main surface 1b side. The P-type first body region 8 has a higher average impurity concentration (for example, 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ ) than the N ⁻ -type second drain region 7 . In addition, the average concentration of P-type impurities in the first body region 8 is determined to be a value capable of generating the N-type channel 13 shown by the dotted line when a gate voltage is applied to the gate 4 .

The P ^- type second body region 9, which can also be called a second base region, adjoins the first body region 8 and also adjoins the trench 11, and has a face.

The source electrode 3 is in Schottky contact with the exposed surface of the P ^- type second body region 9 . Therefore, a Schottky barrier diode (SBD) D3 shown in FIG. 5 is formed by both. In order to make the Schottky barrier diode D3 have a reverse breakdown voltage of 10 V or more, the surface impurity concentration of the second body region 9 is determined to be lower than the surface impurity concentration of the first body region 8 (for example, 1×10 ¹⁶ cm ^-3 or less).

The N-type first source region 10 a adjoins the P ⁻ -type second body region 9 and also the trench 11 , and has an area exposed on the first main surface 1 a of the semiconductor substrate 1 . Since the first source region 10a is a region formed by selective diffusion of N-type impurities, the concentration of N-type impurities decreases corresponding to the diffusion depth. A PN junction 14 is formed between the N-type first source region 10 a and the P-type second body region 9 . This PN junction 14 provides a second PN junction diode D2 shown in FIG. 5 . The second PN junction diode D2 is formed to have the same or higher reverse breakdown voltage as the Schottky barrier diode D3. Therefore, the N-type impurity concentration of the N-type first source region 10a is determined to be a value capable of obtaining the reverse withstand voltage required by the second PN junction diode D2 (for example, 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ ).

The N ⁺ -type second source region 10 b is adjacent to the first source region 10 a and also adjacent to the trench 11 , and has a surface exposed on the first main surface 1 a of the semiconductor substrate 1 . The N-type impurity concentration of the second source region 10b is determined to be higher than the N-type impurity concentration of the first source region 10a (for example, 1×10 ¹⁸ cm ⁻³ to 1×10 ²⁰ cm ⁻³ ).

The source electrode 3 is arranged on the main surface 1 a of the semiconductor substrate 1 , is in ohmic contact with the first and second source regions 10 a and 10 b , and is in Schottky contact with the second body region 9 . The source 3 is made of, for example, metal such as Al or Ti, or silicide, and is connected to a source terminal S shown illustratively. the

The drain 2 is made of metal such as Al, is in ohmic contact with the N ⁺ -type first drain region 6 on the second main surface 1 b of the semiconductor substrate 1 , and is connected to a drain terminal D shown illustratively.

The gate insulating film 5 is made of a silicon oxide film and is formed on the wall surface of the trench 11 . The gate 4 is made of polysilicon doped with impurities filled in the trench 11 . Since polysilicon doped with impurities has conductivity, it functions as the gate 4 similarly to metal. It is of course also possible to form the gate 4 from metal. Although polysilicon is not a metal in the narrow sense, it has the same function as metal equivalently. Therefore, an IGFET with a gate structure made of polysilicon can also be called a MOSFET. In FIG. 3 , an insulating layer 15 is disposed between the source 3 and the gate 4 to electrically separate them. The gate 4 is electrically connected to a gate terminal G shown illustratively. The gate 4 is connected to the gate terminal G using a part of the first main surface 1 a of the semiconductor substrate 1 not covered by the source 3 . the

FIG. 5 schematically shows a circuit composed of IGFETs and the control circuit. The equivalent circuit of the IGFET of FIG. 3 shown in FIG. 5 is the same as the IGFET shown in FIG. 2 with the existing Schottky barrier diode, which includes: FET switch Q1; Health diode) D1, D2; Schottky barrier diode (parasitic diode) D3. The first PN junction diode D1 is connected between the drain terminal D and the source terminal S to have reverse polarity, the second PN junction diode D2 and the Schottky barrier diode D3 are connected between the drain terminal D and the source terminal S They are connected through the first PN junction diode D1 and have forward polarity. the

In order to drive the IGFET, the first DC power supply +E and the second DC power supply -E are provided, the positive terminal of the first DC power supply +E is connected to the drain terminal D via the first switch S1, and the negative terminal is connected to the source terminal via the load L Sub-S connection. In addition, the positive terminal of the second DC power supply-E is connected to the source terminal S via the second switch S2 and the load L, and the negative terminal is connected to the drain terminal D. Therefore, when the first switch S1 is turned on, a forward voltage in which the potential of the drain terminal D becomes higher than that of the source terminal S is applied to the IGFET, and when the second switch S2 is turned on, the source terminal S is applied to the IGFET. A reverse voltage at which the potential of S becomes higher than the potential of the drain terminal D. Furthermore, parts of the first and second DC power sources +E, -E and the first and second switches S1, S2 can also be replaced with AC power sources or bidirectional voltage generating circuits. the

Between the source terminal S and the gate terminal G, a gate control circuit 20 is connected. The gate control circuit 20 is composed of a gate control power supply Eg and a gate switch Sg. The gate switch Sg is formed of, for example, a transistor, and the voltage of the gate control power supply Eg is applied to the gate terminal G when it is turned on. In addition, when the voltage amplitude of the gate control power supply Eg varies, the leakage current of the IGFET varies. the

The IGFET control circuit of FIG. 5 has first and second auxiliary switches Sa and Sb in order to realize bidirectional on/off operation (AC switching operation) and bidirectional current control operation of the IGFET. The first auxiliary switch Sa is connected between the source terminal S and the gate terminal G. The second auxiliary switch Sb is connected between the gate terminal G and the drain terminal D. Although the first and second auxiliary switches Sa and Sb are shown as mechanical switches, they are preferably composed of controllable electronic switches such as transistors. the

When the first switch S1 is controlled to be in the on state and the voltage of the first DC power supply +E is applied between the drain terminal D and the source terminal S, while the gate switch Sg is turned off, the first auxiliary switch Sa is conduction controlled. When the first auxiliary switch Sa is turned on, the source terminal S and the gate terminal G are short-circuited, and the gate terminal G and the source terminal S become the same potential, which can be reliably closed or eliminated. The channel 13 indicated by the dotted line reliably cuts off the leakage current. Therefore, the withstand voltage of the IGFET while the forward voltage is applied between the drain and the source is substantially equal to the withstand voltage of the first PN junction diode D1. the

By turning on the second switch S2, a reverse voltage is applied between the drain terminal D and the source terminal S of the IGFET, and when the control switch Sg is turned off, the second auxiliary switch Sb is turned on. , the drain terminal D and the gate terminal G are short-circuited through the second auxiliary switch Sb. When a reverse voltage is applied between the drain and the source of the IGFET in this way, when the second auxiliary switch Sb is turned on, the gate terminal G becomes the same negative potential as the drain terminal D, and the channel 11 can be closed without Leakage current flows. The withstand voltage of the IGFET when a reverse voltage is applied between the drain and the source of the IGFET and the channel 11 is closed is determined according to the withstand voltages of the second PN junction diode D2 and the Schottky barrier diode D3. the

When both the first and second auxiliary switches Sa and Sb are turned off, any In both cases, the width of the channel 11 , that is, the leakage current can be controlled by the control signal of the gate control circuit 20 . That is, by changing the voltage amplitude of the gate power supply Eg, the magnitude of the leakage current can be changed. the

In FIG. 5, the gate control circuit 20 has a gate switch Sg, but the gate switch Sg can be omitted, and the gate power supply (gate signal source) Eg is always connected between the source terminal S and the gate terminal G. between. In this way, in the state where the gate power supply (gate signal source) Eg is always connected between the gate/source, when a forward voltage is applied from the first DC power supply +E to the drain/source of the IGFET, when the first When the auxiliary switch Sa is turned on, the gate/source is short-circuited and the gate and source are at the same negative potential, so the IGFET is turned off. And when a reverse voltage is applied from the second DC power supply +E to the drain/source of the IGFET, when the second auxiliary switch Sb is turned on, the drain/gate is short-circuited and the gate terminal becomes a negative potential, so the IGFET becomes disconnected. Therefore, the IGFET can be used as a bidirectional switch. the

An example of a method of manufacturing the IGFET shown in FIGS. 3 and 4 will be described with reference to FIGS. 6 to 12 . Note that, for convenience of description, the same reference numerals are assigned to the pre-completion semiconductor region and the post-completion semiconductor region of the semiconductor substrate 1 in FIGS. 6 to 11 . the

First, prepare a silicon semiconductor substrate 1 as shown in FIG. 6, and this silicon semiconductor substrate 1 has: a first drain region 6 made of an N ⁺ type semiconductor of FIG. 3 and a second drain region 7 made of an N ^- type semiconductor . N ⁺ -type first drain region 6 is formed by diffusion of N-type impurities from the second main surface of semiconductor substrate 1 . However, the N ⁺ -type first drain region 6 may also be formed by epitaxial growth.

Next, by diffusing P-type impurities such as boron from first main surface 1a of semiconductor substrate 1, first body region 8 adjacent to N ^- type second drain region 7 is formed as shown in FIG. The formation of the second drain region 7 is not a selective diffusion, but a non-selective diffusion from the entire first main surface 1a of the semiconductor substrate 1, so the PN junction 12 is parallel to the first and second main surfaces 1a, 1b. Furthermore, the first body region 8 may also be formed by an epitaxial growth method.

Next, trench 11 is formed by performing known anisotropic etching from the first main surface 1 a side of semiconductor substrate 1 . The trench 11 is formed to reach the N ^- type second drain region 7 . Furthermore, the process of forming trench 11 can be shifted to after forming second body region 9 in FIG. 10 , or after forming first source region 10 a in FIG. 11 , or after forming second source region 10 b in FIG. 12 .

Next, a thermal oxidation treatment is performed on the silicon semiconductor substrate 1. As shown in FIG. The gate 4 is made of polysilicon. In addition, although the upper surface of the gate electrode 4 coincides with the first main surface 1a of the semiconductor substrate 1 in FIG. 9, it may be lower or higher than the first main surface 1a. the

Next, N-type impurities such as phosphorus are diffused from the surface of the P-type first body region 8, that is, the first main surface 1a of the semiconductor substrate 1, at a concentration such that the conductivity type does not invert, and a P-type impurity is formed as shown in FIG. 10 . ^-Type II body region 9. The diffusion of the N-type impurity offsets the P-type impurity in the P-type first body region 8 to obtain the second body region 9 with a P-type impurity concentration lower than that of the first body region 8 .

Next, N-type impurities such as phosphorus are selectively diffused in the second body region 9 to form the N-type first source region 10 a shown in FIG. 11 . By forming the first source region 10a, the diffusion depth of the P ^- type second body region 9 is locally further deepened, and the boundary between the P-type first body region 8 and the P ^- type second body region 9 becomes non-flat .

Next, N-type impurities such as arsenic are selectively diffused in the first source region 10a to form an N ⁺ -type second source region 10b shown in FIG. 12 .

Then, insulating layer 15, drain 2, and source 3 shown in FIG. 3 are formed to complete the IGFET. the

Embodiment 1 has the following effects. the

(1) Since the Schottky barrier diode D3 having the opposite polarity (directionality) to the first PN junction diode D1 is formed, when the potential of the source 3 is higher than that of the drain 2, the Current passing through the portion of the semiconductor substrate 1 other than the channel 13. the

(2) The current control of the channel 13 using the voltage between the gate and the source can be performed in both cases while the potential of the source 3 is lower or higher than the potential of the drain 2 . the

(3) The second drain region 7 is not exposed on the first main surface 1 a of the semiconductor substrate 1 . Therefore, although the P ^- type second body region 9 used to obtain the Schottky barrier diode D3 is formed, and the second body region 9 with low impurity concentration is set in order to suppress the NPN parasitic transistor action based on the source region, the body region and the drain region a source region 10a, but the distance from the lower end of the channel 13 to the N ⁺ -type first drain region 6 (the thickness of the N ^- -type second drain region 7 ) does not particularly increase. In other words, in FIG. 3, regardless of whether there is a P ^- type second body region 9 and a first source region 10a, the thickness T2 of the N ^- type second drain region 7 can be kept at a smaller fixed value (for example, 1.4 μm). This does not lead to an increase in the on-resistance of the IGFET. For example, when it is assumed ^that the distance from the first main surface 1a' of ^FIG . When the distance is 5.5 μm, the on-resistance of the IGFET with a withstand voltage of about 40 V in this embodiment shown in FIG. 3 becomes about 1/4 of that of the conventional planar IGFET shown in FIG.

(4) By setting the N-type first source region 10a having an N-type impurity concentration lower than that of the N ⁺ -type second source region 10b, and the area of the PN junction 12 is reduced compared with the conventional structure of FIG. 1 , thereby The possibility of turning on the NPN parasitic transistor including the N ^- type drain region 7, the P-type first body region 8, the P ^- type second body region 9, and the N-type first source region 10a is reduced. If the parasitic transistor turns on, the IGFET may be damaged. In addition, even if it is a current that does not damage the IGFET, the current flowing through the parasitic transistor is a leakage current, which reduces the withstand voltage of the IGFET.

(5) The P-type first body region 8 is formed by non-selective diffusion, and the lateral extension to the N-type first source region 10a and the N ⁺ -type second source region 10b is restricted by the trench 11, Therefore, the lateral width of the IGFET is, for example, 4 μm, which is significantly narrower than the value (for example, 14 μm) of the conventional planar structure of FIG. 1 . Compared with the conventional IGFET of FIG. The area of the main surface 1a is reduced by 30 to 40%.

(6) As shown in FIG. 5, using the first and second auxiliary switches Sa, Sb can obtain the off state when a forward voltage is applied to the IGFET, and the off state when a reverse voltage is applied to the IGFET, and when the first When the gate switch Sg is kept turned on while the second auxiliary switches Sa and Sb are kept turned off, the IGFET can be turned on both when a forward voltage is applied and when a reverse voltage is applied. pass status. Therefore, the IGFET can be used as a bidirectional switch (AC switch). the

Example 2

Next, the IGFET of the second embodiment will be described with reference to FIGS. 13 to 15 . However, in FIGS. 13 to 15 , the parts substantially the same as those in FIGS. 3 to 12 are denoted by the same reference numerals and description thereof will be omitted. the

The IGFET of FIG. 13 is formed by implanting P-type impurities along the trench 11 of FIG. The first part 9a in the center of the body region 9 has a second part 9b with a higher impurity concentration, and at least the first and second body regions 8, 9 are subjected to electron beam irradiation treatment. The IGFET case is different, but otherwise the same as Figure 3. the

The second parts 8b, 9b of the first and second body regions 8, 9 formed by P-type impurity implantation are used to increase the threshold value (threshold voltage Vth) of the IGFET. The outer side, that is, the portion where the trench 13 is formed along the trench 11 is formed, and has a higher impurity concentration than the first portions 8a, 9a. In FIG. 13, the second portion 8b is formed in a manner corresponding to the entire length of the channel 13 of the first body region 8, but instead, it may be formed only locally on the upper side of the first body region 8 (a part of the channel 13). ) formed on. In addition, in FIG. 13, the second portion 9b is formed to correspond to the entire length of the channel 13 of the second body region 9, but instead, it may be formed only in a part of the second body region 9, or may not be formed. The second part 9b. the

When assuming that the P ^- type second body region 9 is not set, the impurity concentration of the P-type first body region 8 formed by impurity diffusion is from the N-type first source region 10a side toward the N ^- type second drain Zone 7 gradually decreases. Therefore, it is difficult to form a channel in the portion where the impurity concentration of the adjacent N-type first source region 10a of the P-type first body region 8 is high, and the result is different from that in which the P ^- type second body region of FIG. 9 has a higher threshold voltage Vth than the case of 9. Depending on the circuit, a higher threshold voltage Vth may be required. Therefore, in Embodiment 2 of FIG. 13 , P-type impurities are limitedly implanted from the trench 11 to form second portions 8 b and 9 b with higher impurity concentrations on the first and second body regions 8 and 9 . When the second portions 8b, 9b having a higher impurity concentration are formed, a higher threshold voltage Vth (for example, about 1 V higher than that of the IGFET in FIG. 3 ) can be obtained than when the second portions 8b, 9b are not formed. In addition, since the second portions 8b, 9b are formed in a limited manner, they hardly affect the breakdown voltage and on-resistance of the IGFET.

When forming the P-type impurity implantation region 31, as shown in FIG. The insulating film 5 is punched in a required amount, and then thermally diffused in the semiconductor substrate 1 . As a result, P-type impurity implanted region 31 is locally formed along the wall surface of trench 11 . Through the subsequent diffusion process, the second parts 8b, 9b of the first and second body regions 8, 9 shown in Fig. 13 are finally obtained. the

On the semiconductor substrate 1 of the IGFET of the second embodiment shown in FIG. 13, as shown by the arrow 32 in FIG. Heat treatment at a predetermined temperature (for example, 300° C. or higher) is carried out in the middle. This heat treatment is for recovering the damage generated at the interface of Si (silicon) and SiO2 (silicon oxide) by electron beam irradiation. When an electron beam is irradiated, the lifetime of minority carriers on the first and second body regions 8, 9 is shortened. When the lifetime is shortened like this, when a reverse voltage is applied to the IGFET, the electrons (minority carriers) and holes injected into the first and second body regions 8, 9 from the N ^- type second drain region 7 rapidly Combined, its flow to the N-type first source region 10a is suppressed. This reduces the leakage current of the IGFET and improves the breakdown voltage. For example, when the lifetime of the minority carriers on the first and second body regions 8, 9 becomes 1/10, the withstand voltage is improved from 15V to 21V.

In Example 2, the entire semiconductor substrate 1 is irradiated with electron beams, but partial irradiation may also be performed. Furthermore, lifetime inhibitors such as gold can also be distributed in the first and second bulk regions 8 , 9 . the

Embodiment 2 also has the same effect as Embodiment 1 except for the effect of raising the threshold voltage Vth and the effect of shortening the lifetime described above. the

Example 3

The IGFET of Example 3 shown in FIG. 16 is formed in the same manner as the IGFET of FIG. 3 except that the p ^- type second body region 9 of FIG. 3 is changed to a deformed second body region 9c. In FIG. 16 , the P ⁻ -type second body region 9 c is provided only in the vicinity of the first main surface 1 a of the semiconductor substrate 1 , and does not adjoin the trench 11 . The P ^- type second body region 9c is used to form a Schottky barrier diode along with the source 3. As shown in FIG. The same effect as that of the IGFET of FIG. 3 can be obtained. Furthermore, on the first body region 8 of the IGFET in the third embodiment of FIG. 16, a structure corresponding to the second portion 8b shown in FIG. and the lifetime of the minority carriers on the second body region 8, 9c.

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible. the

(1) As shown in FIG. 17, the linear groove 11 of ^FIG . a first source region 10a', an N ⁺ -type second source region 10b', and the like. In the case of the grid-shaped groove 11a of FIG. 17, the first and second parts 11a1, 11a2 facing each other, or the third and fourth parts facing each other on one quadrangular part included in the grid-like groove 11a Portions 11a3, 11a4 are pairs of trenches constituting unit IGFET cells.

(2) As shown in FIG. 18, the linear trench 11 shown in ^FIG . A source region 10a'' and a second body region 9e of P ^- type.

(3) Instead of forming the N-type first source region 10a and the N ⁺ -type second source region 10b through two impurity diffusions, it is possible to form the first main surface of the semiconductor substrate 1 through one impurity diffusion. A single source region with a high N-type impurity concentration in the vicinity of 1 a and a low N-type impurity concentration in the vicinity of the PN junction 14 .

Claims (11)

1. An insulated gate field effect transistor, characterized in that, possesses: A semiconductor substrate having a first main surface and a second main surface extending parallel to the first main surface, and having at least one pair of grooves extending from the first main surface toward the second main surface; The first drain region of the first conductivity type has a surface exposed on the second main surface of the semiconductor substrate, and has a thickness smaller than the distance between the second main surface and the trench; The second drain region is adjacent to the first drain region, has a thickness greater than the interval between the first drain region and the trench, and has a first conductivity type impurity concentration lower than that of the first drain region; The first body region of the second conductivity type is connected to the second drain region between the pair of trenches so that the second drain region is not exposed on the first main surface of the semiconductor substrate. disposed adjacently, and also adjacent to the aforementioned trench, and having a first impurity concentration; The second body region of the second conductivity type is arranged between the pair of trenches, is adjacent to the first body region, and has a surface exposed on the first main surface of the semiconductor substrate, and having a second impurity concentration lower than the aforementioned first impurity concentration; The source region of the first conductivity type is arranged between the pair of trenches, is adjacent to the second body region, is also adjacent to the trench, and has a exposed face; a drain electrode in ohmic contact with the first drain region in the second main surface of the semiconductor substrate; a source electrode in ohmic contact with the source region in the first main surface of the semiconductor substrate and in Schottky contact with the second body region; a gate insulating film formed on a wall surface of the aforementioned trench; and The gate electrode is arranged in the trench and faces at least the channel-forming portion of the semiconductor substrate via the insulating film. 2. The insulated gate field effect transistor according to claim 1, characterized in that, The second drain region is adjacent to the trench. 3. The insulated gate field effect transistor according to claim 1, wherein: The source region is configured to include: a first source region adjacent to the second body region and also adjacent to the trench, and having a surface exposed on the first main surface of the semiconductor substrate; and a second source region. , is adjacent to the first source region and has a higher impurity concentration than the first source region, and has a surface exposed on the first main surface of the semiconductor substrate. 4. The insulated gate field effect transistor according to claim 1, wherein: A thickness of the second drain region is smaller than a thickness from the first main surface of the semiconductor substrate to a PN junction between the second drain region and the first body region. 5. The insulated gate field effect transistor according to claim 1, characterized in that, The first body region has a first portion separated from the trench and a second portion adjacent to the trench, the second portion having a higher second conductivity type impurity concentration than the first portion. 6. The insulated gate field effect transistor according to claim 1, wherein: The above-mentioned first and second body regions are regions where the lifetime of minority carriers is shortened by electron beam irradiation. 7. The insulated gate field effect transistor according to claim 1, further comprising: a gate control circuit for selectively supplying a gate control signal for bringing the drain and the source into a conduction state to the gate; The first auxiliary switch unit short-circuits between the source and the gate when the drain and the source are in a non-conductive state during a period in which the potential of the drain is higher than that of the source; The second auxiliary switching means short-circuits between the drain and the gate while bringing the drain and the source into a non-conductive state while the potential of the drain is lower than that of the source. 8. A method for manufacturing an insulated gate field effect transistor, characterized in that it has: A step of preparing a semiconductor substrate, wherein the semiconductor substrate has a first main surface and a second main surface facing each other, and has a first conductive type first surface arranged so as to be exposed on the second main surface. a drain region, a second drain region adjacent to the first drain region and having an impurity concentration of the first conductivity type lower than that of the first drain region, and a first body region of the second conductivity type disposed adjacent to the second drain region ; A step of forming at least one pair of trenches, wherein the pair of trenches has a depth from the first main surface of the semiconductor substrate to the second drain region or into the second drain region; A step of forming a gate insulating film on the side surfaces of the trench; A step of forming a gate in the trench, wherein the gate is opposed to a channel forming portion of the semiconductor substrate via the gate insulating film; Before or after forming the above-mentioned trenches, impurities of the first conductivity type are selectively diffused from the above-mentioned first main surface of the above-mentioned semiconductor substrate at a concentration within a range in which the conductivity type does not invert to form a second conductive type impurity. the process of the body region, wherein the second body region of the second conductivity type is adjacent to the first body region and has an impurity concentration of the second conductivity type lower than that of the first body region; Before or after forming the trench, selectively diffusing impurities of the first conductivity type from the first main surface of the semiconductor substrate to form a source region adjacent to the second body region; A step of forming a drain, wherein the drain is in ohmic contact with the first drain region on the second main surface; and A step of forming a source electrode, wherein the source electrode is in ohmic contact with the source region and in Schottky contact with the second body region on the first main surface. 9. The method for manufacturing an insulated gate field effect transistor according to claim 8, wherein: The source region includes: a first source region adjacent to the second body region and having the first conductivity type; and a second source region adjacent to the first source region and having a surface exposed on the first main surface, And has a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the above-mentioned first source region. 10. The method for manufacturing an insulated gate field effect transistor according to claim 8, further comprising: Ions of impurities of the second conductivity type are implanted into the channel formation portion of the first body region through the trench, and a second conductivity type impurity concentration higher than that of other portions is formed on the channel formation portion of the first body region. part of the process. 11. The method for manufacturing an insulated gate field effect transistor according to claim 8, further comprising: In order to shorten the lifetime of minority carriers in the first and second body regions, at least the first and second body regions are irradiated with electron beams.

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