CN101547004A - And gate circuit - Google Patents

Abstract

The invention provides an AND gate circuit. The AND gate circuit of the present invention generates an output signal according to a first input signal and a second input signal. The first and second input signals have different operation intervals. The AND gate circuit of the invention completes the AND logic operation of the first and second input signals without using a potential translation device. A P-type transistor controlled by the first input signal and having one end coupled to a first power supply; the potential provided by the first power supply is related to the operation interval of the first input signal. A P-type transistor controlled by the second input signal and having one end coupled to a second power supply; the potential provided by the second power supply is related to the operation interval of the second input signal. The invention not only improves the reliability of logic operation, but also solves the hidden transistor leakage current problem in the traditional technology.

Description

AND gate circuit

technical field

The present invention relates to a logic circuit, in particular to an AND gate ("AND" gate) circuit.

Background technique

Figure 1 illustrates a conventional AND gate circuit. The AND gate circuit 100 includes a NAND gate ("NAND" gate) 102 and an inverter 104, and all circuit blocks are operated by the same power supply V _PP . The symbol V _GG can be a ground terminal.

The AND gate circuit 100 shown in FIG. 1 receives a first input signal A and a second input signal B, and outputs an output signal C. Referring to FIG. When at least one of the first input signal A and the second input signal B is a logic '0', the potential of the node 106 is pulled up by the transistor 108 or the transistor 110, so that the inverter 104 outputs a logic '0' as the output signal C. When both the first input signal A and the second input signal B are logic '1', the potential of the node 106 is pulled down by the transistor 112 and the transistor 114, so that the inverter 104 outputs a logic '1' as the output signal C. The above actions conform to the 'AND' logic (logic 'AND').

However, with the development of process technology, different blocks in the chip may be driven by different power sources. For example, in a chipset (chipset), the core circuit part can be manufactured using a low voltage (LV) process, and the input/output circuit can be manufactured using a high voltage (HV) process. In this way, the power supply voltage used by the core circuit is lower than the power supply voltage used by the I/O circuit, and the signal operation range of the core circuit is narrower than that of the I/O circuit. If one of the first input signal A and the second input signal B in FIG. 1 comes from the core circuit and the other comes from the I/O circuit, the operation of the AND circuit 100 may be wrong.

For example, suppose: the first input signal A comes from the core circuit and the second input signal B comes from the input/output circuit; the core circuit adopts a first power supply of 1.3 volts; the input/output circuit adopts a second power supply of 3.3 volts; and The AND gate circuit 100 is operated by the second power supply (V _PP in the figure, 3.3 volts). Since the operating range (0V-3.3V) of the second input signal B conforms to the setting of the driving power supply of the AND gate circuit 100 (that is, the second power supply V _PP , which is 3.3 volts), the second input signal B can correctly drive the AND gate circuit 100. Transistor elements within the gate circuit 100 . On the other hand, the operating range (0V-1.3V) of the first input signal A is much smaller than the setting of the driving power of the AND gate circuit 100 (that is, the second power supply V _PP , which is 3.3 volts), so the transistors in the AND gate circuit 100 are very fast. It is easy to be wrongly driven, resulting in leakage current. For example, when the first input signal A is logic '1', its potential is about 1.3 volts, and the transistor 108 may be wrongly turned on, causing the AND gate circuit 100 to malfunction. In order to solve the above-mentioned problems, the traditional solution generally shifts the potential of the first input signal A, and then sends it to the AND circuit 100 for operation.

Contents of the invention

The present invention provides an AND gate circuit, wherein a first input signal and a second input signal are respectively received by a first input terminal and a second input terminal, and the AND gate circuit has an output terminal, a first inverter Phase device and a second inverter, a first P-type transistor and a first N-type transistor, a second N-type transistor and a third N-type transistor.

The first inverter is operated by a first power supply, and the first inverter has an input end and an output end, and the input end of the first inverter is coupled to the first input end. The first P-type transistor has a source coupled to a second power supply, a gate coupled to the second input terminal, and a drain. The first N-type transistor has a drain coupled to the drain of the first P-type transistor, a gate coupled to the second input terminal, and a source. The second N-type transistor has a drain coupled to the source of the first N-type transistor, a gate coupled to the first input terminal, and a source coupled to a ground terminal. The second inverter is operated by the second power supply, and the second inverter has an input terminal and an output terminal, and the input terminal of the second inverter is coupled to the drain of the first P-type transistor. The third N-type transistor has a drain coupled to the output terminal of the second inverter, a gate coupled to the output terminal of the first inverter, and a source coupled to the ground terminal. The drain of the third N-type transistor is also coupled to the output terminal of the AND gate circuit.

The potential of the first power source may be lower than the potential of the second power source. The operating range of the first input signal may be narrower than the operating range of the second input signal.

In another embodiment of the present invention, the AND gate circuit further includes a second P-type transistor having a source coupled to the second power supply, a gate coupled to the output terminal of the AND gate circuit, and a drain coupled to the first The drain of the P-type transistor.

The invention not only improves the reliability of logic operation, but also solves the problem of transistor leakage current hidden in the traditional technology.

Description of drawings

Figure 1 illustrates a conventional AND gate circuit;

Fig. 2 is an embodiment of the AND gate circuit of the present invention;

Fig. 3 is another embodiment of the AND gate circuit of the present invention;

FIG. 4 is an embodiment of the chip of the present invention.

Detailed ways

Various embodiments of the present invention are listed below with illustrations.

Fig. 2 is an embodiment of the AND gate circuit of the present invention. The AND gate circuit 200 respectively receives a first input signal A and a second input signal B through a first input terminal and a second input terminal, and outputs an output signal C through an output terminal. The output signal C is a logical 'AND' operation result of the first input signal A and the second input signal B.

The AND gate circuit 200 includes a first inverter Inv ₁ and a second inverter InV ₂ , a first P-type transistor _MP1 and a first N-type transistor M _n1 , a second N-type transistor M _n2 and a third N-type transistor M _n3 . The first inverter InV ₁ is operated by a first power supply (providing potential V _DD ), and has an input terminal and an output terminal. The input terminal of the first inverter Inv ₁ is coupled to the first input terminal for receiving the first input signal A. As shown in FIG. The first P-type transistor M _P1 has a source coupled to a second power supply (providing potential V _PP ), a gate coupled to the second input terminal for receiving the second input signal B, and a drain. The first N-type transistor _Mn1 has a drain coupled to the drain of the first P-type transistor M _P1 , a gate coupled to the second input terminal for receiving the second input signal B, and a source. The second N-type transistor _Mn2 has a drain coupled to the source of the first N-type transistor _Mn1 , a gate coupled to the first input terminal for receiving the first input signal A, and a source coupled to a ground terminal. V _GG . The second inverter Inv ₂ is operated by the above-mentioned second power supply, and the second inverter Inv ₂ has an input terminal and an output terminal, and the input terminal of the second inverter Inv ₂ is coupled to the first P-type transistor Drain of _MP1 . The third N-type transistor _Mn3 has a drain coupled to the output terminal of the second inverter Inv ₂ , a gate coupled to the output terminal of the first inverter Inv ₁ , and a source coupled to the ground terminal V _GG . The drain of the third N-type transistor _Mn3 is also coupled to the output terminal of the AND circuit 200 to provide the output signal C.

The first power supply V _DD and the second power supply V _PP may have different potentials; and the first input signal A and the second input signal B may have different operating ranges, which are (V _GG ˜V DD ) and (V _GG ˜V _DD ) respectively. V _PP ).

This paragraph exemplifies the operation of the AND gate circuit 200, wherein the first inverter Inv ₁ and the first input signal A belong to a low voltage (LV) operation block, and the first P-type transistor M _P1 and the first N-type transistor M _n1 , the second N-type transistor M _n2 and the third N-type transistor M _n3 , the second inverter Inv ₂ and the second input signal B belong to the high voltage (HV) operation block. The potential of the first power supply V _DD is lower than the potential of the second power supply V _PP , and the operating range (V _GG ˜V _DD ) of the first input signal A is narrower than that of the second input signal B (V _GG ˜V _PP ). . When the first input signal A is logic '0', the first inverter Inv ₁ outputs logic '1', and the third N-type transistor _Mn3 is activated to pull down the output signal C to logic '0'. When the second input signal B is logic '0', the first P-type transistor M _P1 is activated to make the node 202 logic '1', so that the second inverter Inv ₂ outputs logic '0' as the output signal C. When both the first input signal A and the second input signal B are logic '1', the first N-type transistor _Mn1 and the second N-type transistor _Mn2 are turned on to pull down the potential of the node 202, so that the second inverter Inv ₂ outputs logic '1' as output signal C. It can be found from the above description that the output signal C is logic '1' only when the first input signal A and the second input signal B are both logic '1', and other states are logic '0'. The AND gate circuit 200 shown in FIG. 2 is indeed an AND gate circuit.

This paragraph discusses one of the major breakthroughs of the AND gate circuit of the present invention. Since the first power supply V _DD connected to the P-type transistor 204 controlled by the first input signal A matches the operating range of the first input signal A (both belong to low-voltage operation), therefore, the first input signal A can correctly drive P-type transistor 204 . The AND gate circuit 200 not only improves the reliability of logic operations, but also solves the problem of transistor leakage current hidden in the conventional technology shown in FIG. 1 .

The circuit included in the low voltage operation block (the first inverter Inv ₁ ) can be manufactured using a low voltage (LV) process. Circuits included in the high-voltage operation block (the first P-type transistor M _P1 , the first N-type transistor M _n1 , the second N-type transistor M _n2 , the third N-type transistor M _n3 and the second inverter Inv ₂ ) It can be fabricated using a high voltage (HV) process. Comparing the transistors manufactured by the high-voltage process and the low-voltage process, the transistors manufactured by the high-voltage process have a thicker gate oxide layer.

FIG. 3 illustrates another embodiment of the AND gate circuit of the present invention. Compared with the AND gate circuit 200 , the AND gate circuit 300 further includes a second P-type transistor _MP2 . The second P-type transistor _MP2 has a source coupled to the second power supply V _PP , a gate controlled by the output signal C, and a drain coupled to the drain of the first P-type transistor _MP1 . The second P-type transistor _MP2 can be manufactured by a high voltage (HV) process.

The second P-type transistor _MP2 can prevent the node 302 from floating. For example, when the first input signal A is a logic '0' and the second input signal B is a logic '1', the node 302 is neither connected to the second power supply V PP through the first P-type transistor _MP1 , nor connected to the second power supply V _PP through the first P-type transistor MP1. The N-type transistor _Mn1 and the second N-type transistor _Mn2 are connected to the ground terminal V _GG . At this time, the second P-type transistor _MP2 plays a role of stabilizing the potential of the node 302, which will be described in detail below. The first input signal A of logic '0' makes the first inverter Inv ₁ output logic '1', the third N-type transistor _Mn3 is turned on, and the output signal C is logic '0'. The second P-type transistor _MP2 is then activated by the output signal C of the logic '0', and connects the node 302 to the second power supply V _PP , so that the node 302 is not in a floating state, and the second inverter Inv ₂ stabilizes the output logic '0' as output signal C.

In addition to the above-mentioned AND gate circuit, the present invention also provides a chip using the above-mentioned AND gate circuit; FIG. 4 is one implementation manner thereof. The chip 400 includes a low voltage operation block 402 , a high voltage operation block 404 and an AND gate circuit 406 . The AND gate circuit 406 is the AND gate circuit provided above. The low voltage operation block 402 is operated by a first power supply V _DD and provides a first input signal A. The high voltage operation block 404 is operated by a second power supply V _PP and provides a second input signal B . The potential V _PP is higher than the potential V _DD , and the operating range (V _GG ˜V _DD ) of the first input signal A is narrower than that of the second input signal B (V _GG ˜V _PP ).

In the chip 400 shown in FIG. 4 , the low voltage operation block 402 can be manufactured by a low voltage (LV) process, and the high voltage operation block 404 can be manufactured by a high voltage (HV) process. Transistors manufactured by high-voltage processes have thicker gate oxides than transistors manufactured by high- and low-voltage processes.

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.

Claims (10)

1. an AND circuit is characterized in that, comprising:

One first input end receives one first input signal;

One second input receives one second input signal;

One first inverter, by one first power operation, and this first inverter has an input and an output, and the input of this first inverter couples this first input end;

One the one P transistor npn npn has that one source pole couples a second source, a grid couples this second input and a drain electrode;

One the one N transistor npn npn has drain electrode, the grid that a drain electrode couples a P transistor npn npn and couples this second input and one source pole;

One the 2nd N transistor npn npn has that source electrode, a grid that a drain electrode couples a N transistor npn npn couple this first input end and one source pole couples an earth terminal;

One second inverter, by the operation of this second source, and this second inverter has an input and an output, and the input of this second inverter couples the drain electrode of a P transistor npn npn;

One the 3rd N transistor npn npn, have one the drain electrode couple the output of this second inverter, output and the one source pole that a grid couples this first inverter couples this earth terminal; And

One output couples the drain electrode of the 3rd N transistor npn npn.

2. AND circuit according to claim 1 is characterized in that, the current potential of this first power supply is lower than the current potential of this second source.

3. AND circuit according to claim 2 is characterized in that, is narrower than between the operating space of above-mentioned second input signal between the operating space of above-mentioned first input signal.

4. AND circuit according to claim 2 is characterized in that, above-mentioned first inverter adopts a low-voltage processing procedure manufacturing.

5. AND circuit according to claim 4, it is characterized in that, an above-mentioned P transistor npn npn, a N transistor npn npn, the 2nd N transistor npn npn and the 3rd N transistor npn npn and this second inverter adopt a high voltage processing procedure manufacturing, and the transistor of the more above-mentioned low-voltage processing procedure of the transistor manufacturing of this high voltage processing procedure manufacturing has thicker grid oxic horizon.

6. AND circuit according to claim 1, it is characterized in that, also comprise one the 2nd P transistor npn npn, have one source pole and couple above-mentioned second source, a grid and couple the above-mentioned output of this AND circuit and the above-mentioned drain electrode that a drain electrode couples a P transistor npn npn.

7. AND circuit according to claim 6 is characterized in that, the current potential of this first power supply is lower than the current potential of this second source.

8. AND circuit according to claim 7 is characterized in that, is narrower than between the operating space of above-mentioned second input signal between the operating space of above-mentioned first input signal.

9. AND circuit according to claim 7 is characterized in that, above-mentioned first inverter adopts a low-voltage processing procedure manufacturing.

10. AND circuit according to claim 9, it is characterized in that, an above-mentioned P transistor npn npn, the 2nd P transistor npn npn, a N transistor npn npn, the 2nd N transistor npn npn, the 3rd N transistor npn npn and this second inverter adopt a high voltage processing procedure manufacturing, and the transistor of the more above-mentioned low-voltage processing procedure of the transistor manufacturing of this high voltage processing procedure manufacturing has thicker grid oxic horizon.

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