CN101540546B - Power factor correction circuit and power supply device thereof - Google Patents

Abstract

The invention discloses a power factor correction circuit which comprises a boost converter, a first capacitor, a first resistor and a boost control unit. The boost control unit comprises a signal generator and a frequency controller. The boost converter is used for converting a rectified voltage into a correction voltage according to the pulse width modulation signal. The first capacitor and the first resistor are connected in series between the input end of the boost converter and the ground end. The boost control unit is used for generating a pulse width modulation signal and adjusting the working period and the frequency of the pulse width modulation signal according to the current flowing through the first resistor, the rectified voltage and the correction voltage. The signal generator is used for generating a ramp signal and adjusting the slope of the ramp signal according to a charging current. The frequency controller is used for adjusting the charging current according to the rectified voltage.

Description

Power factor correction circuit and its power supply device

technical field

The present invention relates to a power factor correction circuit and its power supply device, and in particular to a power factor correction circuit capable of reducing electromagnetic interference (EMI) and its power supply device.

Background technique

Among the evaluation standards of various electronic devices, Electromagnetic Compatibility (EMC) is a key quality index. The evaluation of electromagnetic compatibility includes electromagnetic interference (Electromagnetic Interference, EMI) and anti-electromagnetic interference (Electromagnetic Susceptibility, EMS). Because the signal transmission speed of the current electronic device is getting faster and faster, the electromagnetic interference caused by the electronic components inside the electronic device will become more and more serious, and then affect the normal operation of other electronic components in the electronic device.

Generally speaking, electromagnetic interference is mainly introduced into the circuit through the power supply. Therefore, in order to pass the corresponding standards in the server, the electromagnetic interference test of the power supply is also a very critical test item. In addition, current power supplies are usually configured with at least one switching element, and the desired output voltage is generated by controlling the switching element to be turned on and off.

However, as the switch is switched repeatedly, the electromagnetic interference that may be caused by the power supply also increases. Although, the existing power supply uses the frequency of its internal pulse width modulation (Power Width Modulation, PWM) signal to constantly change to reduce electromagnetic interference. However, how to change the frequency of the PWM signal while maintaining the stability of the power output is an important issue.

Contents of the invention

The invention provides a power factor correction circuit, which can adjust the frequency of a pulse width modulation signal to reduce electromagnetic interference.

The invention provides a power supply device, which can reduce the phenomenon of electromagnetic interference by adjusting the frequency of the internal pulse width modulation signal.

The present invention proposes a power factor correction circuit, which includes a boost converter, a first capacitor, a first resistor and a boost control unit. The boost converter has an input terminal, an output terminal and a ground terminal, and is used for converting the rectified voltage transmitted by the input terminal into a correction voltage transmitted by the output terminal according to the pulse width modulation signal. The first terminal of the first capacitor is coupled to the input terminal. The first end of the first resistor is coupled to the second end of the first capacitor, and the second end is coupled to the ground. The boost control unit is coupled to the first terminal and the second terminal of the first resistor, the input terminal and the output terminal. The boost control unit generates a pulse width modulation signal based on a ramp signal and flows through the first The current of the resistor, the rectified voltage and the correction voltage are used to adjust the duty cycle and frequency of the PWM signal.

In addition, the boost control unit includes a signal generator and a frequency controller. The signal generator is used for generating a ramp signal, and adjusting the slope of the ramp signal according to a charging current. The frequency controller is coupled to the signal generator and the input terminal for adjusting the charging current according to the rectified voltage.

In an embodiment of the present invention, the boost converter includes an inductor, a first transistor, a diode and a second capacitor. The first end of the inductor is coupled to the input end of the boost converter. The gate terminal of the first transistor receives the PWM signal, the drain terminal thereof is coupled to the second terminal of the inductor, and the source terminal of the first transistor is coupled to the ground terminal of the boost converter. The anode terminal of the diode is coupled to the drain terminal of the first transistor, and the cathode terminal thereof is coupled to the output terminal of the boost converter. A first terminal of the second capacitor C2 is coupled to the cathode terminal of the diode, and a second terminal thereof is coupled to the ground terminal of the boost converter. In addition, the above-mentioned first transistor is an NMOS transistor.

In an embodiment of the present invention, the signal generator includes a second resistor, a second transistor, a third transistor, a third capacitor, a fourth transistor and a comparator. The first terminal of the second resistor receives the charging current, and the second terminal thereof is coupled to the ground terminal. The emitter terminal of the second transistor receives the first voltage, and the base terminal and collector terminal of the second transistor are coupled to the first terminal of the second resistor. The emitter terminal of the third transistor is coupled to the emitter terminal of the second transistor, and the base terminal thereof is coupled to the base terminal of the fourth transistor. The first terminal of the third capacitor is coupled to the collector terminal of the third transistor, and the second terminal of the third capacitor is coupled to the ground terminal. The drain terminal of the fourth transistor is coupled to the collector terminal of the third transistor, and the source terminal of the fourth transistor is coupled to the ground terminal. The first input terminal of the comparator is coupled to the drain terminal of the fourth transistor, the second input terminal thereof receives the second voltage, and the output terminal thereof is coupled to the gate terminal of the fourth transistor.

In an embodiment of the present invention, the above-mentioned second transistor and the third transistor are PNP bipolar transistors. In addition, the above-mentioned fourth transistor is an NMOS transistor.

In an embodiment of the present invention, the frequency controller includes a third resistor, a fifth transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor, a sixth transistor, a Nine resistors, tenth resistors, eleventh resistors, fifth capacitor C5 and twelfth resistors. The first terminal of the third resistor is coupled to the signal generator, and the second terminal of the third resistor is coupled to the ground terminal. The collector terminal of the fifth transistor is coupled to the first terminal of the third resistor. A first terminal of the fourth resistor is coupled to the emitter terminal of the fifth transistor, and a second terminal thereof is coupled to the ground terminal. The first end of the fifth resistor receives the rectified voltage. The first terminal of the sixth resistor is coupled to the second terminal of the fifth resistor.

According to the above, the first terminal of the seventh resistor is coupled to the second terminal of the sixth resistor, and the second terminal of the seventh resistor is coupled to the base terminal of the fifth transistor. The first end of the eighth resistor is coupled to the second end of the seventh resistor, and the second end is coupled to the ground. The first end of the fourth capacitor is coupled to the first end of the eighth resistor, and the second end of the fourth capacitor is coupled to the ground. The collector terminal of the sixth transistor is coupled to the first terminal of the fourth capacitor. The first terminal of the ninth resistor is coupled to the emitter terminal of the sixth transistor, and the second terminal of the ninth resistor is coupled to the ground terminal. The first end of the tenth resistor receives a DC voltage proportional to the rectified voltage, and the second end of the tenth resistor is coupled to the base end of the sixth transistor. The first end of the eleventh resistor is coupled to the second end of the tenth resistor, and the second end is coupled to the ground. A first end of the fifth capacitor is coupled to the first end of the tenth resistor, and a second end thereof is coupled to the ground. The first end of the twelfth resistor is coupled to the first end of the fifth capacitor, and the second end is coupled to the ground.

In an embodiment of the present invention, the fifth transistor and the sixth transistor are NPN bipolar transistors. In addition, the resistance of the ninth resistor is smaller than the resistance of the eighth resistor.

The invention provides a power supply device, which includes a filter, a rectifier, a power factor correction circuit and a DC converter. The filter is used to receive an AC voltage and filter out high frequency components of the AC voltage. The rectifier is coupled to the filter for rectifying the filtered AC voltage to generate a rectified voltage. The power factor correction circuit is coupled to the filter for converting the rectified voltage into a correction voltage according to a pulse width modulation signal, wherein the power factor correction circuit includes a boost converter, a first capacitor, a first resistor, and a boost control unit.

The boost converter has an input terminal, an output terminal and a ground terminal, and is used for converting the rectified voltage transmitted by the input terminal into a correction voltage transmitted by the output terminal according to the pulse width modulation signal. The first terminal of the first capacitor is coupled to the input terminal. The first end of the first resistor is coupled to the second end of the first capacitor, and the second end is coupled to the ground. The boost control unit is coupled to the first terminal and the second terminal, the input terminal and the output terminal of the first resistor, and the boost control unit generates a pulse width modulation signal based on the ramp signal, and according to the voltage flowing through the first resistor Current, rectified voltage and correction voltage are used to adjust the duty cycle and frequency of the PWM signal.

In addition, the boost control unit includes a signal generator and a frequency controller. The signal generator is used for generating a ramp signal, and adjusting the slope of the ramp signal according to a charging current. The frequency controller is coupled to the signal generator and the input terminal for adjusting the charging current according to the rectified voltage. The DC converter is coupled to the power factor correction circuit for converting the correction voltage into an output voltage.

In the present invention, the magnitude of the charging current is controlled by a frequency controller, so that the signal generation circuit adjusts the slope of the ramp signal correspondingly. Since the slope of the ramp signal changes, the frequency of the pulse width modulation signal is further adjusted, so as to reduce the phenomenon of electromagnetic interference generated by the power supply device. In addition, the power supply device of the present invention can still provide a stable voltage source during the process of adjusting the pulse width modulation signal.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a block diagram of a power supply device according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram of the power factor correction circuit shown in FIG. 1 .

FIG. 3 is a detailed circuit diagram of the power factor correction circuit of FIG. 2 .

Detailed ways

In the following description, in order to present the consistency of the description of the present invention, in different drawings, if there are elements with the same or similar functions and structures, the same element symbols and names will be used.

FIG. 1 is a block diagram of a power supply device according to an embodiment of the present invention. Referring to FIG. 1 , the power supply device 100 includes a filter 110 , a rectifier 120 , a power factor correction circuit 130 and a DC converter (DC to DC Converter) 140 .

The filter 110 is used for receiving the AC voltage V _AC and filtering out high frequency components of the AC voltage V _AC . The rectifier 120 is coupled to the filter 110 and used for rectifying the filtered AC voltage V _AC to generate a rectified voltage V _REC . In this embodiment, the rectifier 120 can be implemented as a bridge rectifier.

The power factor correction circuit 130 is coupled to the rectifier 120 . Generally, the power factor correction circuit 130 adjusts the waveform of the input current so that the phase difference between the input current and the rectified voltage V _REC approaches zero. In this way, the power supply device 100 can use the power factor correction circuit 130 to reduce the problem of power consumption.

The DC converter 140 is coupled to the power factor correction circuit 130 for converting the correction voltage V _C so as to generate the output voltage V _O to be provided by the power supply device 100 .

It is worth mentioning that in this embodiment, the power factor correction circuit 130 can further reduce electromagnetic interference. In order for those skilled in the art to easily understand the technical content of this embodiment, the power factor correction circuit 130 will be further described below.

FIG. 2 is a circuit block diagram of the power factor correction circuit 130 in FIG. 1 . Please refer to FIG. 2 , the power factor correction circuit 130 includes a boost converter 210 , a capacitor C1 , a resistor R1 and a boost control unit 230 . Wherein, the boost converter 210 has an input terminal 211 , an output terminal 212 and a ground terminal 213 . Moreover, the boost converter 210 is used for converting the rectified voltage V _REC transmitted by the input terminal 211 into a corrected voltage V _C transmitted by the output terminal 212 according to the pulse width modulation signal V _PWM . A first end of the capacitor C1 is coupled to the input end 211 . A first terminal of the resistor R1 is coupled to a second terminal of the capacitor C1 , and a second terminal thereof is coupled to the ground terminal 213 .

The boost control unit 230 is coupled to the first end and the second end of the resistor R1 , the input end 211 and the output end 212 . The boost control unit 230 generates a pulse width modulation signal V _PWM based on a ramp signal V _R , and adjusts the pulse width modulation signal according to the current I ₁ flowing through the resistor R1 , the rectified voltage V _REC and the correction voltage V _C V _PWM duty cycle (Duty Cycle) and frequency.

In this embodiment, the boost control unit 230 includes a signal generator 231 and a frequency controller 232 . The signal generator 231 is used to generate the ramp signal V _R , and adjust the slope of the ramp signal V _R according to the charging current _IC . The frequency controller 232 is coupled to the signal generator 231 and the input terminal 211 for adjusting the charging current I _C according to the rectified voltage V _REC .

It is worth mentioning that the power factor correction circuit 130 first adjusts the charging current I _C through the frequency controller 232 . Afterwards, the signal generator 231 adjusts the frequency of the ramp signal _VR by utilizing the change of the current value of the charging current _IC , so that the boost control unit 230 adjusts the frequency of the pulse width modulation signal V _PWM accordingly, so as to reduce electromagnetic interference The phenomenon.

The circuit diagram of the power factor correction circuit 130 will be provided below to further illustrate how the power factor correction circuit 130 adjusts the charging current I _C and the slope of the ramp signal _VR .

FIG. 3 is a detailed circuit diagram of the power factor correction circuit 130 in FIG. 2 . Referring to FIG. 3 , the boost converter 210 includes an inductor L, a transistor M1 , a diode D and a capacitor C2 . A first end of the inductor L is coupled to the input end 211 of the boost converter 210 . The gate terminal of the transistor M1 receives the pulse width modulation signal V _PWM , the drain terminal of the transistor M1 is coupled to the second terminal of the inductor L, and the source terminal of the transistor M1 is coupled to the ground terminal 213 of the boost converter 210 . The anode terminal of the diode D is coupled to the drain terminal of the transistor M1 , and the cathode terminal of the diode D is coupled to the output terminal 212 of the boost converter 210 . A first terminal of the capacitor C2 is coupled to the cathode terminal of the diode D, and a second terminal of the capacitor C2 is coupled to the ground terminal 213 of the boost converter 210 . In this embodiment, the transistor M1 is, for example, an NMOS transistor.

The signal generator 231 includes a resistor R2 , transistors Tr1 and Tr2 , a transistor M2 , a capacitor C3 and a comparator 310 . A first end of the resistor R2 receives the charging current I _C , and a second end thereof is coupled to the ground. The emitter terminal of the transistor Tr1 receives the first voltage V1, and the base terminal and the collector terminal of the transistor Tr1 are coupled to the first terminal of the resistor R2. The emitter terminal of the transistor Tr2 is coupled to the emitter terminal of the transistor Tr1 , and the base terminal of the transistor Tr2 is coupled to the base terminal of the transistor Tr1 .

Moreover, the first end of the capacitor C3 is coupled to the collector end of the transistor Tr2, and the second end thereof is coupled to the ground end. The drain terminal of the transistor M2 is coupled to the collector terminal of the transistor Tr2, and the source terminal of the transistor M2 is coupled to the ground terminal. A first input terminal of the comparator 310 is coupled to the drain terminal of the transistor M2, a second input terminal of the comparator 310 receives the second voltage V2, and an output terminal of the comparator 310 is coupled to the gate terminal of the transistor M2. In this embodiment, the transistors Tr1 and Tr2 are, for example, PNP bipolar transistors, and the transistor M2 is, for example, an NMOS transistor.

Please continue to refer to FIG. 3 , the frequency controller 232 includes resistors R3 - R12 , transistors Tr3 and Tr4 , and capacitors C4 and C5 . A first end of the resistor R3 is coupled to the signal generator 231 , and a second end thereof is coupled to the ground. The collector terminal of the transistor Tr3 is coupled to the first terminal of the resistor R3. A first terminal of the resistor R4 is coupled to the emitter terminal of the transistor Tr3, and a second terminal thereof is coupled to the ground terminal. The first end of the resistor R5 receives the rectified voltage V _REC . A first end of the resistor R6 is coupled to a second end of the resistor R5. A first terminal of the resistor R7 is coupled to a second terminal of the resistor R6, and a second terminal thereof is coupled to a base terminal of the transistor Tr3.

In addition, the first end of the resistor R8 is coupled to the second end of the resistor R7, and the second end is coupled to the ground. The first end of the capacitor C4 is coupled to the first end of the resistor R8, and the second end thereof is coupled to the ground. The collector terminal of the transistor Tr4 is coupled to the first terminal of the capacitor C4. A first terminal of the resistor R9 is coupled to the emitter terminal of the transistor Tr4, and a second terminal thereof is coupled to the ground terminal. A first terminal of the resistor R10 receives a DC voltage V _FF proportional to the rectified voltage V _REC , and a second terminal thereof is coupled to the base terminal of the transistor Tr4 .

Furthermore, the first end of the resistor R11 is coupled to the second end of the resistor R10 , and the second end is coupled to the ground. The first end of the capacitor C5 is coupled to the first end of the resistor R10, and the second end thereof is coupled to the ground. A first end of the resistor R12 is coupled to a first end of the capacitor C5, and a second end thereof is coupled to the ground. In this embodiment, the transistors Tr3 and Tr4 are, for example, NPN bipolar transistors.

In terms of overall operation, firstly, when the transistor Tr3 in the frequency controller 232 is not turned on, the charging current _IC is the sum of the currents flowing through the resistors R2 and R3. Since the transistors Tr1 and Tr2 form a current mirror, the current output from the collector terminal of the transistor Tr2 is also the charging current I _C . Afterwards, the comparator 310 controls the conduction state of the transistor M2 to cause the capacitor C3 to be charged or discharged. As the capacitor C3 is repeatedly charged and discharged, the signal generator 231 will generate the ramp signal _VR accordingly.

When the transistor Tr3 is turned on, the charging current _IC is the sum of the currents flowing through the resistors R2, R3 and R4. Therefore, the current value of the charging current _IC will change. Due to the change of the charging current _IC , the signal controller 231 adjusts the slope of the ramp signal _VR . In this way, the boost control unit 230 also adjusts the frequency of the pulse width signal V _PWM correspondingly, thereby reducing the phenomenon of electromagnetic interference of the power supply device 100 .

In this embodiment, the frequency controller 232 can determine the conduction state of the transistor Tr3 through the rectified voltage V _REC . For example, whether the transistor Tr3 is turned on or not depends on the voltage received by its base terminal, that is, the voltage difference between the two ends of the resistor R8. The voltage on the resistor R8 is obtained by dividing the rectified voltage V _REC received by the frequency controller 232 through the resistors R5 - R8 . Therefore, the frequency controller 232 can determine the conduction state of the transistor Tr3 according to the rectified voltage V _REC . The capacitor C4 is used to filter out high frequency noise.

In addition, whether the transistor Tr4 is turned on or not can also determine the conduction state of the transistor Tr3. For example, when the transistor Tr4 is not turned on, the voltage received by the base terminal of the transistor Tr3 is the voltage difference between the two ends of the resistor R8. When the transistor Tr4 is turned on, the voltage received by the base terminal of the transistor Tr3 is the voltage difference after the resistors R8 and R9 are connected in parallel. In contrast, the transistor Tr3 will change its conduction state according to the magnitude of the voltage received by its base terminal.

In addition, the frequency controller 232 can determine the conduction state of the transistor Tr4 according to the magnitude of the DC voltage V _FF . For example, firstly, the DC voltage V _FF is filtered by a filter composed of the resistor R12 and the capacitor C5 . Afterwards, the filtered DC voltage V _FF is divided by the resistors R10 and R11 to generate the base terminal voltage of the transistor Tr4 , that is, the voltage difference between the two ends of the resistor R11 . Therefore, the DC voltage V _FF can control any current change caused by the rectified voltage V _REC , thereby ensuring that the frequency of the pulse width modulation signal V _PWM can be changed as a function of the rectified voltage V _REC .

In this embodiment, the frequency of the pulse width modulation signal V _PWM provided by the boost control unit 230 will be changed by 20%. In addition, in order to keep the minimum inductance and loss, the frequency change of the power factor correction circuit 130 cannot exceed 20% to 30% of the fundamental frequency. Furthermore, the duty cycle in the power factor correction circuit 130 will vary from, for example, 80% to 100%.

To sum up, the present invention controls the magnitude of the charging current through the frequency controller, so that the signal generating circuit adjusts the slope of the ramp signal correspondingly. Since the slope of the ramp signal changes, the frequency of the pulse width modulation signal is further adjusted to reduce the phenomenon of electromagnetic interference generated by the power supply device. In addition, the power supply device will continuously output a stable voltage source during the process of adjusting the pulse width modulation signal.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention, and anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (16)

1. power factor correction circuit comprises:

One boost converter has an input, an output and an earth terminal, in order to convert the commutating voltage that this input transmitted to a correction voltage that this output transmits according to a pulse-width signal;

One first electric capacity, its first end is coupled to this input;

One first resistance, its first end is coupled to second end of this first electric capacity, and its second end is coupled to this earth terminal; And

One control unit that boosts, be coupled to first end and second end, this input and this output of this first resistance, this control unit that boosts is that benchmark produces this pulse-width signal with a ramp signal, and adjust the work period and the frequency of this pulse-width signal according to electric current, this commutating voltage and this correction voltage of this first resistance of flowing through, wherein this control unit that boosts comprises:

One signal generator in order to producing this ramp signal, and is adjusted the slope of this ramp signal according to a charging current; And

One frequency controller is coupled to this signal generator and this input, in order to adjust this charging current according to this commutating voltage.

2. power factor correction circuit as claimed in claim 1 is characterized in that, this boost converter comprises:

One inductance, its first end is coupled to this input of this boost converter;

One the first transistor, its gate terminal receives this pulse-width signal, and its drain electrode end is coupled to second end of this inductance, and its source terminal is coupled to this earth terminal of this boost converter;

One diode, its anode tap is coupled to the drain electrode end of this first transistor, and its cathode terminal is coupled to this output of this boost converter; And

One second electric capacity, its first end is coupled to the cathode terminal of this diode, and its second end is coupled to this earth terminal of this boost converter.

3. power factor correction circuit as claimed in claim 2 is characterized in that, this first transistor is a nmos pass transistor.

4. power factor correction circuit as claimed in claim 1 is characterized in that, this signal generator comprises:

One second resistance, its first termination is received this charging current, and its second end is coupled to a ground end;

One transistor seconds, its emitter terminal receive one first voltage, and its base terminal and collector terminal are coupled to first end of this second resistance;

One the 3rd transistor, its emitter terminal is coupled to the emitter terminal of this transistor seconds, and its base terminal is coupled to the base terminal of this transistor seconds;

One the 3rd electric capacity, its first end is coupled to the 3rd transistorized collector terminal, and its second end is coupled to this ground end;

One the 4th transistor, its drain electrode end are coupled to the 3rd transistorized collector terminal, and its source terminal is coupled to this ground end; And

One comparator, its first input end are coupled to the 4th transistor drain end, and its second input receives one second voltage, and its output is coupled to the 4th transistorized gate terminal.

5. power factor correction circuit as claimed in claim 4 is characterized in that, this transistor seconds and the 3rd transistor are the PNP bipolar transistor.

6. power factor correction circuit as claimed in claim 4 is characterized in that, the 4th transistor is a nmos pass transistor.

7. power factor correction circuit as claimed in claim 1 is characterized in that, this frequency controller comprises:

One the 3rd resistance, its first end is coupled to this signal generator, and its second end is coupled to a ground end;

One the 5th transistor, its collector terminal are coupled to first end of the 3rd resistance;

One the 4th resistance, its first end is coupled to the 5th transistorized emitter terminal, and its second end is coupled to this ground end;

One the 5th resistance, its first termination is received this commutating voltage;

One the 6th resistance, its first end is coupled to second end of the 5th resistance;

One the 7th resistance, its first end is coupled to second end of the 6th resistance, and its second end is coupled to the 5th transistorized base terminal;

One the 8th resistance, its first end is coupled to second end of the 7th resistance, and its second end is coupled to this ground end;

One the 4th electric capacity, its first end is coupled to first end of the 8th resistance, and its second end is coupled to this ground end;

One the 6th transistor, its collector terminal are coupled to first end of the 4th electric capacity;

One the 9th resistance, its first end is coupled to the 6th transistorized emitter terminal, and its second end is coupled to this ground end;

1 the tenth resistance, its first termination is received a direct current voltage that is proportional to this commutating voltage, and its second end is coupled to the 6th transistorized base terminal;

1 the 11 resistance, its first end is coupled to second end of the tenth resistance, and its second end is held with being coupled to;

One the 5th electric capacity, its first end is coupled to first end of the tenth resistance, and its second end is held with being coupled to; And

1 the 12 resistance, its first end couples first end of the 5th electric capacity, and its second end is held with being coupled to.

8. power factor correction circuit as claimed in claim 7 is characterized in that, the 5th transistor AND gate the 6th transistor is the NPN bipolar transistor.

9. power supply device comprises:

One filter, in order to receiving an alternating voltage, and the radio-frequency component of this alternating voltage of filtering;

One rectifier couples this filter, in order to filtered this alternating voltage is carried out rectification, to produce a commutating voltage;

One power factor correction circuit couples this filter, and comprises:

One boost converter has an input, an output and an earth terminal, in order to convert this commutating voltage that this input transmitted to a correction voltage that this output transmits according to this pulse-width signal;

One first electric capacity, its first end is coupled to this input;

One first resistance, its first end is coupled to second end of this first electric capacity, and its second end is coupled to this earth terminal; And

One control unit that boosts, be coupled to first end and second end, this input and this output of this first resistance, this control unit that boosts is that benchmark produces this pulse-width signal with a ramp signal, and adjust the work period and the frequency of this pulse-width signal according to electric current, this commutating voltage and this correction voltage of this first resistance of flowing through, wherein this control unit that boosts comprises:

One signal generator in order to producing this ramp signal, and is adjusted the slope of this ramp signal according to a charging current; And

One frequency controller is coupled to this signal generator and this input, in order to adjust this charging current according to this commutating voltage;

Flow variator always, couple this power factor correction circuit, in order to convert this correction voltage to an output voltage.

10. power supply device as claimed in claim 9 is characterized in that, this boost converter comprises:

One inductance, its first end is coupled to this input of this boost converter;

One the first transistor, its gate terminal receives this pulse-width signal, and its drain electrode end is coupled to second end of this inductance, and its source terminal is coupled to this earth terminal of this boost converter;

One diode, its anode tap is coupled to the drain electrode end of this first transistor, and its cathode terminal is coupled to this output of this boost converter; And

One second electric capacity, its first end is coupled to the cathode terminal of this diode, and its second end is coupled to this earth terminal of this boost converter.

11. power supply device as claimed in claim 10 is characterized in that, this first transistor is a nmos pass transistor.

12. power factor correction circuit as claimed in claim 9 is characterized in that, this signal generator comprises:

One second resistance, its first termination is received this charging current, and its second end is coupled to a ground end;

One transistor seconds, its emitter terminal receive one first voltage, and its base terminal and collector terminal are coupled to first end of this second resistance;

One the 3rd transistor, its emitter terminal is coupled to the emitter terminal of this transistor seconds, and its base terminal is coupled to the base terminal of this transistor seconds;

One the 3rd electric capacity, its first end is coupled to the 3rd transistorized collector terminal, and its second end is coupled to this ground end;

One the 4th transistor, its drain electrode end are coupled to the 3rd transistorized collector terminal, and its source terminal is coupled to this ground end; And

One comparator, its first input end are coupled to the 4th transistor drain end, and its second input receives one second voltage, and its output is coupled to the 4th transistorized gate terminal.

13. power supply device as claimed in claim 12 is characterized in that, this transistor seconds and the 3rd transistor are the PNP bipolar transistor.

14. power supply unit as claimed in claim 12 is characterized in that, the 4th transistor is a nmos pass transistor.

15. power supply device as claimed in claim 9 is characterized in that, this frequency controller comprises:

One the 3rd resistance, its first end is coupled to this signal generator, and its second end is coupled to a ground end;

One the 5th transistor, its collector terminal are coupled to first end of the 3rd resistance;

One the 4th resistance, its first end is coupled to the 5th transistorized emitter terminal, and its second end is coupled to this ground end;

One the 5th resistance, its first termination is received this commutating voltage;

One the 6th resistance, its first end is coupled to second end of the 5th resistance;

One the 7th resistance, its first end is coupled to second end of the 6th resistance, and its second end is coupled to the 5th transistorized base terminal;

One the 8th resistance, its first end is coupled to second end of the 7th resistance, and its second end is coupled to this ground end;

One the 4th electric capacity, its first end is coupled to first end of the 8th resistance, and its second end is coupled to this ground end;

One the 6th transistor, its collector terminal are coupled to first end of the 4th electric capacity;

One the 9th resistance, its first end is coupled to the 6th transistorized emitter terminal, and its second end is coupled to this ground end;

1 the tenth resistance, its first termination is received a direct current voltage that is proportional to this commutating voltage, and its second end is coupled to the 6th transistorized base terminal;

1 the 11 resistance, its first end is coupled to second end of the tenth resistance, and its second end is held with being coupled to;

One the 5th electric capacity, its first end is coupled to first end of the tenth resistance, and its second end is held with being coupled to; And

1 the 12 resistance, its first end couples first end of the 5th electric capacity, and its second end is held with being coupled to.

16. power supply device as claimed in claim 15 is characterized in that, the 5th transistor AND gate the 6th transistor is the NPN bipolar transistor.

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