CN101540312A - Stack type chip packaging structure - Google Patents

Abstract

The invention discloses a stacked chip packaging structure. The stacked chip package structure at least comprises a first substrate, a first chip, a second chip, at least one second substrate and a sealant. The first chip is arranged on the first substrate, the second chip is arranged on the first chip, the second substrate is arranged on the first chip and is electrically connected with the first chip and the first substrate, and the sealant is formed on the first substrate and coats the first chip, the second chip and the second substrate. The stacked chip packaging structure can avoid the situation that the existing wiring is intensively welded on a single substrate, and can solve the problems of overlarge substrate area or excessively dense connecting pads, thereby miniaturizing the volume of the packaging structure and ensuring the qualification rate in the manufacturing process.

Description

Stacked Chip Package Structure

technical field

The present invention relates to a stacked chip packaging structure, and in particular to a stacked chip packaging structure which can avoid wiring from being concentrated on a single substrate.

Background technique

In the semiconductor production process, integrated circuit packaging (IC package) is one of the important steps in the manufacturing process. It is used to protect the IC chip and provide external electrical connections to prevent damage from external forces or environmental factors during transportation and placement. . In addition, integrated circuit components also need to be combined with passive components such as resistors and capacitors to form a system in order to perform the intended functions, and electronic packaging (Electronic Packaging) is used to establish the protection and organizational structure of integrated circuit components. Generally speaking, electronic packaging begins after the integrated circuit chip manufacturing process, including the bonding and fixing of IC chips, circuit connection, structural sealing and bonding of circuit boards, system assembly, and all manufacturing processes until product completion. The purpose of electronic packaging is to complete the combination of IC chips and other necessary circuit components to transmit electrical energy and circuit signals, provide heat dissipation channels, load bearing and structural protection and other functions.

In today's electronic devices, a single electronic device often needs to be provided with multiple chips to perform multiple functions at the same time, so as to meet the needs of modern people for electronic devices. However, if a plurality of chips are respectively formed in different packaging structures, the occupied space of the packaging structures will be increased. Therefore, semiconductor structures that stack semiconductor chips to increase packaging density have been widely used. The traditional stacked chip packaging structure has a stack structure formed by stacking multiple chips. At this time, these chips are stacked on a substrate, and the input/output (I/O) of all chips are connected to multiple bonding pads (Bond Pad) of the substrate through gold wires, and the connection between chips is carried out through this substrate. electrical connection.

However, since all the input/output (I/O) of the existing stacked chip package structure is connected on a single substrate, the number of pads on the substrate is increased, thereby increasing the area of the substrate, and increasing the total cost of the package structure. space; or, the spacing between the pads needs to be reduced, thus increasing the difficulty of connecting gold wires to the pads, and increasing the difficulty of the manufacturing process.

Contents of the invention

The invention provides a stacked chip package structure, which enables the first chip and the second chip to be connected to the second substrate, so as to reduce the installation area of the first substrate, and further miniaturize the volume of the package structure.

The invention provides a stacked chip packaging structure to avoid the situation that the wires are concentratedly soldered on a single substrate, which makes it difficult to solder the wires, thereby ensuring the qualified rate of the manufacturing process.

According to an embodiment of the present invention, the stacked chip packaging structure of the present invention at least includes a first substrate, a first chip, a second chip, at least one second substrate, at least one first wiring, at least one second wiring, and an encapsulant . The first chip is arranged on the first substrate, the second chip is arranged on the first chip, the second substrate is arranged on the first chip, and is electrically connected to the first chip and the first substrate, and the first wiring is connected to the second Between the chip and the second substrate, the second wiring is connected between the first substrate and the second substrate, the sealing body is formed on the first substrate, and covers the first chip, the second chip, the second substrate, and the first wiring and the second connection.

Moreover, according to an embodiment of the present invention, the method for manufacturing the stacked chip packaging structure of the present invention at least includes: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and a second substrate on the first chip , wherein the second substrate is electrically connected to the first chip and the first substrate; at least one first wiring is connected between the second chip and the second substrate; at least one second wiring is connected between the first substrate and the second substrate and forming an encapsulation on the first substrate to cover the first chip, the second chip, the second substrate, the first wiring and the second wiring.

Therefore, the stacked chip packaging structure of the present invention can avoid the situation that the existing wires are concentratedly welded on a single substrate, thereby miniaturizing the volume of the packaging structure and ensuring the yield of the manufacturing process.

Description of drawings

1A is a schematic cross-sectional view of a stacked chip package structure according to a first embodiment of the present invention;

1B is a schematic top view of a stacked chip package structure according to the first embodiment of the present invention;

2A is a schematic cross-sectional view of a stacked chip package structure according to a second embodiment of the present invention;

2B is a schematic top view of a stacked chip package structure according to a second embodiment of the present invention;

3A is a schematic cross-sectional view of a stacked chip package structure according to a third embodiment of the present invention;

3B is a schematic top view of a stacked chip package structure according to a third embodiment of the present invention.

Among them, the accompanying drawings illustrate:

100, 100b, 100c: stacked chip package structure

110: First substrate 111: Pad

120, 120b, 120c: second substrate

121: pad 122: slotting

130: The first chip 131: Conductive bumps

140: Second chip 150: First wiring

160: Second wiring 170: Sealant

Detailed ways

Please refer to FIG. 1A and FIG. 1B , FIG. 1A is a schematic cross-sectional view of a stacked chip packaging structure according to the first embodiment of the present invention, and FIG. 1B is a schematic top view of the stacked chip packaging structure according to the first embodiment of the present invention. The stacked chip packaging structure 100 of the present embodiment includes a first substrate 110 , a second substrate 120 , a first chip 130 , a second chip 140 , a first wire 150 , a second wire 160 and an encapsulant 170 . The first chip 130 is disposed on the first substrate 110 , the second chip 140 is disposed on the first chip 130 , the second substrate 120 is disposed on the first chip 130 and is electrically connected to the first chip 130 and the first substrate 120 , wherein the second substrate 120 is located on at least one side of the second chip 140, the first wiring 150 is connected between the second chip 140 and the second substrate 120, and the second wiring 160 is connected between the first substrate 110 and the second substrate 120 In between, the encapsulant 170 is used to cover the first chip 130 , the second chip 140 , the second substrate 120 , the first wiring 150 and the second wiring 160 . Wherein, the stacked chip packaging structure 100 is provided with an output/input (Output/Input) on the back or front of the first substrate 110 for electrical connection with other electronic components (not shown), for example, the stacked chip The first substrate 110 of the package structure 100 is a substrate (Substrate) or a leadframe (Leadframe), and a plurality of solder balls (Solder Ball) or nail feet (Leader) are provided on the back side as output/input, to be electrically connected to a On the carrier board, such as: printed circuit board (Printed circuit board; PCB), flexible printed circuit board (FlexiblePrinted Circuits; FPC) or motherboard. In addition, the stacked chip package structure 100 can also be provided with a gold finger on the front or back of the first substrate 110 as an output/input, and is electrically connected to a slot of an electronic device in a plug-in manner.

As shown in Fig. 1A and Fig. 1B, the first substrate 110 of the present embodiment is for example made of dielectric material, for example: BT (Bismaleimide Triazine) thermosetting resin material, epoxy resin, pottery or organic glass fiber, and set There is at least one bonding pad 111 (Bonding Pad) and a circuit (not shown), wherein the bonding pad 111 is used for the second wiring 160 to be connected. In some embodiments, the first substrate 110 may also be provided with passive components (not shown), such as capacitors, inductors or resistors, and the passive components may be disposed on the first substrate 110; or, embedded in the first substrate 110 In the process, an integrated passive component substrate is formed.

As shown in FIG. 1A and FIG. 1B , the first chip 130 of this embodiment is bonded on the first substrate 110. In this embodiment, the first chip 130 can be disposed on the first substrate 110 by surface mount (SMT) method. superior. Before disposing the first chip 130 on the first substrate 110, the first chip 130 may pre-form at least one conductive bump 131 (such as a solder ball) on the front side of the first chip 130 (that is, the active surface of the first chip 130 ), so that the second substrate 120 can be electrically connected to the front surface of the first chip 130 through the conductive bump 131, wherein the material of the conductive bump 131 can be tin, aluminum, nickel, silver, copper, indium or the above-mentioned alloy.

As shown in FIG. 1A and FIG. 1B, the second substrate 120 of this embodiment is made of, for example, a dielectric material, such as: BT thermosetting resin material, epoxy resin, ceramic or organic glass fiber, and is provided with a pad 121 . The pads 121 are disposed on opposite upper and lower surfaces of the second substrate 120 so as to be electrically connected to the first chip 130 and the second chip 140 respectively, and can be connected by the second wiring 160 . In this embodiment, the second substrate 120 is provided with a slot 122 exposing a part of the surface of the first chip 130 , wherein the notch area of the slot 122 is larger than the area of the second chip 140 . At this time, the second chip 140 can be disposed in the groove 122 of the second substrate 120, and bonded to a part of the surface of the first chip 130, for example, by using a surface-mounting method, so that the second substrate 120 is disposed on the second chip 140. around.

As shown in Figure 1A and Figure 1B, the first wire 150 and the second wire 160 of this embodiment are, for example, gold wires, silver wires, copper wires or aluminum wires, and the first wires 150 are respectively connected to the second chip 140 and the second chip 140. The pads 121 of the substrate 120 are thus electrically connected to the second chip 140 and the second substrate 120 . The second wires 160 are respectively connected to the pads 121 of the first substrate 110 and the second substrate 120 to form an electrical connection between the first substrate 110 and the second substrate 120 . The material of the encapsulant 170 is, for example: epoxy resin, PMMA, polycarbonate (Polycarbonate) or silica gel, which is formed on the first substrate 110 to cover and seal the first chip 130, the second chip 140, the second The substrate 120 , the first wiring 150 and the second wiring 160 can thus form the stacked chip packaging structure 100 of this embodiment.

When manufacturing the stacked chip packaging structure 100 of this embodiment, firstly, the first chip 130 is provided, then, the first chip 130 is arranged on the first substrate 110, and then, the second chip 140 and the second substrate 120 are arranged on the second substrate 110. On a chip 110, then, carry out the wiring step, thereby connect the first wiring 150 between the second chip 140 and the second substrate 120, and connect the second wiring 160 between the first substrate 110 and the second substrate 120, Then, an encapsulant 170 is formed to seal the first chip 130 , the second chip 140 , the second substrate 120 , the first wiring 150 and the second wiring 160 , thus forming the stacked chip packaging structure 100 .

It should be noted that when the second chip 140 and the second substrate 120 are arranged, the second substrate 120 can be bonded to the conductive bumps 131 of the first chip 130 first, and then the second chip 140 can be bonded to the exposed surface of the first chip 130. Alternatively, the second chip 140 may be bonded on the first chip 130 first, and then the second substrate 120 may be bonded on the conductive bump 131 of the first chip 130 and located around the second chip 140 .

Since the first chip 130 and the second chip 140 of this embodiment can be connected to the second substrate 120 by using conductive bumps (Bump) and bonding wires respectively, and the second substrate 120 is electrically connected to the first substrate 110, using the second The design of the internal circuit (Inter Connecting) of the substrate 120 enables the first and second chips to be electrically connected to the first substrate through the second substrate, so that the first substrate 110 does not need to be provided with too many pads 111, which can avoid existing In the stacked chip packaging structure, the wires are concentratedly soldered to the first substrate 110 , which can solve the problem that the first substrate 110 is too large or the pads 111 are too densely arranged. Therefore, the stacked chip packaging structure 100 and its manufacturing method of the present embodiment can minimize the volume of the packaging structure and ensure the yield of the manufacturing process.

Please refer to FIG. 2A and FIG. 2B , FIG. 2A is a schematic cross-sectional view of a stacked chip packaging structure according to a second embodiment of the present invention, and FIG. 2B is a schematic top view of a stacked chip packaging structure according to a second embodiment of the present invention. Compared with the first embodiment, the second substrate 120b of the stacked chip packaging structure 100b of the second embodiment may not be provided with a slot 122, and the second substrate 120b and the second chip 140 are both connected to the first chip 130, And the second substrate 120b is located on one side of the second chip 140, and is electrically connected to the conductive bump 131 on the first chip 130, and is electrically connected to the connection between the second chip 140 and the second substrate 120b through the first wire 150. between the pads 121, and electrically connect the first substrate 110 and the second substrate 120b through the second wiring 160, so that the first chip 130 and the second chip 140 can be electrically connected to the second substrate 120b, and then electrically connected to the second substrate 120b. A substrate 110 is used to minimize the volume of the packaging structure and ensure the yield of the manufacturing process.

Please refer to FIG. 3A and FIG. 3B , FIG. 3A is a schematic cross-sectional view of a stacked chip packaging structure according to a third embodiment of the present invention, and FIG. 3B is a schematic top view of a stacked chip packaging structure according to a third embodiment of the present invention. Compared with the second embodiment, the stacked chip packaging structure 100c of the third embodiment is provided with two second substrates 120c, the two second substrates 120c and the second chip 140 are connected to the first chip 130, and the two second The substrate 120c is located on both sides of the second chip 140, and is electrically connected to the conductive bumps 131 on the first chip 130, and is electrically connected to the pads of the second chip 140 and the second substrate 120c through the first wiring 150 121, and electrically connect the first substrate 110 and the second substrate 120c through the second wiring 160, so the first chip 130 and the second chip 140 can be electrically connected to the second substrate 120c, and then electrically connected to the first The substrate 110 is used to minimize the volume of the packaging structure and ensure the yield of the manufacturing process.

It can be seen from the above-mentioned embodiments of the present invention that the stacked chip packaging structure of the present invention can avoid the situation that the existing wiring is concentratedly soldered to a single substrate, and can solve the problem of too large substrate area or too densely arranged pads, so it can be miniaturized Encapsulate the volume of the structure and ensure the yield of the manufacturing process.

Although the present invention is disclosed above with the best embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the claims.

Claims (10)

1. A stacked chip packaging structure, characterized in that it comprises at least: a first substrate; a first chip disposed on the first substrate; a second chip disposed on the first chip; at least one second substrate, disposed on the first chip, and electrically connected to the first chip and the first substrate; at least one first wire connected between the second chip and the second substrate; at least one second wire connected between the first substrate and the second substrate; and An encapsulant is formed on the first substrate and covers the first chip, the second chip, the second substrate, the first wiring and the second wiring. 2 . The stacked chip package structure according to claim 1 , wherein the second substrate is provided with a slot, and the second chip is disposed in the slot and bonded to the first chip. 3. The stacked chip package structure as claimed in claim 1, wherein the second substrate is located at one side of the second chip. 4 . The stacked chip package structure as claimed in claim 1 , wherein the stacked chip package structure is provided with two second substrates, which are respectively located on two sides of the second chip. 5. The stacked chip package structure as claimed in claim 1, wherein the first substrate is provided with at least one passive component. 6 . The stacked chip package structure as claimed in claim 1 , wherein the first chip is provided with at least one conductive bump for electrically connecting to the second substrate. 7. A method for manufacturing a stacked chip packaging structure, characterized in that it at least includes: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip and the first substrate; connecting at least one first wire between the second chip and the second substrate; connecting at least one second wire between the first substrate and the second substrate; and An encapsulant is formed on the first substrate to cover the first chip, the second chip, the second substrate, the first wiring and the second wiring. 8. The method of manufacturing a stacked chip package structure according to claim 7, wherein the step of arranging at least one second substrate at least comprises: A second substrate is arranged on one side of the second chip. 9. The method of manufacturing a stacked chip package structure according to claim 7, wherein the step of arranging at least one second substrate at least comprises: Two second substrates are arranged on two sides of the second chip. 10. The manufacturing method of the stacked chip packaging structure according to claim 7, further comprising at least: At least one conductive bump is formed on the first chip to be electrically connected to the second substrate.

Images