CN101527319B - Microcrystalline silicon thin film transistor structure and manufacturing method thereof - Google Patents
Microcrystalline silicon thin film transistor structure and manufacturing method thereof Download PDFInfo
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- CN101527319B CN101527319B CN2008100820700A CN200810082070A CN101527319B CN 101527319 B CN101527319 B CN 101527319B CN 2008100820700 A CN2008100820700 A CN 2008100820700A CN 200810082070 A CN200810082070 A CN 200810082070A CN 101527319 B CN101527319 B CN 101527319B
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Abstract
The invention provides a microcrystalline silicon thin film transistor structure and a manufacturing method thereof.A reversal channel is formed at an upper interface of a microcrystalline silicon active layer and is separated from a nucleation layer of a lower interface of the microcrystalline silicon active layer. The inversion channel is formed in the interface crystalline thin film above the microcrystalline silicon active layer, so that the microcrystalline silicon thin film transistor has better electrical property and reliability.
Description
Technical field
The present invention is about a kind of microcrystalline silicon thin film transistor and manufacture method thereof; Particularly relevant for a kind of gate type microcrystalline silicon thin film transistor and manufacture method thereof of going up.
Background technology
Low-temperature polysilicon film transistor (LTPS-TFTs) is compared with traditional amorphous silicon film transistor (a-SiTFTs), has higher electron mobility (electron mobility) and reaches reliability (reliability) preferably.Yet many at present employing high temperature solid-state crystallisations (solid phase crystallization) or the high laser crystallization method (excimer laser annealing) of equipment cost are carried out the polysilicon membrane manufacturing process.The required crystallization temperature of solid-phase crystallization method is higher, must be with Silicon Wafer or quartz wafer etc. as substrate, and cost is expensive and be unfavorable for the large tracts of land volume production.Though the laser crystallization method can reduce crystallization temperature, the board equipment cost is high and production capacity is not high.As for the microcrystalline silicon thin film transistor that utilizes the plasma-assisted chemical vapour deposition system to make, at the low gate type that continues amorphous silicon film transistor traditionally (bottom gate type) component structure.With reference to Fig. 1, generally in the process of growth microcrystalline silicon film (μ c-Si layer) 103, between insulating layer of thin-film 101 and this microcrystalline silicon film 103, can exist the pregnant stratum nucleare of one deck amorphous phase (incubationlayer) 102, cause inversion layer (inversionlayer) channel region of the follow-up microcrystalline silicon thin film transistor element that completes to be formed in the pregnant stratum nucleare 102 of this amorphous phase, have on the crystalline film and can't be formed on, make the element electrical performance not good.
Fig. 2 is the cross section structure schematic diagram of a traditional low gate type microcrystalline silicon thin film transistor, and it comprises a substrate 200, once gate electrode 201, an insulating barrier 202, a microcrystal silicon layer 203, a pair of tool n
+Admixture microcrystal silicon layer 204a and 204b and a pair of source/drain metal electrode 205a and 205b.This time gate electrode 201 is positioned at this substrate 200 tops, and this insulating barrier 202 is positioned at this time gate electrode 201 tops.This microcrystal silicon layer 203 is positioned at this insulating barrier 202 tops, and this is to tool n
+Admixture microcrystal silicon layer 204a and 204b lay respectively at these microcrystal silicon layer 203 tops, this time gate electrode 201 both sides.This lays respectively at this tool n to source/ drain metal electrode 205a and 205b
+Admixture microcrystal silicon layer 204a or 204b top.This electrically contacts (not shown) formation ohmic contact with side's formed thereon respectively to source/drain metal electrode 205a and 205b.The inverting channel district of this low gate type microcrystalline silicon thin film transistor then is formed at the below interface of this insulating barrier 202 and this microcrystal silicon layer 203.Aforementioned conventional low gate type microcrystalline silicon thin film transistor can directly utilize plasma-assisted chemical vapour deposition mode grow up continuously this insulating barrier 202, this microcrystal silicon layer 203 and this is to tool n
+Admixture microcrystal silicon layer 204a or 204b.But in continuous growth thin-film process, can be at the interface generation one deck amorphous phase pregnant stratum nucleare (incubation layer) of this insulating barrier 202 with this microcrystal silicon layer 203, as shown in Figure 1, cause this inverting channel district of this low gate type microcrystalline silicon thin film transistor to be formed on and have on the crystalline film, and make electrical performance not good.
Summary of the invention
The invention provides a kind of microcrystalline silicon thin film transistor structure, it is a kind of gate type microcrystalline silicon thin film transistor design of going up, its inverting channel (inversion channel) is formed in the top interface crystallinity film of its microcrystal silicon active layers, and separate, and then can improve the electron mobility and the electrical reliability thereof of microcrystalline silicon thin film transistor of the present invention with the pregnant stratum nucleare film of amorphous phase that is positioned at this microcrystal silicon active layers below interface.
On the one hand, microcrystalline silicon thin film transistor structure provided by the invention comprises gate electrode on a substrate, a pair of source/drain electrodes, a tool first conductivity admixture microcrystal silicon layer, a microcrystal silicon layer, the insulating barrier and.This is positioned at this substrate top to source/drain electrodes, and this tool first conductivity admixture microcrystal silicon layer lays respectively at each this source/drain electrodes top.This microcrystal silicon layer is positioned at this tool first conductivity admixture microcrystal silicon layer top, and this insulating barrier is positioned at this microcrystal silicon layer top.Should go up gate electrode this to this insulating barrier between the source/drain electrodes above.This has a channel region to this microcrystal silicon layer between the source/drain electrodes and this insulating barrier interface.
On the other hand, microcrystalline silicon thin film transistor structure provided by the invention comprises gate electrode on a substrate, a microcrystal silicon layer, a pair of tool first conductivity admixture microcrystal silicon layer, a pair of source/drain electrodes, the insulating barrier and.This microcrystal silicon layer is positioned at this substrate top, and this is positioned at this microcrystal silicon layer top to the tool first conductivity admixture microcrystal silicon layer.This lays respectively on this tool first conductivity admixture microcrystal silicon layer source/drain electrodes, and this insulating barrier is positioned at this to the source/drain electrodes top.Should go up gate electrode this to this insulating barrier between the source/drain electrodes above.This has a channel region to this microcrystal silicon layer and this insulating barrier interface between the tool first conductivity admixture microcrystal silicon layer.
The channel region of the aforementioned microcrystalline silicon thin film transistor of the present invention is formed at this insulating barrier interface of this microcrystal silicon layer and its top, and separates with the pregnant stratum nucleare of amorphous phase of this microcrystal silicon layer below interface.This channel region has crystalline structure, thereby can promote the electrical performance of this microcrystalline silicon thin film transistor of the present invention.
Again on the other hand, the invention provides a kind of bigrid microcrystalline silicon thin film transistor structure, it comprises that gate electrode reaches gate electrode on a substrate, a resilient coating, a microcrystal silicon layer, a pair of tool first conductivity admixture microcrystal silicon layer, a pair of source/drain electrodes, the insulating barrier.This resilient coating is positioned at this substrate top, and this microcrystal silicon layer is positioned at this resilient coating top.This is positioned at this microcrystal silicon layer top to the tool first conductivity admixture microcrystal silicon layer, and this lays respectively on this tool first conductivity admixture microcrystal silicon layer source/drain electrodes, and this insulating barrier is positioned at this to the source/drain electrodes top.Should go up gate electrode this to this insulating barrier between the source/drain electrodes above, and this time gate electrode is between this substrate and this resilient coating and to going up gate electrode.This has a channel region to this microcrystal silicon layer and this insulating barrier interface between the tool first conductivity admixture microcrystal silicon layer.
In the aforementioned bigrid microcrystalline silicon thin film transistor structure of the present invention, can strengthen aforementioned channels district and this contact area by the design of this time gate electrode to the tool first conductivity admixture microcrystal silicon layer, and then can reduce the series resistance of microcrystalline silicon thin film transistor of the present invention inside, promote the electrical of this microcrystalline silicon thin film transistor.
The present invention also provides a kind of manufacture method of microcrystalline silicon thin film transistor structure, comprise a substrate is provided, form a pair of source/drain electrodes in this substrate top, form a pair of tool first conductivity admixture microcrystal silicon layer respectively on this source/drain electrodes, form a microcrystal silicon layer in this to tool first conductivity admixture microcrystal silicon layer top, form an insulating barrier in this microcrystal silicon layer top, and form on one gate electrode in this to this insulating barrier top between the source/drain electrodes, and then form the interface of a microcrystal silicon channel region this microcrystal silicon layer and this insulating barrier between this is to source/drain electrodes.
The present invention also provides the manufacture method of another kind of microcrystalline silicon thin film transistor structure, comprise a substrate is provided, form a microcrystal silicon layer in this substrate top, form a pair of tool first conductivity admixture microcrystal silicon layer in this microcrystal silicon layer top, form a pair of source/drain electrodes respectively on this tool first conductivity admixture microcrystal silicon layer, form an insulating barrier in this to source/drain electrodes top, and form on one gate electrode in this to this insulating barrier top between the source/drain electrodes, and then form microcrystal silicon channel region interface between this microcrystal silicon layer and this insulating barrier between this is to source/drain electrodes.
Description of drawings
Fig. 1 shows when a microcrystal silicon layer is grown up above an insulating barrier, can have the pregnant stratum nucleare of an amorphous phase between this microcrystal silicon layer and this insulating barrier;
Fig. 2 is a traditional low gate type microcrystalline silicon thin film transistor cross section structure schematic diagram;
Fig. 3 is the cross section structure schematic diagram of first specific embodiment of microcrystalline silicon thin film transistor of the present invention;
Fig. 4 is the cross section structure schematic diagram of second specific embodiment of microcrystalline silicon thin film transistor of the present invention;
Fig. 5 is the cross section structure schematic diagram of the 3rd specific embodiment of microcrystalline silicon thin film transistor of the present invention.
Drawing reference numeral:
The 101----insulating barrier
308,408,509----conductivity weld pad
The pregnant stratum nucleare of 102----amorphous phase
The 103----microcrystal silicon layer
200,300,400, the 500----substrate
201, gate electrode under the 501----
202,305,405, the 506----insulating barrier
203,304,402, the 503----microcrystal silicon layer
204a，204b，303a，303b，403a，403b，504a，504b
----tool n
+The admixture microcrystal silicon layer
205a，205b，302a，302b，404a，404b，505a，505b
----source/drain metal electrode
301,401, the 502----resilient coating
306,406, the last gate electrode of 507----
307,407,508----electrically contacts
Embodiment
The present invention is by the different last gate type microcrystalline silicon thin film transistor structure of design, to promote the electrical and reliability of microcrystalline silicon thin film transistor of the present invention.Below will and cooperate various not the same gate type microcrystalline silicon thin film transistor structures of graphic detailed description the present invention and manufacture method thereof by various specific embodiments.
Fig. 3 is the cross section structure schematic diagram of first specific embodiment of microcrystalline silicon thin film transistor of the present invention.In first specific embodiment, at first above a substrate 300, for example metal substrate, glass substrate or plastic base form a resilient coating 301.This resilient coating 301 can be silicon nitride (SiN
x) layer, silica (SiO
x) layer or silicon oxynitride (SiN
xO
y) layer.Then, form a pair of source/ drain metal electrode 302a and 302b in these resilient coating 301 tops.Form a pair of tool n
+Admixture microcrystal silicon layer 303a and 303b lay respectively at this source/ drain metal electrode 302a or 302b top.This is to tool n
+The manufacture method of admixture microcrystal silicon layer 303a and 303b can add PH in its microcrystal silicon layer deposition process
3Gas, and obtain a tool n
+The admixture microcrystal silicon layer carries out pattern etching again, to form this to tool n
+Admixture microcrystal silicon layer 303a and 303b.In addition, this is to tool n
+Admixture microcrystal silicon layer 303a and 303b also can a pair of p
+The admixture microcrystal silicon layer replaces, and for example can add B in its microcrystal silicon layer deposition process
2H
6Gas, and obtain a tool p
+The admixture microcrystal silicon layer carries out pattern etching again, to form this to tool p
+The admixture microcrystal silicon layer.Then, form a microcrystal silicon layer (μ c-Si layer) 304 in this to tool n
+Admixture microcrystal silicon layer 303a and 303b top form for example silicon nitride (SiN of an insulating barrier 305
x) layer, silica (SiO
x) layer or silicon oxynitride (SiN
xO
y) layer on this microcrystal silicon layer 304.306 pairs of gate electrodes should be to these insulating barrier 305 tops, zone between source/drain metal electrode 302a and the 302b in the formation one.Should go up gate electrode 306 can be a metal gates.This insulating barrier 305, this microcrystal silicon layer 304 and this tool n are passed in a pair of electrical contact 307 respectively
+Admixture microcrystal silicon layer 303a or 303b, and form ohmic contact with this source/drain metal electrode 302a or 302b.Each electrically forms a conductivity weld pad 308 in contact 307 tops, electrically conducts to set up with the external world.The zone that 305 pairs of this insulating barriers should be gone up gate electrode 306 belows is for the gate insulator of doing this microcrystalline silicon thin film transistor, and an inverting channel district of this microcrystalline silicon thin film transistor then is formed at should be to the interface of these microcrystal silicon layer 304 tops, zone and this insulating barrier 305 between source/drain metal electrode 302a and the 302b.Therefore, gate type microcrystalline silicon thin film transistor structure design on mat the present invention first specific embodiment can make this inverting channel district be formed on the crystallinity film, and and between these microcrystal silicon layer 304 belows and this resilient coating 301 the pregnant stratum nucleare of amorphous phase of interface separate.Thus, the present invention should go up gate type microcrystalline silicon thin film transistor channel region can have preferable electron mobility, and then can improve the electrical and reliability of gate type microcrystalline silicon thin film transistor on this.
Fig. 4 is the cross section structure schematic diagram of second specific embodiment of microcrystalline silicon thin film transistor of the present invention.In second specific embodiment, at first form a resilient coating 401 in a substrate 400 tops, this substrate 400 for example is metal substrate, plastic base or glass substrate, and this resilient coating 401 can be silicon nitride (SiN
x) layer, silica (SiO
x) layer or silicon oxynitride (SiN
xO
y) layer.Then, form a microcrystal silicon layer 402, form a pair of tool n in these resilient coating 401 tops
+Admixture microcrystal silicon layer 403a and 403b are in these microcrystal silicon layer 402 tops.This is to tool n
+The manufacture method of admixture microcrystal silicon layer 403a and 403b can add PH in its microcrystal silicon layer deposition process
3Gas, and obtain a tool n
+The admixture microcrystal silicon layer carries out pattern etching again, to form this to tool n
+Admixture microcrystal silicon layer 403a and 403b.In addition, this is to tool n
+Admixture microcrystal silicon layer 403a and 403b also can a pair of p
+The admixture microcrystal silicon layer replaces, and for example can add B in its microcrystal silicon layer deposition process
2H
6Gas, and obtain a tool p
+The admixture microcrystal silicon layer carries out pattern etching again, to form this to tool p
+The admixture microcrystal silicon layer.Then, form a pair of source/ drain metal electrode 404a and 404b respectively at this tool n
+Admixture microcrystal silicon layer 403a or 403b top.Form for example silicon nitride (SiN of an insulating barrier 405
x) layer, silica (SiO
x) layer or silicon oxynitride (SiN
xO
y) layer in this to source/ drain metal electrode 404a and 404b top.Then, form on one gate electrode 406 in to these insulating barrier 405 tops, zone between should be to source/drain metal electrode 404a and 404b.Should go up gate electrode 406 can be a metal electrode.A pair of electrical contact 407 is passed this insulating barrier 405 respectively and is formed ohmic contact with this source/drain metal electrode 404a or 404b.Each electrically forms a conductivity weld pad 408 in contact 407 tops, electrically conducts to set up with the external world.The zone that 405 pairs of this insulating barriers should be gone up gate electrode 406 belows is for the gate insulator of doing this microcrystalline silicon thin film transistor, and an inverting channel district of this microcrystalline silicon thin film transistor then is formed at should be to the interface of these microcrystal silicon layer 402 tops, zone and this insulating barrier 405 between source/drain metal electrode 404a and the 404b.Therefore,, this inverting channel district is formed on the crystallinity film by gate type microcrystalline silicon thin film transistor structure design on the present invention's second specific embodiment, and and between these microcrystal silicon layer 402 belows and this resilient coating 401 the pregnant stratum nucleare of amorphous phase of interface separate.
Fig. 5 is the cross section structure schematic diagram of one the 3rd specific embodiment of microcrystalline silicon thin film transistor of the present invention, and it is a kind of bigrid microcrystalline silicon thin film transistor structure design.In the 3rd specific embodiment, form at first that gate electrode 501 is in a substrate 500 tops, this substrate 500 for example is metal substrate, plastic base or glass substrate.This time gate electrode 501 can be a metal gates.Then, form a resilient coating 502 in this time gate electrode 501 tops, this resilient coating 502 can be silicon nitride (SiN
x) layer, silica (SiO
x) layer or silicon oxynitride (SiN
xO
y) layer.Form a microcrystal silicon layer 503 in these resilient coating 502 tops, then form a pair of tool n
+Admixture microcrystal silicon layer 504a and 504b are in these microcrystal silicon layer 503 tops and respectively to descending gate electrode 501 both sides.This is to tool n
+The manufacture method of admixture microcrystal silicon layer 504a and 504b can add PH in its microcrystal silicon layer deposition process
3Gas, and obtain a tool n
+The admixture microcrystal silicon layer carries out pattern etching again, to form this to tool n
+Admixture microcrystal silicon layer 504a and 504b.In addition, this is to tool n
+Admixture microcrystal silicon layer 504a and 504b also can a pair of p
+The admixture microcrystal silicon layer replaces, and for example can add B in its microcrystal silicon layer deposition process
2H
6Gas, and obtain a tool p
+The admixture microcrystal silicon layer carries out pattern etching again, to form this to tool p
+The admixture microcrystal silicon layer.Afterwards, form a pair of source/ drain metal electrode 505a and 505b respectively at this tool n
+Admixture microcrystal silicon layer 504a or 504b top.Form for example silicon nitride (SiN of an insulating barrier 506
x) layer, silica (SiO
x) layer or silicon oxynitride (SiN
xO
y) layer in this to source/ drain metal electrode 505a and 505b top.Afterwards, 507 pairs of gate electrodes should descend gate electrode 501 and be formed at this insulating barrier 506 tops in the formation one.Should go up gate electrode 507 can be a metal gates.Form that this insulating barrier 506 is passed in a pair of electrical contact 508 respectively and form ohmic contact with this source/drain metal electrode 505a or 505b.Each electrically forms a conductivity weld pad 509 in contact 508 tops, electrically conducts to set up with the external world.This insulating barrier 506 between this to the zone between source/drain metal electrode 505a and the 505b for doing the gate insulator of this bigrid microcrystalline silicon thin film transistor, and an inverting channel district is formed at this interface to these microcrystal silicon layer 503 tops and this insulating barrier 506 between source/drain metal electrode 505a and the 505b.This inverting channel district separates with the pregnant stratum nucleare of an amorphous phase in the interface that is present in these microcrystal silicon layer 503 belows and this resilient coating 502.
Be used as when putting on this gate electrode 507 with voltage, the electric field that gate electrode 507 produces on this and this can be covered source/ drain metal electrode 505a and 505b by this source/drain metal electrode 505a and the overlapping part of 505b.In the 3rd specific embodiment, add a complementary following gate electrode 501, can strengthen this inverting channel district and this is to tool n
+The contact area of admixture microcrystal silicon layer 504a and 504b, and then can reduce the series resistors inside of microcrystalline silicon thin film transistor of the present invention, and further promote this transistor unit electrically.
Microcrystalline silicon thin film transistor structure of the present invention can utilize plasma chemical vapor deposition process grow up continuously aforementioned dielectric layer, microcrystal silicon layer and tool conductivity admixture microcrystal silicon layer, for example has n+ admixture microcrystal silicon layer or a tool p+ admixture microcrystal silicon layer.The manufacture method of the aforementioned microcrystalline silicon thin film transistor of the present invention can be avoided numerous and diverse implanting ions of traditional low-temperature polysilicon film transistor and activation manufacturing process.Moreover the present invention utilizes plasma chemical vapor deposition process grow up continuously aforementioned dielectric layer, microcrystal silicon layer and tool conductivity admixture microcrystal silicon layer, is beneficial to large tracts of land volume production thin-film transistor element, has the even equal property of good element of large tracts of landization again concurrently.Microcrystalline silicon thin film transistor structure provided by the invention and manufacture method thereof are fit to be applied in the making of organic LED panel.
The above is specific embodiments of the invention only, is not in order to limit claim scope of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the claim scope.
Claims (15)
1. a microcrystalline silicon thin film transistor structure is characterized in that, described microcrystalline silicon thin film transistor structure comprises:
One substrate;
One microcrystal silicon layer is positioned at described substrate top;
The a pair of tool first conductivity admixture microcrystal silicon layer is positioned at described microcrystal silicon layer top;
A pair of source/drain electrodes lays respectively on the described tool first conductivity admixture microcrystal silicon layer;
One insulating barrier, be positioned at described this to source/drain electrodes top; And
Gate electrode on one, described this to the described insulating barrier between the source/drain electrodes above;
Wherein said this has a channel region to described microcrystal silicon layer and described insulating barrier interface between the tool first conductivity admixture microcrystal silicon layer.
2. microcrystalline silicon thin film transistor structure as claimed in claim 1 is characterized in that, described microcrystalline silicon thin film transistor structure more comprises a resilient coating between described microcrystal silicon layer and described substrate.
3. microcrystalline silicon thin film transistor structure as claimed in claim 1 is characterized in that described substrate comprises metal substrate, glass substrate or plastic base.
4. microcrystalline silicon thin film transistor structure as claimed in claim 1 is characterized in that, the described tool first conductivity admixture microcrystal silicon layer is a n+ type admixture microcrystal silicon layer or a p+ type admixture microcrystal silicon layer.
5. microcrystalline silicon thin film transistor structure as claimed in claim 1 is characterized in that described insulating barrier comprises silicon nitride, silica or silicon oxynitride.
6. microcrystalline silicon thin film transistor structure as claimed in claim 1 is characterized in that, described this be metal electrode to source/drain electrodes.
7. microcrystalline silicon thin film transistor structure as claimed in claim 1 is characterized in that, described upward gate electrode is a metal gates.
8. microcrystalline silicon thin film transistor structure as claimed in claim 1, it is characterized in that, described microcrystalline silicon thin film transistor structure more comprise a resilient coating gate electrode above the described substrate and once between described resilient coating and the described substrate also corresponding described on gate electrode.
9. microcrystalline silicon thin film transistor structure as claimed in claim 8 is characterized in that, described upward gate electrode and described gate electrode down are metal electrode.
10. the manufacture method of a microcrystalline silicon thin film transistor, described method comprises:
One substrate is provided;
Form a microcrystal silicon layer in described substrate top;
Form a pair of tool first conductivity admixture microcrystal silicon layer in described microcrystal silicon layer top;
Form a pair of source/drain electrodes respectively on the described tool first conductivity admixture microcrystal silicon layer;
Form an insulating barrier in described this to source/drain electrodes top; And
Form on one gate electrode in described this to the described insulating barrier top between the source/drain electrodes.
11. the manufacture method of microcrystalline silicon thin film transistor as claimed in claim 10 wherein more comprised before described microcrystal silicon layer forms and forms gate electrode on described substrate.
12. the manufacture method of microcrystalline silicon thin film transistor as claimed in claim 10 wherein more comprised formation one resilient coating on described substrate before described microcrystal silicon layer forms.
13. the manufacture method of microcrystalline silicon thin film transistor as claimed in claim 12 wherein after the formation of described gate electrode down, then forms a resilient coating in described gate electrode down top.
14. the manufacture method of microcrystalline silicon thin film transistor as claimed in claim 10, wherein said this be n+ type admixture microcrystal silicon layer or p+ type admixture microcrystal silicon layer to the tool first conductivity admixture microcrystal silicon layer.
15. the manufacture method of microcrystalline silicon thin film transistor as claimed in claim 14 wherein adds PH in forming described this manufacturing process to the tool first conductivity admixture microcrystal silicon layer
3Gas or B
2H
6Gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100820700A CN101527319B (en) | 2008-03-05 | 2008-03-05 | Microcrystalline silicon thin film transistor structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100820700A CN101527319B (en) | 2008-03-05 | 2008-03-05 | Microcrystalline silicon thin film transistor structure and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN101527319A CN101527319A (en) | 2009-09-09 |
| CN101527319B true CN101527319B (en) | 2010-12-15 |
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|---|---|---|---|
| CN2008100820700A Expired - Fee Related CN101527319B (en) | 2008-03-05 | 2008-03-05 | Microcrystalline silicon thin film transistor structure and manufacturing method thereof |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0473988A1 (en) * | 1990-08-29 | 1992-03-11 | International Business Machines Corporation | Method of fabricating a thin film transistor having amorphous/polycrystalline semiconductor channel region |
-
2008
- 2008-03-05 CN CN2008100820700A patent/CN101527319B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0473988A1 (en) * | 1990-08-29 | 1992-03-11 | International Business Machines Corporation | Method of fabricating a thin film transistor having amorphous/polycrystalline semiconductor channel region |
Non-Patent Citations (2)
| Title |
|---|
| JP平2-263474A 1990.10.26 |
| JP平9-181326A 1997.07.11 |
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