CN101507145A - System and method for performing concatenation of different routing channels - Google Patents
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Abstract
A system for performing a Local Central Authorization Service (LCAS) in a network system is provided. The system has a data adjuster configured to adjust input data bytes according to the set of branches. The system also includes an LCAS control manager configured to generate a de-sequencing control command in response to data input from the data aligner. The system further includes a de-sequencer configured to de-sequence data input from the data aligner according to de-sequencing control commands received from the LCAS control manager.
Description
Priority request
The application requires in the U.S. Provisional Application No.60/645 of submission on January 24th, 2005,841 priority.
Background technology
VCAT
The present invention is directed to hardware and software system, method, equipment and the structure of the novelty of virtual concatenation signal form, comprise being used to make TDM (time division multiplexing) network can adapt to the New Deal of data communication better.
Such system is suitable for being undertaken by Synchronous Optical Network (SONET) and synchronous digital level (SDH) effective transmission of data service.Term " TDM " can be used to represent SONET and SDH.New Deal is included in the broadband low order (LO) that illustrates in the T1.105 appendix and high-order (HO) virtual concatenation (VCAT) and Link Capacity Adjustment Scheme (LCAS) G.7042, and described New Deal allows the TDM network better to adapt to data communication.International Telecommunication Union has announced and has considered LCAS and at the standard of virtual concatenation signal.G.7042/Y.1305, the source end and the desired state of receiving terminal of network linking have been stipulated in ITU-T suggestion, and have stipulated the control information of switching between the source end of link and receiving terminal, so that can adjust neatly for the virtual concatenation signal.G.783 and at the ITU suggestion of OTN G.709 and obtain regulation G.798 the information field of reality that is used for transmitting control signal by transmission network is at the ITU-T suggestion of SDH G.707.All these are approved at large for a person skilled in the art and are well-known and be that effectively the purpose for this application merges by reference, and it comprises the regulation of generally using that is included in wherein (quote ITU-T with reference to).
Virtual concatenation provides and has sent and received the ability of several discrete STS/VC fragments as signal flow.This group STS/VC is called as virtual concatenation group (VCG).Identical sample before utilizing in the paragraph can be the VCAT load with the STS-3c load transfer, and discontinuously maps to three STS-1, as shown in Figure 7.
The VCAT symbol (notation) that is used for SONET is STS-n-mv, and wherein, n is the size that is used to transmit the discontinuous STS fragment of whole VCG.The value of m is the entire quantity of n fragment, and it constitutes whole VCG." v " represents that this is a VCAT load.So in aforementioned sample, VCG should be a STS-1-3v stream.
Three STS-1 have constituted the whole stream of STS-3.STS-12c can be decomposed into STS-1 or STS-3c fragment; Therefore, it can be used as STS-1-12v or STS-3c-4v transmission.The VCAT symbol that is used for SDH is VC-n-mv, and is wherein, defined identical among the definition of n and m and the SONET.For example, the VC-4-16c load can be mapped to VC-3-16v or VC-4-4v.
Unlike non-public cascade, for example, STS-24c/VC-4-8c is because the order of multiframe rearranges and indicate the path overhead field (path overhead field) by the H4 byte to carry out, so VCAT only need implement in channel terminal device.Path overhead only is used in the source and destination place of TDM stream.Because VCAT is made up of STA-1/VC-3 and STS-3c/VC-4, its all SONST/SDH equipment by reality is supported, so traditional non-channel end transmission equipment does not need to support VCAT.Therefore, utilize gain (utilization gain) to enjoy, and need not as early stage the explanation, make circuit be mapped to bigger fixedly cascade, make less adfluxion synthesize bigger fixedly cascade by the TDM network of remainder.
Although another feature---it does not have specified device---that VCAT supports indirectly is to provide the nothing of STS/VC path to interrupt adjusting (hitless resizing).LCAS is that a kind of the definition do not have the scheme of interrupting adjustment.Because the VCAT load is decomposed into several fragments, as discussing in the paragraph afterwards, increasing or remove bandwidth can be by increasing to fragment existing stream (existingflow) or removing from existing stream and finish.Though VCAT does not specify protection scheme, the LCAS scheme can also provide protection control.
Finally, be used for virtual tributary (VT)-1.5 (1.544Mbps) and VC-12 (2.048Mbps) even other broadbands support also effectively for more closely-spaced selection, this is low order (LO) VCAT.
LCAS
The bandwidth profile that changes the user is a problem always.Take effective measure, it is changed and determines that it works on and need not anyone notice be important.A lot of such requirements of user, and a lot of people writes on it in their service contract.The preferred embodiments that increases or reduce bandwidth occurs in old when all having enough bandwidth with new path for what coexist between the amortization period.When reaching two circuit, carry out bridge joint-upset (bridge-and-roll) the user is moved to new circuit, but when not having enough bandwidth, must before new circuit is set up, remove old circuit, so just produce user's loss for two coexistence streams.The purpose of LCAS is to make the change bandwidth to become a kind of simple and safe task.
LCAS provides a kind of controlling mechanism, and it is used for the increase of " nothing is interrupted " or reduces the bandwidth needs of the capacity of VCG link with satisfied application.Interim removing for the branch road link (member link) of experiencing failure also is provided.The LCAS supposition, when beginning, increasing or reducing at capacity, the modification of the end to end path of the VCG branch road that each is independent is responsible for by network and entity management system.That is, LCAS provides a kind of mechanism of bandwidth compensation, but it is not to determine the controlling mechanism of when and why operating.
The LCAS feature comprises: when the automatic removing of the bandwidth change that increases its segmentation bandwidth, nothing interruption, failure VCG fragment, can increase and reduce the VCG capacity, and the VCG that need not clear all, simultaneously, dynamically replaced the fragment of failing with the work fragment, LCAS VCG can carry out mutual operation with non-LCASVCG; That is, the LCAS transmitter can switch to non-LCAS receiver, and vice versa, and the unidirectional control of VCG has provided the ability with asymmetric connection, and a lot of other features.These features provide the benefit that can improve transmission network greatly to list.LCAS provides the flexibility that increases and remove bandwidth capacity among the VCG, and does not influence service or removal VCG.So not only saved the make-up time, and eliminated the restriction of working during " keeping window (maintenance widow) ".In addition, need planning seldom, because the engineer only needs to find out for circuit the bandwidth of increase, rather than bridge joint-desired additional bandwidth overturns.
Another crucial benefit is the bandwidth in LCAS increase and the deletion VCG increment.Allow provider that wider SLA is provided like this.Equally, increasing the SLA mark sheet is the ability that LCAS increases bandwidth as requested.Therefore, it helps to produce the bandwidth change based on customer requirements---another advantage for service provider.
Except management compensation and customer requirements, LCAS can move in conjunction with signaling protocol, dynamically to change the communication stream in the network.For its application is whole network (network-wide) or based on the load balancing (load balancing) of entire scope (span-based).In addition, load balancing/network recovery will be to those the client side's skews for the high efficiency payment.The load-share compensation scheme can be a kind of formation of service potentially, when packet grade prioritization and congestion control scheme in conjunction with the time, produce novel enhanced service supply.
By LCAS, the VCAT flexibility also will be enhanced.This has just improved greatly, and supplier provides flexibly and the ability of efficient SLA, and dynamic TDM path recovery also is provided.
SONET/SDH (" Synchronous Optical Network/synchrodata level ") transmission level is designed to offer a kind of utility unit of telecommunications carrier wave, in order to using time-division multiplexing bearing sound and private leased circuit service.In its initial design, SONET/SDH keeps the have limited series data rate fixing hierarchical structure of (for example, 51Mb/s, 155Mb/s, 622Mb/s, 2.5Gb/s, 10Gb/s, 40Gb/s).Along with the growth of Internet and business data net, and because the expansion of the scope of business and type needs such structure more flexibly with powerful.
The introducing of a series of SONET/SDH technology of future generation, comprise GFP, VCAT and LCAS, the SONET/SDH transmission network is changed into the flexible and effective carrier of data and sound circuit, simultaneously, keep preferential operation and the management function of in the SONET/SDH standard, setting up in order to carry out monitoring and Fault Isolation (fault isolation).GFP, VCAT and LCAS be development abreast, when they combine use, has realized its advantage.They are complimentary to one another, thereby the effective utilization and the control of elasticity bandwidth of transmission sources are provided.Device, sale equipment and testing equipment based on this become increasingly mature, and are interconnected into high-level network.In above-mentioned three kinds of basic technologies each all has unique contribution for SONET/SDH of future generation:
Generic Framing Procedure/GFP (ITU-T G.7041 and G.806) is a kind of easy method for packing to any data type, be used for different bitstream type flexibly mapping advance byte-synchronizing channel.It provides has that every packet is fixed but the effective encapsulation of little expense.The GFP that has two kinds of main types:
GPF (GFP-F) based on frame stores and transmits whole user's frames in single gfp frame.For major part bag type, this is a method for optimizing.
The group encoding signals that transparent GFP (GFP-F) uses by transmission such as memory block field network (perhaps SAN) provides low latency.
Virtual concatenation/VCAT (ITU-T G.707 and G.783) is in conjunction with the inverse multiplexing technology of SONET/SDH passage arbitrarily, thereby has produced the byte synchronous flow.Be unlike in the continuous cascade that needs cascade function in each networking component, VCAT only needs the cascade function on the channel terminal device.VCAT can transmit a kind of load, and this load is not fit to effectively usually by the standard STS-Nc of existing SONET/SDH NE support or the size of VC SPE.The VCAT function only is required on the channel end assembly, rather than on each NE in the passage.VCAT utilizes less bandwidth container to set up bigger bandwidth end-to-end link.Independent container can utilize the compensation that helps different delay between each container to select route separately.
Link Capacity Adjustment Scheme LCAS (ITU-T G.7042, G.806 and G.783) is a kind of signaling mechanism, and it dynamically and do not have and interruptedly be adjusted at the container size of transmitting in the SONET/SDH network with VCAT.This is the expansion of the SONET/SDH channel quantity dynamic change during VCAT is allowed to use, and carries out in the band on the path overhead byte.
Suppose and stipulated the path that LCAS adjusts the bandwidth adjustment on the end points.It also comprises optional fault recovery (failover recovery) feature.
At the edge of SONET/SDH network, can there be equipment such as multiservice provisioning platform (mspp), be used for the Ethernet physical interface that transmits at the SONET/SDH network with adjustment.Remove lead code (preamble) and SFD (start of frame delimiter) in the mac frame, and the GFP load is advanced in content (comprising source and target address, length/type field, MAC data, byte of padding and Frame Check Sequence (frame check sequence)) mapping remaining in the mac frame.Increase the GFP overhead byte, and gfp frame is distributed to VCAT organize (VCG), can utilize the different path of across a network (to note like this, in the OIF world interoperability certificate of inspection (WorldInteroperability Demonstration), the SONET/SDH network can be formed with the multicarrier laboratory by utilizing difference to sell the multi-field of method, apparatus).LCAS signaling intention increases or removes the branch road of VCG link, needs to adjust the bandwidth of using, and in response to the fault or the reparation of VCG branch road link.At network egress MSPP place, mapping is separated in the load of VCG from GFP, rallies with time sequencing, obtains multiplexing on the Ethernet physical interface and transmission.
The service that detects in the interoperability check of the OIF world is adjusted feature and is concentrated on four fields:
The throughput of Ethernet private wire service on the SONET/SDH infrastructure;
Ethernet transmission by adaptive minute speed of GFP and VCAT and full rate;
For the heterogeneous networks feature (difference time-delay) carry out the elasticity adjustment;
Utilize LCAS, to increasing/reduce the immediate reaction of bandwidth requirement and network failure situation;
These test case have not only proved different interactions of selling between the method, apparatus, have also proved the interaction between GFP-F, VCAT and the LCAS inner characteristic.
As the example that VCAT and LCAS use, the example of utilizing the Ethernet service that LCAS can provide by the VCAT system has been shown among Figure 1A-1D.Fig. 1 shows has the Ethernet system that service is provided by VCAT and LCAS.Link between node A and the node Z utilizes the virtual concatenation group transmission ethernet frame of three branch roads, and can be any amount of branch road.Three independently the LCAS agreement monitor reciprocity position continuously, comprising: the LCAS-a of the LCAS-a of node R and node Z carries out session, LCAS-b (R) and LCAS-b (Z) carry out session ... LCAS-n (R) and LCAS-n (Z) carry out session or the like.The LCAS agreement has been set up many structural parameters and the state machine that is used for such system, but it does not have for carry out the concrete enforcement of LCAS function assignment component in specific node.In order to realize communication, each node need send and receiving unit, and it transmits and receive data from for example CP1 and CP2, and a plurality of node is fine.
CP1 sends the ethernet signal of the packet with the node R of being sent to, and in this, it is suitable for data service, and ethernet frame is handled according to Generic Framing Procedure (GFP).Then, according to the process isolated frame of VCAT.
In history, the Multiplexing Technology of packet-oriented, for example IP and Ethernet all can not make frequency band and the granularity (granularity) that is provided by continuous cascade mate well.VCAT is a kind of inverse multiplexing technology, and it allows the granularity of bandwidth and single VC-n unit to increase.At the source node place, the continuous load that VCAT produces equals X times of VC-n.X container of this group is called as virtual container group (VCG), and each independent VC is the part of VCG.Low order virtual concatenation (LO-VCAT) uses X VC11, VC12 or VC2 container (VC11/12/2-X:X equals 1...64) doubly.High-order virtual concatenation (HO-VCAT) uses X VC 3 or VC 4 containers (VC 3/4-X equals 1...256) doubly, and X is provided the load capacity of 48384 or 149760kbit/s doubly.
Virtual concatenation operation with reference to Figure 1A more specifically, shows the Ethernet service that is provided by VCAT/LCAS.Processor CP1 is connected to Ethernet and connects, and in this Ethernet, carries out current control according to Ethernet protocol.According to new agreement, node R is according to the ethernet signal in the virtual concatenation operation reception Generic Framing Procedure, and is adaptive to carry out business, carries out load subsequently and separates.By before cross bar switch (the cross bar switch) dateout,, be shown as traditional STH here in node R according to LCAS agreement executive communication control.As shown in the figure, ethernet frame is additional on the VCAT branch road information, and transfers to node Z by traditional STH.The configuration of node Z is similar to node R, and node Z is configured to receive data by the LCAS operating protocol, and it is synthetic rebuilding data to carry out load, thereby makes the controller CP 2 that receives ethernet signal use these data.By the flow control of Ethernet protocol, this flow control moves similarly or realizes.In order to communicate by letter, each node all has the ability that sends and receive ethernet signal.Utilize virtual concatenation, finish Control on Communication by the LCAS operation, traditional STH can increase its bandwidth and efficient.
With reference to Figure 1B, virtual concatenation goes out with diagrammatic representation, and wherein, for example, continuous load VC3/4V is broken down into X fragment, each fragment have a plurality of sequences with relevant MFI number.Each fragment has X VC 3, virtual concatenation group doubly, and wherein, each fragment is corresponding to specific MFI number and sequence.As can be seen, cascaded series (VCG) is sent separately virtually.
With reference to Fig. 1 C, show VCAT channel by the LCAS management.Between node A and Node B, by VCG (virtual concatenation group of pipe method), signal is sent by X and is received by Rx.Each node has source and the device (sync) synchronous with it, and each also has corresponding LCAS configuration.The NGSDH that LCAS helps network operator to control effectively and is based upon the VCAT website connects.The use of LCAS is not necessarily managed but can improve VCAT.As see, the source and corresponding arranged 4/ free time (idle) with line state between its synchronous device, increase (add)/failure (fail), normal (norm)/ok, DNU/ failure and removing/Ok.Simultaneously, can also see that transmission channel A, B, C and D illustrate with the channel of transmission mode, and respective channels H, I, J and K be depicted as from described source the channel that sends signal to the described device synchronous with it, from Node B to node A.
With reference to Fig. 1 D, show multi-frame K4 (VCAT and LCAS numbering).Shown in the 17-20 position of lower order path overhead in the K4 multi-frame.Equally, in multi-frame, be MFI number, sequence number, control number, control bit, RS-ACK, MST number and CRC-3.Equally, the K4 superframe is shown having corresponding MFI number, sequence number control and CRC-3.(SQ is at-VCG[0...] in sequence indication) MFI: multi-frame counting indication [0...31].The K4 super frame has the time span of 512ms.K4 is the part of LO-PO expense, and per 500 milliseconds are repeated once.In complete multi-frame, send 32 bits, spend 16 milliseconds and repeat once (500 * 32=16ms).Deputy super frame is made of 32 multi-frames, and has spent 512 milliseconds and carry out repetition.In the high-order side, with reference to Fig. 1 E, multi-frame H4 illustrates with the form of VACT and LCAS numbering.H4 is the part of HO-PO (high-order overhead).A4 represents that per 125 milliseconds are carried out repetition.16 milliseconds of the multi-frame costs of 1-6 byte.The multi-frame cost of 4096 complete bytes repeats (125 * 4096=512ms) for 512 milliseconds.
In order to obtain flexible and powerful structure, people had carried out a lot of the trial.Yet, in the legacy system between the hardware and software cutting apart of function be inequitable.Especially, when requiring certain to handle, for example, change not a size and a line state of working group, the instruction in the processing can hinder the branch road state activity.
For example, in the system based on velocity of sound, the ITU among the space G 707 of renewal V-4 requires virtual concatenation.For example, if require 7,000,000 channel, the result of expectation can be 7 1,000,000 a channel.Therefore, need to realize that LCAS is additional.Need change not a size and a line state of working group according to the requirement of standard.In legacy system, such processing is tediously long, and very high for the requirement of processor.For example, the processing of requirement is to check configuration, interruption, order, fault, replacement and other operations.Given new standard-required, system will be born by real-time processing requirements.
Multiplexing by allowing the SONET/SDH channel to carry out with any layout, it all is " suitable dimensions " for various data payloads that virtual concatenation (VCAT) makes transmission pipeline.VCAT decomposition data bag, and they are shone upon the into elementary cell of TDM frame; For example, be used for the STS-1 (51Mb/s) of SONET, and the AU 4 (155Mb/s) that is used for SDH.Such data are followed polymerization in a plurality of data flow of earthquake size, to produce bigger synthetic load, optionally dispose its size to mate the capacity of effective SONET/SDH pipeline.VCAT is applied at the end points place that connects, and this just allows the channel of each use to send individually by traditional transmission network.Usually utilize GFP that data are encapsulated.VCAT (ITU-T G.707 in definition) make up with some little SDH/SONET virtual container (VC) loads, to constitute bigger virtual concatenation group (VCG).VC has three different sizes, and wherein, VC-12 provides about 2Mbit/s, and the about 50Mbit/s of VC-3, and the about 150Mbit/s of VC-4 make that for example the data flow of 8Mbit/s can be made up of 4 VC-12.The SDH/SONET pipeline that produces the fine tuning of these variable capacity has improved the measurability and the efficient of data processing, simultaneously, has also controlled the agreement of service quality (QoS) and customer service level.VCG is used as one group of independent VC and handles, and this just means that each VC can utilize any effective time slot (time slot) by end-to-end path, and VCG recombinates at the other end.For example, the load of above-described 8Mbit/s can be cut apart 4 VC-12 of leap in whole SDH.SONET signal.
For the transfer of data flexibly of being undertaken by SDH/SONET, it is also important that Link Capacity Adjustment Scheme (LCAS), it defines in G.7042 at ITU-T, makes the load of VCG to obtain adjusting by increasing or removing single VC like this.LCAS suggestion provides mechanism for the variation of notice request between two end points, and can lost package, because load capacity has obtained adjustment.
The VCAT of junction link capacity adjusting scheme (LCAS, ITU-T are G.7042) is a kind of worthwhile elastic mechanism, and it allows data, services to cover existing optical transport network.The technology permission carrier wave maximum revenue that these standard utilizations have existed and used.Because the service provider has been subjected to utilizing multiple transmission mechanism to send the challenge of identical (or increasing) service, come into vogue gradually by so measured method of a transmission architecture in conjunction with Ethernet and traditional voice and data service.These require to be even more important by the coverage outside the zone of metropolitan area packet network (metro packet network) covering traditionally for those.Referring to:
Http:// www.haliplex.com.au/multis1600.html
For legacy system and relevant solution, this has just produced a significant problem.In such system, the division of the processing capacity between the hardware and software is not reciprocity.Because such system only is used to transmission, receive and exchanges voice data and setting up only, so there not be the more modern data of realization to send desired efficient.In network system, it is necessary managing apace that branch road link activity moves effectively for system, and it comprises and solves diverse branch road link.For example, if branch road requires the channel of 7 megabits, still receive the channel of 71 megabits, a size and the line state in order to change this group should need be carried out LCAS in addition so.This proposes in G.7042 at ITU-T.According to new ITU standard-required, this must carry out in non operating state, or free of discontinuities is carried out.Yet this standard does not strictly propose how to carry out such scheme.For processor, this is very heavy, and it need detect configuration, needs compiler directive, and in order effectively also to link and provide new standard desired VCAT efficiently, program must be robust (robust).LCAS source of simplifying and receiver (sink) state machine are shown in Fig. 1 F.
Therefore, need a kind of LCAS operated system and method in based on the SONET system environments, carried out in the art, so just provide in the network service more effectively balanced between the hardware and software operation, and this system and method can be carried out LCAS in the mode that is not subjected to real-time processing requirements restriction and operates.As will seeing, the present invention provides such system and method in the mode of exquisiteness.
Description of drawings
Figure 1A-F is the LCAS of background technology and the diagrammatic sketch of relevant network;
Fig. 2 A is the sketch of the system of configuration according to the present invention;
Fig. 3 A-G is the diagrammatic sketch according to source of the present invention and receiver;
Fig. 4 A-E is the diagrammatic sketch according to method of adjustment of the present invention and system;
Fig. 5 is the diagrammatic sketch of ANA;
Fig. 6 is the diagrammatic sketch of LVC;
Fig. 7 is the diagrammatic sketch of DSQ;
Fig. 8 is the diagrammatic sketch of VCT_TX;
Fig. 9 is the diagrammatic sketch of buffer system;
Figure 10 is the diagrammatic sketch that is used for based on the system of the schedule of channel type circulation (calendar round);
Figure 11 is the diagrammatic sketch of buffer system;
Figure 12 is the diagrammatic sketch of VCT adjuster;
Figure 13 is the diagrammatic sketch how the VCT adjuster produces schedule;
Figure 14 resets and how fault mode acts on together and authorize and unauthorized branch road;
Figure 15 is the diagrammatic sketch of main FIFO;
Figure 16 is the diagrammatic sketch of 64 word bytes;
Figure 17 is the diagrammatic sketch of main FIFO in the receiving circuit;
Figure 18 is the diagrammatic sketch how state is reset;
Figure 19 is the diagrammatic sketch that is used for the state diagram of LCAS; And
Figure 20 is the diagrammatic sketch that how to distribute main FIFO.
Embodiment
The present invention relates to a kind of system and method that is used for carrying out the novelty of local central authority service (LCAS), overcome the shortcoming of prior art in network system.This system is many-sided, and provides a lot of features to being used for the VCAT system for transmitting, more specifically but be not limited to those LCAS is provided functional feature.It should be appreciated by those skilled in the art that following embodiment can be used in any system and method, in described system and method, following function and device are useful.
An embodiment of innovative system provides the data in the virtual concatenation process are adjusted, sort and has conciliate the distinct configuration of preface.Such system and process can be used in SONET/SDH transmission processor or the analog, but are not limited to any specific network protocol.More specifically, system and process can be used for having high-order and the low order framer and the processor of virtual concatenation and LCAS function.It should be appreciated by those skilled in the art that the spirit and scope of the invention extend to the application of broad, and in claims and equivalent thereof, define.
Another embodiment of the present invention has proposed the new balance between the hardware and software feature in such system, wherein, has removed loaded down with trivial details processing from process, and has carried out outside courses of action.This carries out LCAS with regard to the permission system with effective and efficient manner more, and has quickened general process.The present invention carries out in based on the system environments of SONET in the environment of LCAS operated system and method and is described, but it should be appreciated by those skilled in the art that the present invention's reality on scope is broad more, and expand between the hardware and software from network service and other are used any system that benefits in the more effective balance.
In one embodiment of the invention, processor is configured to increase and the deletion branch road with effective and efficient manner, and wherein, the processor expense is similar to traditional hardware based state machine.Common point is similar configuration detection, order decipher and device programming.But according to the present invention, the LCAS processor of configuration operated under the significantly reduced processing time according to the present invention, and required unconspicuous real-time processor requirement.In stable state or normal running, do not have the loading processing device, and only during configuration variation, require processor.Therefore, the present invention is by reducing the shortcoming solution that burden on the processor has proposed to have overcome prior art greatly at the stable state run duration.For example, when increasing or delete branch road, for the source and the receiver-side of operation, system only needs two interruptions (in increasing operation) or an interruption (in deletion action) are responded.Equally, in fact, the processing time of every branch road can be less than 1 millisecond in such operation, and can be independent of concrete enforcement (HO: high-order, LO: low order) move, for example:
The best-case worst condition
HO:8ms+4XProp time-delay 70ms+4XProp time-delay
LO:128ms+4XProp time-delay 352ms+4XProp time-delay
If the incident of breaking down, the present invention provides response to the branch road that breaks down in 100 milliseconds so.For LO, the LCAS fault speed of interruption can be that every 32ms receives up to 8 fault branch status messages, for HO, can be that every 2ms receives up to 8 fault branch status messages.In a word, carry out, can ignore the processor time of implementation basically for the LCAS agreement.
Adjust
The present invention also provides the Adjustment System of a kind of LCAS of execution, and wherein, data conditioner is configured to adjust the channel of input data.In one embodiment, adjuster comprises writes manager, and it is configured the input Data Receiving is advanced in the first memory.Writing manager then writes byte in the transparent module of the multichannel with second memory (MCT) from a plurality of channels.MCT is configured to store the input data in the second memory of writing the manager reception, and the data of each channel are kept separately.Adjustment System also comprises reads manager, and it is configured to advance in the 3rd memory with the input data read that the mode of adjusting will be stored in the second memory.In one embodiment, read manager and be configured to read channel data from one group of channel, when all data when VCG receives, this group channel has constituted virtual concatenation group (VCG).Be configured to carry out in the system of LCAS type of process a kind of, different independent virtual concatenation (VC) channel group arrive at the receiving terminal of transmission at different time.According to the present invention, read the space among the manager permission channel data filling MCT, arrive up to all group circuit-switched data.At this moment, they have been ready to be read out, and then send to subsequent process, for example separate preface.Also be fine separating the part execution of preface as adjustment process.In a preferred embodiment, the variation of adjusting with the sequence of independent channel data separates execution.
Preface is conciliate in ordering
The present invention also provides a kind of system and method that is used for novelty that the channel data from VCG is sorted.This system comprises order module, and it is configured to predetermined transmission gap order according to the path channels of VCG to the rearrangement of data byte and handle dynamic VCG branch road state variation.System also comprises at least two buffers, and it is arranged such that module can carry out double buffering and handle, and carrying out VCG branch road state variation, thereby supports LCAS.Read manager and be configured to read the branch road state variation, be configured to the branch road state variation is write another buffer and write manager from a buffer, wherein, the write functionality of reading manager and writing manager between two buffers alternately.In one embodiment, the byte capacity of each buffer is equal to or greater than the quantity of VCG branch road.
Inventing the system that forms that disposes (can independently or can be synthetic the use) according to different embodiment can be benefited greatly in a lot of modes.System can be provided for the agency of fixed structure cheaply of follow-on highly integrated speech/data, the customer terminal equipment that SOMET/SDH enables (CPE) system, be used for the integrated advanced Ethernet service of follow-on height and transmit solution, the MSPP ply-yarn drill that SONET/SDH enables, support Ethernet-over-SONET (EOS), Packet-Over-SONET, POS, network element with the TDM business, be used for intelligence (weight) set of data service is advanced the service card/Line cards of SONET/SDH circuit, data and/or circuit classification (grooming) system, support the Ethernet E-circuit of enhancing, E-LIN/VPLS, PWE data service and traditional professional and other application of TDM.
The present invention allows processor can make system platform transmit such business, simultaneously, reduces and the relevant transmission cost of professional transmission.In addition, Ethernet interface is used for general client access by inciting somebody to action cheaply, and the hardware and software solution of configuration can activating service speed and other SLA performance according to the present invention.Requirement when these can begin according to the client is automatically revised, and has also saved with high costs making house calls (truck roll).
Utilize the highly integrated solution of the present invention, because cost/service provided by the invention/value, systems provider can be enjoyed extra carrying capacity.The service supplier can utilize advanced service mode to increase their monthly benefits probability (along with the CAPEX expenditure approximately identical with every month extra charge of running), simultaneously, reduces their OPEX by the service integration technology.The user of terminal can utilize more service to select.The invention provides interface selection flexibly; comprise megabit Ethernet, 10/100 Ethernet, shielded SONET/SDH (light or MSOO optical fiber), PDH expansion bus, up to the STS-48 bandwidth, it has complete SONET/SDH and processing data packets.It utilizes GFP, virtual concatenation and LCAS, makes the transmission optimization of the Ethernet service on existing SONET/SDH framework.The present invention also provides a kind of carrier wave classification schemes that is used for sending by the Ethernet carrier network Ethernet service.
The system of configuration allows the professional transmission of high bandwidth Ethernet virtual dedicated line (E-Line), private virtual lan (E-LAN and VPLS) and pseudo-line (pseudowire) according to the present invention, allows service distribution widely.This system also activates virtual switch, and wherein, a lot of virtual switches are served the multiple income that produces E-LAN, and their each bandwidth, port and static father all isolated on the function and in the management.
In one embodiment of the invention, system comprises the LCAS state machine, and it is configured to store the state date relevant with the state of the LCAS of system hardware with management.Virtual concatenation (VCT) module is configured the virtual and standard cascade process in the executive system, more specifically, and according to the ITU standard of calling such process.The VCT module comprises the packet engine interface, and it is configured to send, receives or wraps exchanges data by SONET/SDH logic port and packet engine.The VCT module also comprises cross-connect-interface (cross connect interface), and it is configured to send, receives and utilize internal sonet/SDH interconnection exchange wherein to have the SONET/SDH business of mapping (enum) data.The VCT of system can be configured to utilize internal sonet/SDH interconnection to exchange the SONET/SDH business that (transmission) wherein has mapping (enum) data by inner STM-16 interface.
The HW system
With reference to Fig. 2 A, show the sketch of the hardware system of the receive channel of configuration according to the present invention.
With reference to Fig. 2 A, show the configuration of the receive channel of LCAS structure.Be in operation, data 202 are received by the adjuster in the system 200 204, and adjuster is adjusted the data branch road.In discrete processing, sorting unit 206 is according to the sequence rearrangement of MFI information to the VCG branch road.This all handles 208 by LCAS control data bag and controls, and it receives the data identical with sorting unit and the preface processing is separated in control.Then, output is sent to buffer 210, sends to multiplexer 212 then.What be received multiplexer into equally is the output of handling from non--VCAT data packets for transmission path overhead (POH) of module 214.
According to the present invention, divide hardware and software in the LCAS structure in a kind of mode of acquisition optimum efficiency of novelty.In the ITU standard, LCAS stipulates in software usually.Yet, in practice, find that the independent use of software in the application program is too slow.The better combination of finding software and hardware provides better result.Usually, with control path relevant data by software control.Hardware only uses in needs, for example, and in the data path transmission.
According to the present invention, all functions of overhead data (overhead data) are produced by software basically.Determine to hardware synchronization to change and take place.Process must be arranged all non-steps in limited time in software, wherein, hardware provides the synchronous of control path and data path.Therefore, hook (hook) and hardware is inserted data for software and is disposed with obtaining data.
When considering the control path individually, the control in control path is exclusively used in software field.In order to insert the control data bag, the hardware hook allows software to insert the control data bag.In order to extract, the hardware hook allows outcast controlling packet in the software reading data flow.In fact, when software definition changes must take place, and hardware judges to change when can take place and change.Therefore, hardware provides synchronism.
Consider control path and data path, at the receiver side of configuration, software arrangements hardware makes that the expense that receives in data path size, branch road quantity and the LCAS control data bag is consistent.At transmitter side, consideration is still controlled and according to the path, software indication hardware changes the transmission expense in the first data path size and the LCAS control data bag.These two kinds of functions are carried out by hardware synchronization ground, and therefore, software and hardware separates.
Consider that internal resource is synchronous, different virtual concatenation group are of different sizes.Therefore, some buffers are categorized as different packet sizes, and software control hardware is to be provided with buffer sizes.Similarly, resource allocation can realize by using this hardware-software to distinguish, wherein, and the software dictates resource allocation, and therefore hardware make a response.In buffer switched synchronously, software indication hardware changed the buffer that is used by specific VC group.Hardware is carried out in the appropriate time of strictness and is changed.
It should be appreciated by those skilled in the art that software can be in the outside or inner of the outside of memory or inside or CPU.It can be realized on identical Line cards or different Line cards.Equally, software can be positioned on the chip (die) separation or similar.Therefore, the present invention is not limited to any customized configuration, in described configuration, at the outside or inner software that uses of CPU or certain chip or chipset.
With reference to Fig. 3 A-G, show the simple and easy flow chart that the hardware and software that uses in one embodiment of the present of invention is cut apart.Fig. 3 A to 3G structure that illustrates and system flow chart are in order to help to describe the operation according to system of the present invention.According to the present invention, the LCAS business is broken down into a series of automatic operations, utilizes the hardware of configuration to carry out each automatic operation, and wherein, software is responsible for sending the suitably operation automatically of each business.
With reference to Fig. 3 A, show the source/synchronous LCAS system of configuration according to the present invention.System comprises the hardware controls module 304 in first driver 302, the source in source, synchronous hardware controls module 306 and the software driver 308 of sync numbers.The step format of operating procedure order illustrates, and will be described in this article.
With reference to Fig. 3 B, in operation, when increasing the new branch road 310 of NMS, process advances to system's step 312 of free time.When increasing new branch road, this is a kind of running status.In step 314, increase control setting, wherein, increase new branch road, and sequence number adds 1 successively, thereby equaling N, sequence number adds 1.In step 316, send LCAS control.In step 388, the set timer.In step 320, begin to increase sequence, and send control by line sequence path 326 and 328 respectively.In step 328, carry out checking sequence and check control operation.In step 330, be that standard and sequence number are set to N with control setting.In step 332, be sequence end (EOS) with control setting, and sequence number equal N and add 1.In step 334, begin to send the operation of LCAS control, in step 336, send load.In step 338,, and send to hardware device 304 with load criteriaization.In hardware system, control word generator (generator)/extractor (exactor) receives the load information that is ready for sending load.In step 340, the load serial device is established the order of load, packet 342.Produce and then control word is sent to packet 342 from the control word generator in the increase sequence in source/extractor by transmit path 344.In the opposite direction, path 346, control word is extracted by control word generator/extractor 324.Packet then sends and receives as packet 348 at receiver 306 places by path 343.These packets are received by receiver control word generator/extractor 350 by path 352.If packet is sent out back source hardware by path 343, control word generator/extractor can produce control word and by path 354 it is attached to packet.Control word generator/extractor then will be sent to software driver 308 from the packet that source hardware receives.At first, will send to the OK 355 that drives the path 356 in 308, to judge at the additional whether OK of 355 line states from the control word of control word generator/extractor 350.In step 366, carry out checking sequence and check control operation.Sequence then is advanced to step 364, has wherein begun RS-ACK upset (flip).In case these EOs, program are advanced into the step 362 that expression receives load.If increase branch road 359, idle step 372 beginnings and operation are reversed to driver 302.After idle step 372, checking sequence and inspection control operation begin in step 370, and begin to send LCAS control in step 368 subsequently, and operation is reversed.
With reference to Fig. 3 C, show the more detailed description that LCAS increases traffic sequence.In operation, handle driver 302 and 308 and move, replaced traditional hardware based state machine basically with expense.According to the present invention, for source and receiver, structure inspection can be public.In addition, order compiling and device programming also can be public.The LCAS state machine shows the total processing time less than 20%, and does not have the significantly requirement in real time of extra introducing process.In steady state operation, during normal running, do not handle or load, in addition, only during structural change, require processor.When increasing or delete branch road, there are significantly reduced operation in source and receiver.When increasing branch road, only need two interruptions to respond.When the deletion branch road, only require an interruption.When in the end analyzing, each branch road requires the disposed of in its entirety time less than 1 millisecond.This is the whole LCAS agreement deadline by the minimum of LCAS standard code.Therefore, the processing of time of implementation is carried out relevant with the LCAS agreement significantly.Still, show the flow chart that LCAS increases the traffic sequence example with reference to Fig. 3 C.In step 380, the source begins business by transmission control data bag (increase) is set to be increased on the new branch road.In step 382, receiver detects the variation in the control, and transmitting branch state variation (MST), in step 384, under situation about existing, by be provided with EOS on control=new branch road and control=before at last the NORM on the branch road increase branch road.In step 386, receiver detects the variation in the control and triggers RS-ACK or the affirmation of RS sequence.
With reference to Fig. 3 D and Fig. 3 A, show in further detail and increase the relevant path of new branch road process.In operation, in step 312, path 1 is initially located in idle, and advance to control word generator/extractor 324 by path 388, wherein, control word produces for packet 342, then be sent at receiver 306 packet 348 in the transmitter-receiver 306.The control word extractor then extracts control word, increases new branch road, still proceeds to step 342 by path 388 then.
With reference to Fig. 3 E, step 2 shows the operation that receiver detects the order MST that variation in the control and transmission equal OK.This is undertaken by path 390.The increase branch road 372 of driver 308 sends a command to control word generator/extractor by path 390 by path 390, and it is sent to control word the packet 348 of generation.These packets transmit to provide packet 342 by path 390.Then, control word extractor 324 extracts the MST order that equals OK, and sending it to then increases operational module 320 to finish the increase sequence.
In step 3F, proceed to step 328 from increasing block 320, handling, and by path 392 continuation, wherein, the source is detected MST and is changed, and under situation about existing, by the NORM on the branch road at last of EOS on control=new branch road and control=before is set.Still continue downlink path 392, handle advancing to control word generator/extractor 324 and load sorting unit 340 simultaneously,, thereby continue by path 392 to receiver hardware 306 with generation packet 342.Then, control word generator/extractor extracts control word, control=EOS, and process proceeds to step 358, and wherein, new assembly is in the OK state.
With reference to Fig. 3 G, final step, wherein receiver detects the variation in the control, and trigger RS-ACK or confirm order, handle like this and come downwards to step 394, beginning detects sequence therein and detects control, proceeds to path 394 downwards, thereby control word generator/extractor extracts control word, confirms order and sends it to packet 348 by path 394.In source hardware 304, these packets receive as packet 342, then, handle the control word generator/extractor that proceeds to source hardware and confirm order to extract, and then, handle the NORM process of returning.
1.1 operation automatically
1.2 oppositely control information
According to the present invention, the initial utilization in software in response to the hardware of software command of operation carried out automatically, optimized system the biglyyest.Consider reverse control information, and with reference to Fig. 3 A, these operations of receiver 303 operational administratives, receiver is positioned at the receiver side of receiver or LCAS operation.At the receiver of LCAS link, Orion can insert reverse control information, and for example, (RS-ACK) confirmed in a line state (MST) and rearrangement.Such information is by software arrangements.In addition, when software change information, change on all branch roads of virtual concatenation group (VCG) and take place simultaneously.This variation is also synchronous with the beginning of new LCAS control data bag.
At the place, source that LCAS connects, reverse control information is extracted in the source from the LCAS controlling packet that enters, for example, and MST and RS-ACK.CRC check is also carried out to confirm the validity of these data in the source.If such information changes, source processor is with interrupt software, and permission software reads the new value that receives.
1.3 forward control information
Consider the forward control information, at the place, source that LCAS connects, source processor inserts the forward control information, for example, and sequence number (SQ) and control word (CTRL).Such information is by software arrangements.When the such information of software change, new control data must be write next LCAS controlling packet.In addition, the data path change must be synchronous with the control path changing.New data path configuration by new SQ and CTRL value defined must strictly take place when the controlling packet of following the controlling packet that writes new SQ and CTRL value begins.
At the receiver place that LCAS connects, the receiver processor extracts the forward control information from the LCAS controlling packet that enters, for example, and SQ and CTRL.The receiver processor is also carried out CRC check to verify such data.If new SQ and CTRL value arrive, the receiver processor will interrupt software, and presents the value of new reception.If channel has been " mandate " pattern by software arrangements, the receiver processor will use new SQ and the CTRL information from this channel so, with the extraction of control real data.It is synchronous that datapath architecture changes, and makes it strictly take place when the controlling packet of following the controlling packet with new SQ and CTRL value begins.
With reference to Fig. 3 B-G, show an example describing the software and hardware lock out operation.
HW/SW separates explanation
2 summaries
The application has described based on the desired hardware and software of the various LCAS schemes of register mode and has interacted, and provides register mode in the document of LCAS/VCAT register.The asymmetric character of reaction LCAS, the operation that software need be carried out is separately discussed, because receiver separates with source.
Cover following content at presents:
Receiver-side
ο produces VCG
ο deletes VCG
ο provides new branch road to VCG
ο removes from VCG and supplies with new branch road
ο increases the VCG bandwidth
ο reduces the VCG bandwidth
ο reduces the VCG bandwidth because of fault
ο changes reverse control information and extracts configuration
Source
ο produces VCG
ο deletes VCG
ο provides new branch road to VCG
ο removes from VCG and supplies with new branch road
ο increases the VCG bandwidth
ο reduces the VCG bandwidth
ο reduces the VCG bandwidth because of fault
ο changes reverse control information and inserts configuration
The application does not cover the labor of wrong scheme, and supposition does not have mistake during the configuration relevant with business.The application is intended to help to understand how to utilize the LCAS configuration and carry out the LCAS protocol function by the state interface that Orion provides in software.
3 receiver-side schemes
3.1 produce VCG
When wanting to produce new receiver VCG, NMS specifies following operation for the receiver node side:
Receive LPID to be used for this receiver VCG
The channel type of VCG
If exist, discern described receive channel, it will be used as the branch road of this receiver VCG and provide at first
For each initial path channels, if exist, whether the reverse control information of LCAS should be from wherein extracting, and if it should be applied to the transmission LPID of local source VCG.Different path channels can carry the reverse control information that is used for different local source VCG.Reverse control signal can also not extract in some or all initial propping up on the path channels
Formulated following hypothesis:
Receiving port LPID is not in use (that is, set be used for the RX_SK_SW_CFG_EN of this reception LPID)
If exist, it is identical with receiver VCG type initially to prop up path channels
If exist, initially prop up path channels and be not in user mode (that is, their RX_SK_SW_CFG_EN position is set), and they come from the remote source node
Software is carried out following configuration step to produce receiver VCG:
1. set RX_SK_VCAT_EN and RX_SK_LCAS_EN are to be used to be dispensed to the reception LPID of receiver VCG
2. the TX_SK_LCAS_INS_MST field set with receiver VCG is that FALL is to be used for all possible sequential value (that is, this field being changed to complete 1)
3. by removing the SK_SW_CFG_EN position, make receiver VCG break away from reset mode.
If the designated receiver VCG that is provided at first of any receive channel, remaining configuration step with when these receive channels being provided the step of carrying out when having receiver VCG now identical.
3.2 deletion VCG
When hope deletion receiver VCG, NMS is assigned to receiver node with following operation:
Receive LPID and be dispensed to this receiver VCG
Inventor's supposition no longer provided all branch roads before deletion receiver VCG.Under these circumstances, software need be carried out following operation:
1. will receive LPID and place Reset Status by its SK_SW_CFG_EN position is set.
3.3 provide into VCG with a new path channels
When hope provided a new path channels into existing receiver VCG, NMS was assigned to receiver node with following configuration parameter:
Be dispensed to the reception LPID of this receiver VCG
The sign of receive channel, this receive channel should be as the new branch roads of this receiver VCG and are provided
For each initial path channels, whether the reverse control information of LCAS should be from wherein extracting, and if it should be applied to the transmission LPID of local source VCG.Different path channels can carry the reverse control information that is used for different local source VCG.Reverse control signal can also not extract in some or all initial propping up on the path channels.
Formulated following hypothesis:
Receiver VCG is activated, and, has been provided with the RX_SK_VCAT_EN and the RX_SK_LCAS_EN position that are used to receive LPID that is, and the RX_SK_SW_EN position that receives LPID is not set
A new path channels is identical with the type of receiver VCG
New path channels is not in user mode (that is, set their RX_SK_SW_CFG_EN position), and they come from the remote source node.
Software is carried out following operation so that a new path channels to be provided:
1. check and utilize these channels can compensate the difference time-delay as branch road.In VCAT scheme document, describe its details in detail.
2. each new path channels of configuration as following:
Its RX_CH_LPID field is set to be dispensed to the reception LPID of receiver VCG
Remove its RX_CH_VCAT_ACCEPT position
If channel will be used to extract the reverse control information of LCAS, its RX_CH_LCAS_RSV_EXT_SO_LPID field value that is set to provide so, and its RX_CH_LCAS_REV_EXT_EN position is set
3. by removing their RX_CH_SW_CFG_EN position, a new path channels of resetting is taken out.Because have the load that increased without any one before synchronous exchange, the order that is used for this is unessential.
4. wait for always, comprising on the receiver VCG that newly props up path channels up to the difference compensation of delay and carrying out.Can determine by the RX_CH_VCAT_TD_STATE position of observing all (being not only new) path channels like this.When all path channels during, carry out the difference compensation of delay with this bit set.Software can poll these or utilize their relevant interruptions for such purpose.
5. after different compensation of delay, wait for that a multi-frame (is low order or high-order decision duration according to receiver VCG) or longer time handles a LCAS controlling packet at least to guarantee all channels.
6. read RX_CH_LCAS_CTRL, RX_CH_VCAT_SQ and the RX_CH_LCAS_CRC_ERR field of all new path channels.
Because before receiver-side, NMS finishes the supply of a new path channels at source, in case obtain the difference compensation of delay at receiver-side, receiver-side should be found the IDLE control word on all new path channels.Sequence number that should these channels is set to than the high value of sequence by the employed current maximum of receiver node VCG.
But, because the behavior of proper configuration or NMS or source is not guaranteed, whether just is used as control word and receives, and whether the sequence number that receives is higher than the current maximum of receiver VCG so software should be checked IDLE.If find any mistake, whole supply business will be cancelled by all path channels are changed to reset, and NMS meeting defendant is with fault.
Should read the RX_CH_LCAS_CRC_ERR field reads effectively to determine control word and sequence-number field.Inventor supposition does not have crc error, and control word and sequence number are desired.
7. by one is write wherein, remove all RX_CH_VCAT_SQ_CHG positions of a path channels newly
This step is necessary, because the reset values of RX_CH_LCAS_CTRL_SQ field is zero.When Orion handled first controlling packet of newly propping up on the path channels, the sequence number in the controlling packet should be different from zero, thus set RX_CH_VCAT_SQ_CHG.
At this moment, supply is professional successfully to be finished from the receiver VCG of view point, and can will successfully inform NMS.
Supply with a path channels 3.4 from VCG, remove
When wanting to remove supply path channels from existing receiver VCG, NMS is assigned to receiver node with following configuration parameter:
Be dispensed to the reception LPID of this receiver VCG
Should remove the sign of the receive channel of supply
Formulate following hypothesis:
Prop up the branch road that path channels has been provided with receiver VCG, but their current use (that is, IDLE are as control word in reception, and its RX_CH_VCAT_ACCEPT position does not have set)
Software is carried out following operation and is provided a new path channels with removal:
1. by its RX_CH_SW_CFG_EN position is set, a new path channels is changed to reset mode.
At this moment, from the receiver VCG point of view completed successfully remove supply with professional, and NMS can defendant with success.
3.5 increase the bandwidth of VCG
Suppose that remote source can increase a plurality of path channels synchronously.Therefore, receiver-side will wait for, up to finding the ADD control word on all path channels, be before in them any one sends MST=OK, will be on a path channels increase ADD control word.In this mode, only after finding to increase NORM/EOS on all path channels, receiver-side just can trigger RS_ACK.
If remote source can only at a time increase path channels, the increase of a plurality of branch roads in this source should be decomposed into a lot of and the distinct business of each receiver node so.Because this only is the special circumstances that a plurality of path channels increase, so this can not produce any difference for the receiver based on Orion.
When hope increased new branch road to receiver VCG, NMS was assigned to receiver node with following configuration parameter:
Be dispensed to the reception LPID of local reception device VCG
The sign of a path channels that increases
Formulate following hypothesis:
Path channels has been provided with the branch road of receiver VCG, but they are current and be in the user mode (that is, receive IDLE as control word, its RX_CH_VCAT_ACCEPT position does not have set) of carry load
Software is carried out following operation to increase a path channels:
1. wait for always, just receiving the ADD control word, perhaps protocol error or overtime generation up to each path channels that will increase.
Software because supposing the remote source node, the inventor increases all path channels simultaneously, so before MST=OK being sent to wherein any one, can be waited for the ADD that receives on all path channels.
Software can determine when all channels receive the ADD control word by observing the RX_CH_LCAS_CTRL field of a path channels that will increase.Software can these field of poll or is utilized their relevant interruptions for such purpose.
If generation is overtime before finding the ADD control word on the path channels of all increases, software can be cancelled business, and gives NMS with Trouble Report.
When whether changing on the path channels that the control word that software judge to receive is increasing (by poll or utilize RX_CH_LCAS_CTRL_CHG to interrupt), should check whether new value is ADD.Equally, software should read the sequence number of its reception, thereby can verify the viability that is dispensed to the sequence number of described path channels by source node.They should form continuous sequence, and described sequence is from a sequence number higher than the sequence number of the maximum of current use on local reception device VCG.Any protocol error can cause professional cancellation and to the Trouble Report of NMS.
2. for the path channels of each increase, its RX_CH_VCAT_ACCEPT position of set.
3. the position, mapping (shadow) MST position that will be used for sequence number in the TX_SK_LCAS_INS_MST of receiver VCG field is OK, the corresponding path channels that increases of described sequence number.
The mapping MST position of supposing other branch roads keeps identical with activation.
4. trigger the TX_SK_LCAS_REV_SEL position of receiver VCG.
5. wait for, up to set TX_SK_LCAS_REV_CHG_DONE position always.
Software can utilize TX_SK_LCAS_REV_CHG_DONE to interrupt or poll TX_SK_LCAS_REV_CHG_DONE position for this reason.
6. wait for always, receive NORM/EOS control word, perhaps protocol error or overtime generation up to each path channels that increases.
Because the inventor supposes that the remote source node increases all new path channels simultaneously, the inventor wishes that the source begins to send NORM/EOS simultaneously on new branch road receive channel.Software will wait for that before triggering RS-ACK, it finds NORM/EOS control on all new path channels.
When changing on the path channels that the control word that software determine to receive is increasing (by poll or utilize RX_CH_LCAS_CTRL_CHG to interrupt), whether it should have highest serial number according to channel, checks whether new value is NORM or EOS.
If receiver is not found NORM/EOS at time-out period from all path channels, need to cancel this business so.In order to carry out like this, software should be removed the RX_CH_VCAT_ACCEPT position of the branch road of all increases.
Suppose that except having that of highest serial number, new receiving branch channel will receive NORM now.With highest serial number that just receiving EOS.Their sequence number will be with maintenance ground be the same before.This also should be examined.
Software has the RX_CH_LCAS_CTRL field of branch road receive channel of highest serial number before also should checking, and whether set is NORM now.
Last branch road before disregarding should suppose that also the sequence number and the control word that are used for existing branch road receive channel (if having) do not change.
If between service period, detect protocol error, may need the VCG that resets so, and inform that NMS breaks down.
7. (copy) duplicated in the mapping that triggers the TX_SK_LCAS_REV_SEL position that is used for local reception device VCG.
8. trigger the TX_SK_LCAS_REV_SEL position of receiver VCG.
9. wait for, up to the TX_SK_LCAS_REV_SEL_CHG_DONE position is set always.
At this moment, business has successfully been finished from the local reception device VCG of view point, and can notify NMS.
3.6 reduce the VCG bandwidth
The inventor supposes that receiver-side does not obtain just automatically responding from the request of NMS the removing request (that is, the control word of reception becomes IDLE from NORM/EOS) of source.Source sends the request of removing when it receives reduction bandwidth request from NMS.When source obtains correct affirmation from receiver (, receive MST=FAIL removing on the branch road, and found the RS_ACK triggering), inform NMS, it then can require the receiver node side to remove and supply with branch road, if necessary.
Although be not described clearly in this application, alternatively, even channel (that is, source is not initiated the request of removing) under the NORM/EOS state, NMS also can require receiver-side to remove a path channels.In this case, receiver-side can show as it and receive IDLE on this channel from source, but it should not send to source with the RS_ACK signal.Then, if wish, had better remove the supply channel.
Suppose that remote source can attempt removing simultaneously a plurality of channels, that is, the control word of a plurality of channels is changed to IDLE in identical multi-frame.Receiver-side software can be handled this situation.
When receiving the RX_CH_LCAS_CTRL_CHG interruption on a path channels of software at receiver VCG, it should carry out following operation:
1. wait for about 2K core clock (core clock) and read the RX_CH_LCAS_CTRL of all branch roads of VCG and RX_CH_VCAT_SQ number.
Allow software to judge whether to receive the IDLE control word like this more than one path channels.Also allow to check protocol error.
According to the sequence number of the channel that just is being eliminated, can change the sequence number and/or the control word of remaining branch road receive channel.For example, if the channel branch road that just is being eliminated has the highest sequence number, the control word that has the branch road receive channel of next highest serial number so should become EOS.
2. for each path channels that receives the IDLE control word, the bit in the TX_SK_LCAS_INS_MST field of receiver VCG that will be relevant with (that is, before it begins the to receive IDLE) sequence number before the branch road is changed to FAIL.
3. trigger the TX_SK_LCAS_REV_SEL position of receiver VCG.
4. wait for, up to the TX_SK_LCAS_REV_CHG_DONE position is set always.
5. the mapping that triggers the TX_SK_LCAS_INS_RS_ACK position that is used for local reception device VCG is duplicated.
6. trigger the TX_SK_LCAS_REV_SEL position of receiver VCG.
7. wait for, up to the TX_SK_LCAS_REV_SEL_CHG_DONE position is set always.
8. remove the RX_CH_VCAT_ACCEPT position of a path channels of removing.
At this moment, business has successfully been finished from the local reception device VCG of view point, and can notify NMS.
3.7 because fault reduces the VCG bandwidth
Receiver-side software need respond in use the detected fault on the path channels of propping up of (that is NORM/EOS state).According to channel known being protected whether, consider to handle the mistake (for example LOS, LOF, LOP, OOM) of an influence path channels, there are two kinds of situations.
If channel is not protected, software is carried out following operation:
1. remove the RX_CH_VCAT_ACCEPT position of faulty channel
With the SK_LCAS_INS_MST field of receiver VCG in the mapping MST position of corresponding fault branch channel be set to FAIL
3. trigger the TX_SK_LCAS_REV_SEL position of receiver VCG;
4. wait for, up to the TX_SK_LCAS_REV_CHG_DONE position is set always.
If channel is protected, the delimiting period (definedperiod) that software should the Wait-to-Restore channel.If this does not take place, software should be carried out above step for not protected channel.
When switching to the protection channel or recovering channel by faulty channel, software should be carried out following operation:
1. check with this channel and whether can compensate the difference time-delay as branch road
2. behind the difference compensation of delay, whether the control word that software should detect on the channel is DNU
3. set is used for the RX_CH_VCAT_ACCEPT of a path channels
4. the mapping MST position of propping up path channels of the correspondence in the TX_SK_LCAS_INS_MST field of receiver VCG is set to OK
5. trigger the SK_LCAS_REV_SEL position of receiver VCG
6. wait for, up to the TX_SK_LCAS_REV_SEL_CHG_DONE position is set always.
Extract configuration 3.8 change oppositely control
When configuration was extracted in the reverse control of a path channels of wanting to change receiver VCG, NMS specified following operating parameter for the receiver node side:
Channel logo, it oppositely controls to extract to dispose needs to change
For each such channel, whether should be with the reverse control information of LCAS from wherein extracting, and if it should be applied to the transmission LPID of local source VCG
Formulate following hypothesis:
Channel has been provided with and has enabled the LCAS branch road that receiver meets VCG.
Software is carried out following operation and is extracted configuration with the reverse control that changes the private driveway channel:
1. each new path channels of such configuration as described below:
If channel will be used to extract the reverse control information of LCAS, its RX_CH_LCAS_RSV_EXT_SO_LPID field value of being set to provide and its RX_CH_LCAS_REV_EXT_EN position is set so.Otherwise, remove its RX_CH_LCAS_REV_EXT_EN position.
4 source schemes
Supposing, is that source node software rather than NMS management transmits Sequence Number to the distribution of the branch road transmitting channel that sends VCG.
4.1 produce VCG
When hope produced new source VCG, NMS was assigned to source node with following operation:
The transmission LPID that will be used for source VCG
The channel type of VCG
The sign of transmitting channel, if exist, it should just provide as the branch road of this source VCG in beginning
Initially prop up path channels for each,, whether the LCAS reverse control signal should be inserted each initially path channels if exist, and if it should be applied to the reception LPID of local reception device VCG.The different branch road channel bearing of possibility is used for the reverse control information of different local reception device VCG.Also oppositely control information is not inserted on some or all initial path channels.
Formulate following hypothesis:
Transmit port LPID is not in user mode (that is, do not have transmitting channel to give this LPID with its TX_CH_LPID field set, described transmitting channel does not reset)
If there is an initial path channels, just the type with source VCG is identical initially to prop up path channels
If there is an initial path channels, initially prop up path channels and just be not in user mode (that is, their TX_CH_SW_CFG_EN position is set), and they is transferred into the far-end receiver node.
Software is carried out following configuration step to produce source VCG:
1. for the transmission LPID that distributes to source VCG TX_SO_VCAT_EN and TX_SO_LCAS_EN position are set
To provide to source VCG when initial if any transmitting channel is designated, remaining configuration step so should be identical with the step of carrying out when these receive channels being provided to existing source VCG.
4.2 deletion VCG
Inventor's supposition had removed to remove all branch roads of having supplied with it before deletion source VCG.In fact source VCG deletes from the hardware of point of observation.
4.3 provide into VCG with a new path channels
When hope provided a new path channels to existing source VCG, NMS was assigned to source node with following configuration parameter:
Be dispensed to the transmission LPID of this source VCG
The sign of the transmitting channel that should provide as the new branch road of this source VCG
For each new path channels, whether the reverse control information of LCAS should be inserted into, and if it should be applied to the reception LPID of local reception device VCG.The different branch road channel bearing of possibility is used for the reverse control information of different local reception device VCG.Also oppositely control information is not inserted on some or all new path channels.
Formulate following hypothesis:
The TX_SO_VCAT_EN and the TX_SO_LCAS_EN position that send LPID have been set
A new path channels is identical with the type of source VCG
A new path channels is not in user mode (that is, their TX_CH_SW_CFG_EN position is set), and they are transferred into the far-end receiver node.
Software is carried out following operation so that a new path channels to be provided:
1. as described as follows, dispose each new path channels:
Its TX_CH_LPID field is provided with to the transmission LPID that is dispensed to source VCG
If channel will be used to insert the reverse control information of LCAS, its TX_CH_LCAS_REV_INS_SK_LPID field value that is set to provide and the TX_CH_LCAS_REV_INS_EN position that it is set so
2. by removing their TX_CH_SW_CFG_EN position, a new path channels is broken away from resetted.Because without any one its load will be increased in them before in signal Synchronization exchange (handshake), so such order is unessential.
Should be noted that because the reset values of TX_CH_LCAS_CTRL is IDLE, be not set to IDLE so do not need the mapping of the TX_CH_LCAS_CTRL field of a new path channels duplicated, and the TX_SO_LCAS_FWD_SEL position that does not need to trigger source VCG.
Supply with a path channels 4.4 from VCG, remove
Remove from existing source VCG when supplying with path channels when hope, NMS is assigned to source node with following configuration parameter:
Distribute to the transmission LPID of this source VCG
Should be disengaged the sign of the transmitting channel of supply
Formulate following hypothesis:
Prop up the branch road that path channels has been provided source VCG, but, they are current not to be used to send load or oppositely control information (that is, the activation of their TX_CH_LCAS_CTRL field is duplicated and is set to IDLE, and their TX_CH_LCAS_REV_INS_EN position does not obtain being provided with)
Software is carried out following operation and is supplied with a new path channels to remove:
1. by their TX_CH_SW_CFG_EN position is set, a new path channels is changed to reset mode.
At this moment, remove the supply business from the source VCG point of view and successfully finish, and can inform the NMS success.
4.5 increase the bandwidth of VCG
Suppose that the far-end receiver can increase a plurality of branch roads simultaneously.By like this, it has confirmed to increase order on all path channels that all just are being increased in case we plan, and the far-end receiver will trigger RS_ACK.When increasing a plurality of branch road, the control word that source software will the path channels that all just are being increased in identical multi-frame is set to ADD.
If the far-end receiver at a time only can increase path channels, the source software business that needs can be increased a plurality of branch roads is decomposed into a plurality of single branch roads so increases subservices.
Usually, know not necessarily whether the far-end receiver can at a time increase a plurality of branch roads.May, the source can send the ADD control word simultaneously on a plurality of branch roads, think that receiver will confirm them together, but the far-end receiver can not done so.So source software should be able to be handled a plurality of RS_ACK and trigger.For simplicity, such situation is not discussed in this application.
When hope was added into source VCG with new branch road, NMS was assigned to source node with following configuration parameter:
Be dispensed to the reception LPID of local reception device VCG
The sign of a path channels that will be added
Formulate following hypothesis:
Prop up the branch road that path channels has been provided active VCG, but their current carry load (that is, transmission is as the IDLE of control word) that is not used in
Software is carried out following operation to increase a path channels:
1. the TX_CH_LCAS_CTRL field of a path channels that all is added is set to ADD
2. the also high sequence number of current highest serial number that is used for source VCG since a ratio is given serial number assignment the branch road that will be increased
3. the TX_CH_VCAT_PL_SQ and the TX_CH_LCAS_OH_SQ of each that will be increased path channels are provided with to the sequence number that is dispensed to it
4. trigger the TX_SO_VCAT_FWD_DONE position of source VCG
5. wait for, up to the TX_SO_VCAT_FWD_CHG_DONE position that source VCG is set always
Software can utilize TX_SO_VCAT_FWD_CHG_DONE to interrupt, perhaps poll TX_SO_VCAT_FWD_CHG_DONE position for this reason.
6. wait for always, receive MST=OK state or overtime generation up to each branch road that is just increasing
Because inventor's supposition, before triggering RS_ACK, the far-end receiver will send the MST=OK of all new branch roads that just increasing, and software is waited for always, detects MST=OK up to it on all path channels.
Software can determine when that all channels are just receiving the MST=OK state by the RX_SO_LCAS_EXT_MST field of observing source VCG.Software can interrupt by such field or the relevant RS_SO_LCAS_EXT_MST_CHG of utilization of poll.The position of inquiring about in this field of given the path channels that is used for being increased is based on the sequence number of distributing to this channel.
If before on the MST=OK state will increase all path channels, detecting, takes place overtimely, software can be cancelled business so, and with Trouble Report to NMS.In order to cancel business, software is set to IDLE to the control word of all branch roads that increase, and triggers the TX_SO_VCAT_FWD_SEL position.
7. the TX_CH_LCAS_CTRL field of a path channels that will increase is set to NORM/EOS (EOS is used to have the branch road of highest serial number)
8. if there is the branch road that has activated, the TX_CH_LCAS_CTRL field that has the existing branch road of highest serial before is set to NORM
9. trigger the TX_SO_VCAT_FWD_SEL of source VCG
10. wait for, up to the TX_SO_VCAT_FWD_CHG_DONE position that source VCG is set always
11. wait for, always up to the RS_ACK value that exhausts the reception that is used for local VCG triggering or RS_ACK timer
At this moment, increase band width service and successfully finish, and can inform the NMS success from the source of view VCG point.
4.6 reduce the bandwidth of VCG
Suppose that the far-end receiver can be removed a plurality of branch roads simultaneously.By like this, it has confirmed clear command on all path channels that all just are being eliminated in case we plan, and the far-end receiver will trigger RS_ACK.When removing a plurality of branch road, the control word that source software will the path channels that all just are being eliminated in identical multi-frame is set to IDLE.
If the far-end receiver at a time only can be removed path channels, the source software business that needs can be removed a plurality of branch roads is decomposed into a plurality of single branch roads and removes subservices so.
Usually, know not necessarily whether the far-end receiver can at a time remove a plurality of branch roads.May, the source can send the IDLE control word simultaneously on a plurality of branch roads, think that receiver will confirm them together, but remote receiver can not done so.So a plurality of RS_ACK that source software should be able to be handled reception trigger.For simplicity, such situation is not discussed in this application.
When hope was added into source VCG with new branch road, NMS was assigned to source node with following configuration parameter:
Be dispensed to the reception LPID of local reception device VCG
The sign of a path channels that will be eliminated
Formulate following hypothesis:
Prop up the branch road that path channels has been provided active VCG, and carry load (that is, transmission is as the NORM/EOS of control word)
Software is carried out following operation to increase a path channels:
1. the TX_CH_LCAS_CTRL field of a path channels that all is eliminated is set to IDLE
2. be necessary sequence number is redistributed to some or all residue branch roads, make them keep zero-based continuous fragment.If like this, TX_CH_LCAS_OH_SQ and the TX_CH_VCAT_PL_SQ field with such branch road is provided with to new sequence number.For residue branch road, also can be necessary its TX_CH_LCAS_CTRL field value is changed into EOS from NORM with highest serial
3. trigger the TX_SO_VCAT_FWD_DONE position of source VCG
4. wait for, up to the TX_SO_VCAT_FWD_CHG_DONE position that source VCG is set always
5. wait for always, be in reception MST=FAIL state or take place overtime up to each branch road of just removing
Because inventor's supposition, before triggering RS_ACK, the far-end receiver will send MST=FAIL for all branch roads of just removing, and software is waited for always, detects MST=FAIL up to it on all path channels.
Software can determine when that all channels are in the MST=FAIL state that receives by the RX_SO_LCAS_EXT_MST field of observing source VCG.Software can this field of poll or the relevant RS_SO_LCAS_EXT_MST_CHG interruption of utilization.Be based in the position that this field of given the path channels that is used for being increased is inquired about and remove the sequence number that is dispensed to this channel before telling on.
6. wait for, up to the RS_ACK value that exhausts the reception that is used for local VCG triggering or RS_ACK timer always.
At this moment, reduce band width service and successfully finish, and can inform the NMS success from the source of view VCG point.
4.7 because fault reduces the VCG bandwidth
When (that is, being in the NORM/EOS state) not protected path channels broke down in using, receiver-side will send to source with the MST=FAIL state.When source detects this status signal, it will carry out following operation:
1. the TX_CH_LCAS_CTRL field of all fault branch channels is set to DNU
2., will have TX_CH_VCAT_PL_SQ field minimizing 1 than all branch roads of the higher sequence number of faulty channel if the channel that breaks down is not the last branch road of source VCG
If the channel that breaks down is the last branch road of source VCG, the TX_CH_LCAS_CTRL field with branch road of next highest serial is set to EOS.
3. trigger the TX_SO_VCAT_FWD_SEL position of source VCG
4. wait for always that when a path channels that breaks down recovered, receiver-side can send to source with the MST=OK state up to the TX_SO_VCAT_FWD_CHG_DONE position that source VCG is set.When source detects this state, it will carry out following operation:
1. if the channel of Hui Fuing is last branch road, the TX_CH_LCAS_CTRL field of a path channels that recovers is set to EOS, and the TX_CH_LCAS_CTRL field with branch road of next highest serial is set to NORM.
Otherwise the TX_CH_LCAS_CTRL field of a path channels that recovers is set to NORM.
2., will have TX_CH_VCAT_PL_SQ field increase by 1 than all branch roads of the higher sequence number of this channel if the channel of Hui Fuing is not last branch road.
3. trigger the TX_SO_VCAT_FWD_SEL position of source VCG.
4. wait for, up to the TX_SO_VCAT_FWD_CHG_DONE position that source VCG is set always.
Insert configuration 4.8 change oppositely control
When configuration was inserted in the reverse control of propping up path channels of hope change source VCG, NMS was assigned to source node with following configuration parameter:
Need to change oppositely control and extract the sign of the channel of configuration
For each such channel, whether the reverse control information of LCAS should be inserted wherein, and if it should be applied to the reception LPID of local source VCG
Formulate following hypothesis:
Channel has provided the branch road that LACS makes energy VCG
Software is carried out following operation and is extracted configuration with the reverse control that changes the particular branches channel:
2. each newly props up path channels configuration as described below:
If channel will be used to insert the reverse control information of LCAS, its TX_CH_LCAS_REV_INS_SK_LPID field value that is set to provide and the TX_CH_LCAS_REV_INS_EN position that it is set so.Otherwise, empty its TX_CH_LCAS_REV_INS_EN position.
Adjust
With reference to Fig. 4 A to 4E, show the sketch of the hardware system of the receive channel of configuration according to the present invention.These embodiment show the receive channel that embodies the LCAS function, and have embodied the embodiment and the function of various novelties of the present invention.These functions are below with reference to adjustment, the Xie Xu of channel with belong to other functions of the present invention and be described in detail.
With reference to Fig. 4 A, show the example of the adjuster of configuration according to the present invention.System 400 comprises high-order in the receive channel and low order (HO/LO), multi-frame indication (MFI) analyzer, is called ANA together.ANA is sent to data flow and writes manager 405, and has a plurality of (FIFO) memory storage circuit of going into earlier/go out earlier, FIFO-A (406), FIFO-B (408) ... FIFO-N (410).So for a person skilled in the art configuration is well-known.According to the present invention, write each branch road that manager receives the VCG among each FIFO, and data are write the transparent module 412 of multichannel.In one embodiment, write manager and be configured in the static RAM (SRAM), and the transparent module of multichannel is configured to dynamic random access memory (DRAM).Yet, as well-known to persons skilled in the art that and can use different configurations and dissimilar memory and memory elements.According to the present invention, read manager 414 and be configured to the content of the transparent module of multichannel is read in the memory storage apparatus.With to write manager similar, read manager dispose first-in first-out-A (416) ,-B (418) ...-N (420).According to the present invention,, read manager the content of the transparent module of multichannel is read in into its FIFO storage separately when the branch road of virtual concatenation group (VCG) is complete and when the transparent module 412 of multichannel is adjusted.In case it obtains adjusting, and reads manager adjusted VCG is sent to Xie Xuqi (de-sequencer).In one embodiment, reading manager is configured in the static random-access memory (SRAM).It should be appreciated by those skilled in the art that memory construction is flexibly, and under the situation that does not deviate from the spirit and scope of the present invention, can use the memory or the structure of other types that this limits in claims and its equivalent.
With reference to Fig. 4 B, flow chart shows an operation of receive channel according to an embodiment of the invention.In step 424, receive input VCG channel data, for example, ANA 402 places among Fig. 4 A.In step 426, detect LCAS bag sign (LPID) to determine whether transmission is the VCAT transmission.If not, so transmission is sent to POH, 422 among Fig. 4 A, and process is back to step 424.If it is VCAT transmission that LPID shows this transmission, handle and proceed to step 430, wherein storage is being write manager, and among Fig. 4 A 405, it can be SRAM.In step 432, write manager and write MTC, 412 among Fig. 4 A, it can be DRAM.In step 434, judge whether the branch road of VCG obtains adjusting.If they are not adjusted, handle so and be back to step 424 to receive further data.In step 434, they are adjusted once.Below will be explained in more detail embodiment.Then, in step 436, read the branch road that manager reads VCG.In step 438, data are sent to Xie Xuqi further handling, and in step 440, output signal output.
With reference to Fig. 4 C, calcspar symbolically shows the branch road of how adjusting in the group.In step 448, receiving inputted signal, wherein data are not adjusted or are not in suitable order.In step 450, carry out and adjust, wherein adjust respective sets, be two branch roads of a group in this embodiment.In step 452,, thereby the branch road of VCG and arrangement have in turn been adjusted to the sequence rearrangement.
With reference to Fig. 4 D, also show and adjust another example of handling in the receive channel with the form of sketch, when when the receive channel angle is considered, also think to separate adjustment (de-alignment).In first step 442, receive independent channel A, B, C and D from writing manager at the transparent module of multichannel place.According to one embodiment of present invention, these begin to read by reading manager, and wherein, first channel that will in time be received reads by reading manager, and are provided with MFI number at (GO) state that is written into.In reading manager, have three kinds of states.The GO state is from writing the state of manager to the complete receive channel of MCT, and when other channel was received fully and adjusts and therefore also is in the GO state, it was ready to be read.(DRAIN) state that empties is the state of channel, wherein, does not fully receive whole channel data in MCT, and needs the further information of reception to finish.Wait for or halted state is the state of received channel before initial channel, but when MFI is set, it has passed through first and has read channel, and be set to wait for up to all channels of adjustment.
As can be seen, channel A is in the GO state, because it is first channel that will receive.At this, be provided with MFI number.Because channel B was in time received afterwards, and also imperfect, so channel B is set to the state of emptying.On the contrary, channel C is received in advance, and wherein, it is for complete and be provided with in wait state to wait for that other channels catch up with to adjust.The situation of channel D is similar, and it is also in the wait state setting.The MFI that can reset waits for or halted state to eliminate.Yet the LCAS code requirement does not have interrupt operation, and replacement MFI can produce interruption.Therefore accordingly, in a preferred embodiment, in case the first channel branch road of reception group just is provided with MFI, and follow-up branch road in the group that arrives at is set.
In next step 444, the channel fact that their data have arrived at by all is readjusted, and it is set to GO.In step 446, all channel A-D are set to the GO state, represent that they have obtained adjusting, and are in the GO state, and prepare to read from read manager.After this, read manager and entirely read VCG.VCG then is sent to sorting unit and sorts.
According to the present invention, no matter the modularity of hardware is to realize on the singulated dies or on chipset, and the adjustment that the modularity of hardware all allows to receive data is independent of the sequence that receives data.In operation subsequently, the sequence of receive channel is resequenced.This is the improvement on prior art, and wherein these processing realize in an independent step.Therefore, data steadily arrive at and withdraw from receiving circuit, and do not fluctuate, and this has caused decoupling.In operation, at first adjust, in case it is adjusted, (time domain multiplex order) reads these data in the date of memory with the time-domain multiplexed order.Operate more stablely, tediously long, wherein each gap has obtained a time slot.All operations are pre-set.In configuration, there are not burst service stream, abnormal data burst or uncertain.Each channel has obtained the cycle time slot, so data stabilization ground transmits and flows through.
This is opposite with existing operation, in the existing operation, and when extracting in data arrives and with same sequence, the storage data.Rearrangement or carry out in data block (chunk) synchronously causes problematic burst service stream, and has used a plurality of memories.This structural change transmission mode, and arbitrariness is very complicated.According to the present invention, the solution in cycle is more stable, wherein at first carries out and adjusts, and has avoided any burst service stream or obliterated data basically.
With reference to Fig. 4 E, flow chart shows the system according to the MFI of setting of the present invention number.In step 458, channel data is received by a path channels.In step 460, read in the MFI self-channel.In step 462, judge whether channel is first channel that reads in group.If be provided with MFI number for this group so.Then, in step 484, judge whether to have received all circuit-switched data.If no, process is back to step 458 so, wherein, when they arrive at, writes a further path channels.In step 460, come the MFI of self-channel to read, and if it be not first channel, handle to be advanced into step 470 from step 462, wherein the MFI of the MFI of the channel that will receive subsequently and setting compares, MFI is provided with by first channel of establishment.In step 472, judge that whether MFI is greater than the MFI that is provided with.If greater than the MFI that is provided with, state is set to wait in step 474 so.If not, perhaps after state is provided with, in step 476, judge that whether MFI is less than the MFI that is provided with.If answer is a "Yes", in step 478, think known in its possibility of existing step, state is set to " DRAIN " in step 478, and process proceeds to the MFI of step 480 to judge whether it equals to be provided with.If the MFI that equals to be provided with, in step 482, the process state is set to GO, and process is back to step 484 to judge whether to receive all circuit-switched data.This process is received up to all channels around step 458 and subsequent step circulation.Return with reference to Fig. 4 D, how its MFI that shows described in Fig. 4 E is provided with state after channel is received.Still, illustrate and described processing procedure, illustrated when each channel is received among Fig. 4 E and how state is provided with reference to Fig. 4 D.When channel A at first in time arrived at, it was set to the GO state, set up first MFI.After other channels were received, for example channel B, C and D compared MFI so that their state to be set.In Fig. 4 D, step 444 shows because channel A is first channel that arrives at, so it is set to the GO state.Can read and further before the processed group, all channels must proceed to the GO state.Because channel B is not fully received, so channel B is set to empty, and channel C and D keep waiting for or halted state, finished its transmission up to channel B.In step 446, in case all channel datas arrive at, must they be set to GO from all channel A, B, C and D, and be ready to read by reading manager.
Return with reference to Fig. 4 A, when all channel datas are set to GO, read manager and read channel data, receive the data of each channel among FIFO 416,418 and other FIFO.In fact, read manager and can repeatedly read position among the MCT 412, be in the GO state up to all.In case be in the GO state, read manager and intactly read all data.In operation, when channel data arrives at, write manager receive channel data from ANA 402, and it is stored in the MCT memory storage apparatus.In one embodiment, writing manager is SRAM, and MCT is DRAM, and reading manager also can be SRAM.Therefore, writing that manager compares with MCT with the size of reading manager can be littler, and MCT can be the DRAM that are used for a large amount of storages.Write manager and lot of data can be write MCT, and do not require a large amount of memories, receive the data of a plurality of channels simultaneously.MCT can store data, obtains adjusting up to it.In case obtain adjusting, reading manager can be with time-domain multiplexed mode reading of data in MCT.Be sent to from the output of reading manager and separate the preface module, thereby it is resequenced to channel data.
5 summaries
In one embodiment, in a plurality of modules, the distributing function of receiving circuit or VCT_RX functional block.In one embodiment, module comprises that configuration (CFG) module, schedule/fault/register (CFR) module, MFI analyzer (ANA) module, adjuster are write manager (ALIG_WR), adjuster is read manager (ALIG_RD), LCAS/VC controller (LVC) and load and separated preface device (DSQ).In a preferred embodiment, compare with the VCAT business, transmit in non-VCAT data packet traffic different path in the VCT_RS functional block.
Configuration (CFG)
5.1 summary
The CFG module is kept all global configuration and state parameter and all interrupt status parameters.Its CPU request that will be used for every other configuration and status register is assigned to the module of carrying out it.The CFG module can produce a plurality of requests from the single cpu request, to carry out the register that makes up a plurality of module parameters therein.
The CFG module realizes the indirect access scheme by every other module use in the RX_VCT functional block.Should be noted that configurations all in these modules and state parameter use indirect access, and the parameter in the CFG functional block is by directly access.That uses in indirect access scheme and the packet functional block is the sort of identical, that is, it supports to increase automatically model.
The CFG module is responsible for generating interruption summation state and the interruption that generates top CPU module among the Orion.
5.2 interface
The CFG module is connected to the every other module in the VCT_RX functional block of utilizing independent point-to-point bus, and described bus is transmitted configuration or the state read of CPU.Notice that the CFG module itself is safeguarded some configurations and state parameter, comprises all interrupt status parameters.
Except the ALIG_WR module, the point-to-point interrupt bus that all module utilizations are independent is to represent interrupt event the module to CFG.Unique interruption that ALIG_WR can produce is used for the parity error (parity error) on the channel status memory.It indicates the module to ALIG_RD by the read pointer that destroys influenced channel with the parity error incident.The ALIG_RD module will combine with himself channel level parity error incident from the parity error incident of ALIG_WR module.Because ALIG_RD is driven by identical schedule with the LVC module, so the CFG functional block can be arranged interruption, (not interrupting from DSQ) takes place in described interruption in from its identical clock.
5.3 configuration and state parameter
In one embodiment, the CFG module is safeguarded following parameters:
All global configuration parameters
All channel level interrupt enabling configuration parameter
All receiver port levels interrupt enabling configuration parameter
All source port levels interrupt enabling configuration parameter
All global state parameters
All global interrupt state parameters
All channel level interrupt status parameters
All receiver port level interrupt status parameters
All source port level interrupt status parameters
Utilize for example trigger (flop), reverse circuit (flip flop) or other memory devices or configuration, these parameters of execution as described below:
Utilize trigger to carry out global parameter
Utilize trigger execution receiver port level or source port level to interrupt enabling and the interrupt status parameter
Utilizing memory to carry out channel level interrupts enabling and the interrupt status parameter
According to the collision algorithm (collision algorithm) of representing hardware and software to handle, the conflict between the software and hardware of the parameter that processing is safeguarded in the CFG functional block.In one embodiment, processing is as follows:
Conflict with read request if be used for the write request from software of configuration parameter, will use by hardware from the value of software from hardware
Conflict with read request if be used for the write request from software of global state or interrupt status parameter, will be transferred to software from the value of hardware from hardware.
5.3.1 global configuration
According to the size of group, configuration VCAT DRAM.These parameters are static.When the VCAT_RX functional block is not in reset mode (perhaps when any VCAT enable channel when not being in reset mode), they should not be changed.
Counter is configured to enter/and withdraw from OOM and enter LOM.Order occurs with forms such as RX_VCAT_HO_OOM1_IN, RX_VCAT_HO_OOM1_OUT, RX_VCAT_LO_OOM1_IN and RX_VCAT_LO_OOM1_OUT.These parameters also are static, and when the VCAT_RX functional block is not in reset mode (perhaps when any VCAT enable channel when not being in reset mode), they should not be changed.
Other counters are used for being provided with and removing the lasting CRC alarm of LCAS (DCRC).
Their form is RX_LCAS_DCRC_N1, RX_LCAS_DCRC_K1 etc.Similar, their parameter is static, and when the VCAT_RX functional block is not in reset mode (perhaps when any VCAT enable channel when not being in reset mode), they should not be changed.
MFI catches the MFI value that (capture) is configured to catch each channel.The order form be RX_VCAT_MFI_CAP_CHAN1 ... RX_VCAT_MFI_CAP_CHAN (n) and RX_VCAT_MFI_CAP_DONE_INT_EN.
Group id is hunted down similarly.Order can be following form: RX_LCAS_GID_CAP_PORT, RX_LCAS_GID_CAP_DONE_INT_EN etc.
The DRAMFIFO level is measured and is configured in the software of channel according to suitable threshold.The form of order can be RX_VCAT_DRAM_FIFO_LVL_CAP_CHAN, RX_VCAT_DRAM_FIFO_LVL_THSLD, RX_VCAT_DRAM_FIFO_LVL_CAP_DONE_INT_EN, RX_VCAT_DRAM_FIFO_BELOW_THSLD_CHG_INT_EN or other similar forms.
Interrupting summation enables configurable in various environment and application program.For example, interrupt enable bit can be configured to be positioned at the interruption summation mode bit of STS level (48 bit register).They can also be configured to be positioned at the interruption summation mode bit of VT level (48 * 28 bit register).They can also be configured to be positioned at the interruption summation mode bit of interruption summation mode bit that port level (128 bit register) locates, all channels or/and the interrupt enable bit of all of the port, interrupt the summation mode bit.It should be appreciated by those skilled in the art that various interrupt configuration enable different application programs.
DRAM can be configured to utilize and interrupt enabling to read asking FIFO to overflow.Command forms can be RX_VCAT_DRAM_RD_WR_FIFO_OVFL_CNT_CHG_INT_EN.
Equally, DRAM can be configured to enable to write unripe (static state) mistake and interrupt enabling, and its form can be RX_VCAT_DRAM_WR_NOT_RDY_ERR_INT_EN.Similarly, DRAM can be configured to read unripe (static state) mistake and interrupt enabling, and its form can be RX_VCAT_DRAM_RD_NOT_RDY_ERR_INT_EN.
5.3.2 channel level interrupts enabling configuration
Channel interruption enables configuration parameter and can be combined in the twin port of memory, for example 1344 * 12 twin port memories.This can be by high-order and low order Channel Sharing.An example is a following table, and it shows the structure of the clauses and subclauses in this memory:
| Parameter | Size | Static | Value after the initialization |
| RX_CH_VCAT_OOM1_CHG_INT_EN | 1 | |
0 |
| RX_CH_VCAT_OOM2_CHG_INT_EN | 1 | |
0 |
| RX_CH_VCAT_LOM_CHG_INT_EN | 1 | |
0 |
| RX_CH_VCAT_ACC_ESL_CHG_INT_EN | 1 | |
0 |
| RX_CH_NL_VCAT_SQM_CHG_IN_EN | 1 | |
0 |
| RX_CH_LCAS_SO_CHG_INT_EN | 1 | |
0 |
| RX_CH_LCAS_CTRL_CHG_INT_EN | 1 | |
0 |
| RX_CH_LCAS_CRC_ERR_CHG_INT_EN | 1 | |
0 |
| RX_CH_LCAS_NL_SRRC_INT_EN | 1 | |
0 |
| RX_CH_CFG_PRTY_ERR_CHG_INT_EN | 1 | |
0 |
| RX_CH_CTRL_PRTY_ERR_CHG_INT_EN | 1 | |
0 |
| Odd | 1 | N/ |
1 |
In a preferred embodiment, hardware does not forbid coming the interruption of self-channel, and described channel has clauses and subclauses in having the memory of parity error.
5.3.3 receiver port level interrupts enabling configuration
Following table shows the receiver port and interrupts enabling configuration parameter:
| Parameter | Size | Static | Value after the initialization |
| RX_SK_VCAT_RBID_CHG_DONE_INT_EN | 1 | |
0 |
| RX_SK_LCAS_GID_ERRCHG_INT_EN | 1 | |
0 |
Note, in trigger, realize, so not configuration or control parity check in receiver port level because receiver port grating is put with state parameter.
5.3.4 the source port level interrupts enabling configuration
Following table shows the source port level and enables configuration parameter:
| Parameter | Size | Static | Value after the initialization |
| RX_SO_LCAS_MST_CHG_INT_EN | 1 | |
0 |
| RX_SO_LCAS_RS_ACK_CHG_INT_EN | 1 | |
0 |
Note, because source port does not have configuration parameter or state variable, so configuration or control parity check are not interrupted enabling at source port level place.
5.3.5 global state
Global state can comprise MFI trapped state, DRAM-FIFO level measurement state, interrupt the summation state, comprises following parameters: DRAM read request FIFO overflows, DRAM writes and do not prepare wrong and other state informations.Some examples are as follows:
The MFI trapped state:
○RX_VCAT_CHAN1_MFI
○RX_VCAT_CHAN2_MFI
○RX_VCAT_MFI_CAP_DONE
The DRAM-FIFO level is measured state:
○RX_VCAT_DRAM_FIFO_LVL
○RX_VCAT_DRAM_FIFO_LVL_CAP_DONE
○RX_VCAT_DRAM_FIFO_LVL_BLW_THSLD_CHG
Interrupt the summation state:
ο is in the interruption summation status bits (in 2 registers) of STS level
ο is in the interruption summation status bits (in 48 registers) of VT level
ο is in the interruption summation status bits (in 4 registers) of port level
The interruption summation status bits (in the STS level) of all channels of ο
The interruption summation status bits of ο all of the port
DRAM reads to require FIFO to overflow:
○RX_VCAT_DRAAM_RD_REQ_FIFO_OVFL_CNT
○RX_VCAT_DRAM_RD_REQ_FIFO_OVFL_CNT_CHG
DRAM writes and does not prepare mistake:
○RX_VCAT_DRAM_WR_NOT_RDY_ERR
Following global interrupt mode bit can be combined in the register:
●RX_VCAT_MI_CAP_DONE
●RX_VCAT_DRAM_FIFO_LVL_CAP_DONE
●RX_VVCAT_DRAM_FIFO_LVL_BLW_THSLD_CHG
●RX_VCAT_DRAM_RD_REQ_FIFO_OVFL_CNT_CHG
●RX_VCAT_DRAM_WR_NOT_RDY_ERR
The interruption summation status bits of all channels
The interruption summation status bits of all of the port
5.3.6 channel level interrupt status
Except RX_CH_VCAT_FAIL_STICKY_STICKY, all channel interruption parameters can be combined in twin port 1344 * 12 memories, and it is by high-order and low order Channel Sharing.Following table shows the example of entry structure in this memory configurations:
| Parameter | Size | Value after initialization and |
| RX_CH_VCAT_OOM1_CHG | ||
| 1 | 0 1 | |
| |
1 | 0 1 |
| |
1 | 0 1 |
| |
1 | 0 1 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
Alternatively, when RX_CH_VCAT_MFI_EN was set to zero, these positions can reset.
Equally, for the low order channel of carrying spread signal label (lable), such parameter can be effective.Hardware can not be configured to detect when extracting the spread signal label, whether has used the V5 position of expression spread signal label.Equally, such memory can not protected by parity check.
5.3.7 receiver port level interrupt status
Below be the example of receiver port interrupt status parameter, wherein order is RX_SK_VCAT_RBID_CHG_DONE, and size is 1 bit, and is that value after initialization or receiver port reset is 0.If putting with state parameter, all receiver port gratings in trigger, realize, will be on receiver port level less than configuration or control parity check.
5.3.8 source port level interrupt status
The example of source port level interrupt status parameter is RX_SO_LCAS_MST_CHG and RX_SO_LCAS_RS_ACK_CHG, and wherein, each size is 1 bit, and the value that has after initialization is zero.If do not have the state variable or the configuration parameter of source port, can not have configuration or control parity error interrupt status position so at source port level place.Equally, if there is not the source port level to reset, these state variables must be written as 1 to remove by software always.
5.4 interrupting summation produces
The interrupt status summation can produce on several levels.The summation that for example, can have all interrupt status parameters that are relevant to STS-1.Note, shine upon, then this and the interrupt status parameter that covers all the VT channels among this STS if STS-1 is VT.STS interrupts the summation bit and is kept in 48 triggers.
The summation that can also have all the interrupt status parameters relevant with the VT channel.VT is organized and is remained on by STS in total position in 48 * 28 the trigger.If the STS channel is not VT mapping, the summation mode bit corresponding to the VT channel of this STS will be eliminated trigger so.
The summation that can also have all the interrupt status parameters relevant with the receiver port.Notice that these interrupt parameters are that VCAT is just meaningful when enabling at the receiver port only.The receiver port interrupts total position and will remain in 128 triggers.
The summation that can also have in addition, all the interrupt status parameters relevant with source port.Notice that these interrupt parameters are that LCAS is just meaningful when enabling at the receiver port only.Source port interrupts total position and will remain in 128 triggers.
When resetting channel, CFG removes the interrupt status position of this channel.It does not directly remove the total interrupt bit relevant with this channel.When the receiver port was reset, CFG removed the interrupt status position of this receiver port.It does not directly remove the total interrupt bit relevant with this receiver port.Do not exist the source port of removing source port level interrupt status position to reset.Software need write RX_SO_LCAS_MST_CHG and RX_SOL_LCAS_RS_ACK_CHG interrupt status position with its removing with 1.Do not enable configuration bit if the interruption of specific interruption mode bit is set, this interrupt status position is for not contribution of summation so.
5.4.1 the channel interruption summation produces
Channel interruption when the CFG block configuration becomes to handle from two independent sources, for example, from ANA and ALIG_RB/LVC.In order to handle this situation, CFG can be configured to two dual port stores of independence are used for channel level interrupt status parameter from ANA and ALGN_RD/LVC.In order to carry out the interruption summation, the CFG module can read channel interruption status register and receiver and source port interrupt status register constantly.Channel interruption summation production process and CPU share the port on the twin port memory, wherein, and the parity check that the CPU access is given.
6 schedule fault register modules (CFR)
6.1 summary
The CFR module can have multiple function.For example, it can have following function: the first, store all channel level configurations.Equally, based on the whole DRAM that distributes to VCAT, channel type and DRAM diagnostic mode, dispensed is given the start and end address of the dram space of channel.In addition, it can also dispose based on channel architecture, is configured to produce the schedule (1x, 2x, 56x and 62x) of the internal freedom operation that is used for whole VCT_RX functional block.It can also be configured to channel configuration and fault/reset mode distributed to together in company with calendar information other module.And it can also be disposed for VCAT and adjust troubleshooting.Schedule generation, dram space position and troubleshooting function are described in " VCT_Aligner " document.
6.2 interface
The CFR module is connected to ANA, ALIG_WR, ALIG_RD and CFG module.Referring to " vct_rx_cfr " micro-structural document at interface signal.
6.2.1 the interface of ANA
For ANA, the interface of ANA is used to obtain channel configuration information at first.But the response to structural requirement from ANA also comprises channel fail bits (fail bit) except configuration parameter.
The ANA module is not handled the channel failure indication from the CFR module.It only sends to the ALIG_WR module with this signal, and this module utilizes this signal to judge whether data are write among segmentation (staging) FIFO of correlated channels, and judges whether destroy the write pointer of correlated channels.Notice that the channel fail condition can exist, even the ANA module does not have the alarm on the reporting channel.
CFR will send to ANA as the CH_CFG_PRTY_ERR condition of the part of configuration response.Although this is not the requirement of ANA function, ANA is stored in such position in its status register.When it detects variation, will produce CFG and interrupt.
6.2.2 the interface of ALIC_WR
The CFR interface of ALIG_WR has the 1x of depending on and two independent signal groups of 2x schedule:
The sets of signals based on the 2x schedule of CFR is used for the TID of the channel of current schedule circulation and its failure scenarios are passed to ALIG_WR, and it utilizes them that data are moved to data among the main FIFO from the FIFO of segmentation; And
The sets of signals of CFR based on the 62x schedule, be used for TID, its failure scenarios of the channel of current schedule circulation and distribute to its beginning in space and the address of end passes to ALIG_WR in DRAM, it utilizes them that data are moved to DRAM from main FIFO.
6.2.3 the interface of ALIG_RD
In one embodiment, the CFR interface of ALIG_RD has 5 independently sets of signals, and four in these signals can be based on 56x, 62x and 1x schedule.
The sets of signals based on the 56x schedule of CFR is used for TID, its failure scenarios of the channel of current schedule circulation and distributes to its beginning in space and the address of end passes to ALIG_WR in DRAM, it utilizes them that data are moved to the main FIFO of channel and the main FIFO of the channel that resets from DRAM.
Another of CFR based on the sets of signals of 2x schedule be used for the TID of the channel of current schedule circulation and it reset and failure scenarios passes to ALIG_WR, it utilizes them that data are moved among the segmentation FIFO of channel from the main FIFO of channel, and the segmentation FIFO of the channel that resets.
Another of CFR based on the sets of signals of 1x schedule be used for the TID of the channel of current schedule circulation, it reset and failure scenarios, it configuration, it type, it produces counter and passes to ALIG_WR as the reset mode of the VCG under the branch road, its parity state of config memory clauses and subclauses and current schedule, it utilizes them that data are moved among the LVC from the FIFO of the segmentation transportation of channel, and reset its channel kept and VCG state.
Utilize the channel configuration data of 1x schedule transmission can comprise not only by the ALGI_RD needs also by downstream LVC and the needed data of DSQ module.Channel type and schedule produce counter and are used by ALIG_RD and DSQ.
Another sets of signals can be based on the 1x schedule that is used for ALIG_WR, thereby gives CFR with the TID of the channel in the current schedule circulation, its DRAM overflow error or alarm detection state transfer, and it utilizes them to upgrade channel and VCG status of fail.Other sets of signals cannot still can be used by ALIG_RD based on schedule, thereby obtains the status of fail of channel from CFR.
In mutual between CFR and CFG, CFR is to read and to write channel configuration in the CFG visit.CFR is configured to interrupt event is sent to CFG.
6.3 configuration
The CFR module is safeguarded all every parameter channel configuration and STS channel architecture configuration parameter.Disregard resequencing buffer sign (RX_SK_VCAT_RBID0/1), it safeguards that all receiver port gratings put parameter.Configuration information is sent in the functional block that needs it in company with 1x schedule pipeline together.
6.3.1 STS channel interface configuration
STS channel architecture configuration register utilizes 48 * 9 trigger realization.
| Parameter | Size | Static | Value after the initialization |
| RX_CH_STS_VT | 1 | |
0 |
| RX_CH_STS_VC4 | 1 | |
0 |
| RX_CH_STS_VTG_TYPES | 7 | |
0 |
Note 1: the channel architecture configuration parameter is static in some sense, and when any current channel that is subjected to variable effect was broken away from reset mode, they should not change.Equally, the variation of these parameters in the VCT_RX functional block should be carried out with the response configuration consistency ground in the SONET/SDH receiving function piece.
6.3.2 channel level configuration
Because the ANA module need be about the 1x schedule asynchronous access configuration information of free-running operation, this schedule drives other modules, so duplicated in independent twin port memory by the desired configuration information of ANA.When these parameters of software upgrading, two memories have also been upgraded.When software reads them, obtain by the value in the employed memory of 1x schedule.
6.3.2.1 the memory of the channel configuration of 1x schedule access
All channel level configuration parameters are combined in 1344 * 25 twin port memories, and it is shared by high-order and low order channel.Following table shows the structure of the clauses and subclauses in this memory:
| Parameter | Size | Static: | Value after the initialization |
| RX_CH_SW_CFG_EN | 1 | N/ |
1 |
| RX_CH_VCAT_MFI_EN | 1 | |
1 |
| RX_CH_SK_LPID | 7 | |
0 1 |
| RX_CH_VCAT_ACCEPTED | 1 | |
0 2 |
| RX_CH_LCAS_REV_EXT_EN | 1 | |
0 |
| RX_CH_LCAS_REV_EXT_SO_LPID | 7 | |
0 |
| RX_CH_NL_VCAT_EXP_SQ | 6 | |
0 1 |
| Odd | 1 | N/ |
1 |
Note 1: these parameters do not need to have the initial value that is used to operate purpose, yet for the parity check protection, they are set to 0.
Note 2: during operational cycle, before channel is broken away from reset mode,, should the RX_CH_VCAT_ACCEPTED parameter be set to zero so if channel belongs to the VCG that LCAS enables.
Attention 3:RX_CH_VCAT_MFI_EN is independent of RX_CH_SW_CFG_EN and uses.Referring to the discussion in 7.4 chapters and sections.
6.3.2.2 the memory of the channel configuration of ANA access
The desired following configuration parameter of ANA is combined in 1344 * 10 twin port memories, and it is shared by high-order and low order channel.Following table shows the entry structure in this memory:
| Parameter | Size | Static | Value after the initialization |
| RX_CH_SW_CFG_EN | 1 | N/ |
1 |
| RX_CH_VCAT_MFI_EN | 1 | |
1 |
| RX_CH_SK_LPID | 7 | |
0 1 |
| Odd | 1 | N/ |
1 |
Note 1: for the operation purpose, such parameter does not need to have initial value.Yet for the parity check protection, they are set to zero.
6.3.3 receiver port grating is put
Utilize 128 * 4 triggers to realize following receiver port configuration parameter:
| Parameter | Size | . static state | Initialization or receiver port reset |
| RX_SK_SW_CFG_EN | 1 | N/ |
1 |
| RX_SK_VCAT_EN | 1 | |
0 |
| RX_SK_LCAS_EN | 1 | |
0 |
| RX_SK_VCAT_RBID_SEL | 1 | |
0 |
Note 1: when existence maps to the channel of breaking away from reset mode of this port or when RX_SK_SW_CFG_EN not being set, should not change RX_SK_VC_EN and RX_SK_LCAS_EN configuration parameter.
6.4 state
Send the parity error in the channel configuration memory to the ALIG_RD module, it is stored in them in the channel status memory of self.So just avoided and in this module, to have had status register.
Because state parameter need carry out access by all three schedules in the CFR functional block, so utilize 1344 triggers, the RX_CH_VCAT_FAIL_STICKY state parameter is realized in the CFR functional block.
| Parameter | Size | Value after the |
| RX_CH_VCAT_FAIL_STICKY | ||
| 1 | 0 |
Notice that in some sense, RX_CH_VCAT_FAIL_STICKY is not typical state parameter, it is not the active state of fault.It more may be an interrupt parameters, and in some sense, it is the value that latchs, and still, also needs to write 1 with its removing to it in software.Yet it not exclusively resembles other interrupt status parameter, does not interrupt because it does not produce also, and thereby does not have relevant interruption and enable parameter.This is intentional, because cause faults will produce interruption.
6.5 situation
The CFR module is utilized the malfunction of trigger maintenance channel and VCG.Equally, the CFR module is kept the counter that is used for each channel, thereby removes their fault/reset mode, to guarantee for all modules channel-failures/reset and keep the ground long enough being detected.These counters utilize 1344 * 7 twin port memories (not having the parity check protection) to realize.More detailed situation is referring to " vct_rx_cfr " micro-structural document.
6.6 interrupt event
CFR produces following interrupt event to CFG:
·RX_CH_CFG_PRTY_ERR_CHG
6.7 schedule produces
Schedule produces and is based on the configuration of STS channel architecture and four internal counters.Referring to " VCT_Aligner " framework and " vct_rx_cfr " little framework.
6.8 troubleshooting
Referring to " VCT_Aligner " framework and " vct_rx_cfr ".
7 MFI analyzers (ANA)
7.1 summary
Referring to Fig. 5, show the embodiment of MFI analyzer.ANA502 and interconnection (CXC) 504, separate preface device 506, adjust write device (align writer) 508, incoming frame module (IFR) 510, configuration module (CFG) 512 and CFR514 and be connected.ANA also comprises channel (CH) situation/status register and non-VCAT channel data memory.In one embodiment, ANA carries out following function:
Based on the configuration that is stored in the CFR module, the VCAT data packet traffic is divided from non-VCAT data packet traffic
On the VCAT channel, before sending it to ALIG_WR, except the H4/K4 byte that is used for VCAT/LCAS, remove all expenses and byte of padding (stuffbyte)
On non-VCAT data packet channel, before it is write internal data buffer, remove all expenses and byte of padding
For the VCAT channel, carry out MFI locking (lock) state machine based on the coupling that is stored in the global programming in the CFG module and the counter that do not match
The CXC alarm that to represent on the VCAT channel combines with the MFI loss of adjusting, single alarm conditions are represented the module to ALIG_WR
With data byte, the current MFI value of channel is offered ALIG_WR module (when channel is not in alarm conditions)
MFI lock-out state on each channel is offered software
When the CFG functional block requires, catch the snapshot (snapshot) of VCAT channel to last MFI value
Extract the spread signal label of low order channel
Before sending it to IFR, will merge from VCAT data packet traffic and the non-VCAT data packet traffic of DSQ.
7.2 the interface of CFR
When the ANA module when the CXC of given channel obtains effectively request, it requires the configuration of this channel to CFR.Channel is by discerning based on channel id with from 11 ana_cfr_tid signals of the signal type of CXC.The configuration information that is returned by CFR that is used for channel comprises following content:
On this channel, whether enable MFI and analyze (RX_CH_MFI_EN)
At the remainder of VCT_RX functional block, whether channel is in reset mode (RX_CH_SW_CFG_EN)
Whether channel is relevant with VCAT enable logic port
As follows, the ana_cfr_tid signal comes from the CXC signal:
If (cxc_vct_rx_sts_vt){
ana_alig_wr_tid＝cxc_vct_rx_sts＊28+c×c_vct_r×_grp＊4+
cxc_vct_rx_vt
}
Else{
ana_cfr_tid＝cxc_vct_rx_sts_master＊28
}
Notice that ana_cfr_tid always is provided with based on cxc_vct_rx_sts_master.Used this method of the continuous cascaded series of VC4-Nc that is used to carry non-VCAT data (wherein, N 〉=2), single channel configuration clauses and subclauses.
CFR sends the CH_CFG_PRTY_ERR condition to ANA as the part of configuration response.Although this is not the desired function of ANA, ANA is stored in such position in its status register.When it detects the variation generation, will produce the interruption of CFG.
7.3 the interface of ALIG_WR
If the configuration result from CFR shows that channel belongs to VCG, ANA will produce the request to ALIG_WR so.
The combination of the OOM1/2 state of the ana_alig_wr_alm alarm signal that to be ANA obtain from the CXC of this channel and this channel.
As follows, the ana_alig_wr_alm signal comes from the CXC signal:
If (cxc_vct_rx_sts_vt){
ana_alig_wr_tid＝cxc_vct_rx_sts＊28+cxc_vct_rx_grp*4+
cxc_vct_rx_vt
}
Else If(I cxc_vct_rx_sts_au4){
ana_alig_wr_tid＝cxc_vct_rx_sts＊28
}
Else {
ana_alig_wr_tid＝(cxc_vct_rx_sts ％ 16)＊28
}
As follows, the ana_alig_wr_sof signal comes from the CXC signal:
If (cxc_vct_rx_sts_vt){
ana_alig_wr_sof＝cxc_vct_rx_vt_sof
}
Else {
ana_alig_wr_sof＝(cxc_vct_rx_row＝＝0)&&(cxc_vct_rx_col＝＝0)
}
Ana_alig_wr_ch_ctrl_prty_err and ana_alig_wr_mfi signal be respectively based on current MFI field value and parity error position, and be the status register clauses and subclauses by the position of the value index of ana_alig_wr_tid signal.
7.4 enabling to contrast channel, channel MFI resets
Channel MFI enable operation is independent of the channel reset operation and carries out.Channel resets does not influence the MFI of ANA module capturing function and MFI state machine.Just MFI enables to control these functions.The ANA module is utilized channel to reset to judge whether make data to pass through.
Even when channel is in reset mode, if analyzing, MFI is enabled, ANA handles MFI information and carries out the MFI capturing function.Such pattern is favourable for the difference time-delay variation that measurement can occur on the existing VCG, because new channel-attach, and reality does not influence upward data flow of this VCG.This will describe in detail in chapters and sections 7.8.
When channel is not in reset mode, can forbid that MFI analyzes.Such situation can not used in normal running.This is favourable for quick lock in operation during verifying.Under such pattern, because the OOM/LOM mode bit is set to default (that is, when MFI enables not to be set up), ANA will just indicate the manager to ALIG_WR to alarm conditions at first.For the quick lock in operation, when workbench (bench) detected the H4/K4 byte that use, it write with back door (back-door) RX_CH_MFI_EN is set.
If resetted channel, no matter whether be provided with RX_VCAT_MFI_EN, ANA does not send to ALIG_WR with any request, perhaps any data is not write non-VCAT data buffer.
If on channel, detect the control parity error, note, need to trigger RX_VCAT_MFI_EN and RX_CH_SW_CFG_EN position.This is because the source of parity error can be in the status register of ANA or in the status register of other modules.
7.5 the interface of CFG
For following purpose, the ANA module is connected to the CFG module:
In order to send interrupt event (that is, the OOM1/2 of channel, LOM or CFG_PRTY_ERR state change)
In order to obtain the global configuration parameter that the MFI lock state machine uses
In order to provide to being stored in the visit of the channel MFI lock-out state in the ANA module
In order to receive the MFI request of catching and to send the value of catching.
7.5.1 channel status
LVC provides following channel condition information to CFG:
·RX_CH_VCAT_OOM1
·RX_CH_VCAT_OOM2
·RX_CH_VCAT_LOM
RX_CH_ACC_ESL (only being used for the low order channel)
·RX_CH_CFG_PPTY_ERR
Notice that even ANA does not have any channel level configuration, it also obtains to be used for the parity error situation of the channel configuration memory of CFG, and it is stored in its situation and represents in the status register of CFR.As shown below, when having variation, it also produces interruption.
Although the channel conditions memory of ANA is protected, ANA does not provide control parity error state or interrupts for it produces.On the contrary, it is controlled the parity check condition with channel and sends ALGI_WR to, and ALIG_WR sends it to ALIG_RD, channel control parity error state then is provided and produces to interrupt.
7.5.2 interrupt
Be following incident, the channel interruption state that LVC produces for CFG is provided with request:
·RX_CH_VCAT_OOM1_CHG
·RX_CH_VCAT_OOM2_CHG
·RX_CH_VCAT_LOM_CHG
RX_CH_ACC_ESL_CHG (only being used for the low order channel)
·RX_CH_CFG_PRTY_ERR_CHG
7.6 the interface of DSQ
The ANA module obtains the VCAT data from DSQ, so that itself and IFR non-VCAT data are before merged.Interface from DSQ comprises that ANA is used for obtaining the dsq_ana_tid signal of data from the internal data buffer of non-VCAT channel.
7.7 MFI lock state machine
With reference to " vct_mfi_ana_uarch " document.
Notice that when not being in LOM, ANA sends the MFI value of expectation rather than the value that receives to ALIG_WR in the H4/K4 byte.
7.8 MFI catches
7.8.1 difference Time delay measurement
During supplying, be given as the DRAM capacity that VCAT distributes, need judge whether the difference time-delay of the alternative branch road interchannel of VCG can be supported.Orion provides a kind of mechanism, the MFI value of two channels of this mechanism Short Description.By doing like this, to combination, software can determine difference time-delay maximum among the VCG for all suitable branch roads.
When new channel will be increased to given LCAS VCG, maximum difference time-delay was determined in expectation, and this maximum difference time-delay will be put into practice on VCG, and can not carry out related with this VCG channel practically.Do the data flow (caused at least potentially and stopped) that can influence on this VCG like this.If untapped receive logic port is effective, break away from reset mode when avoiding this incident when it, such channel can at first be mapped to such port.Yet this is not practicable always.
The solution of this problem is to make the RX_CH_VCAT_MFI_EN position to be independent of the RX_CH_SW_CFG_EN position.ANA is used as all positions (comprising the spread signal tag extraction) that reset based on the function of MFI analysis with RX_CH_VCAT_MFI_EN.It as the position that resets, only is used for the RX_CH_SW_CFG_EN position expense/filling and revises (pruning), data separating and data pooling function.
Utilize this scheme, when on the channel that will be increased to VCG, carrying out the difference Time delay measurement, only have the RX_CH_VCAT_MFI_EN position of this VCG initially to be provided with.In case carry out Time delay measurement and this channel can be increased to actual VCG, can remove the RX_CH_VCAT_SW_CFG_EN position.
7.8.2 interface and operation
When software write overall RX_VCAT_MFI_CAP_CHAN1/2 register in the CFG module, the CFG module will send to the ANA module to the MFI request of catching with the sign of two channels.In response, ANA reads the MFI value, and it has the condition memory that is used for based on two channels of CXC request, and will carry out signal and send to CFG with the value that it reads.
When having the CFG module of the MFI value that is stored in two channels in the situation memory, the MFI analyzer does not check whether channel is in the MFI lock-out state.Whether software inspection channel before request is caught in generation is in the MFI lock-out state.Yet if broken away from the MFI locking after the time that channel obtains to ask through ANA, the MFI value can not be effective.Guarantee after catching generation, not have the MFI loss of locking to occur by software.
Notice that the MFI analyzer does not check whether channel is that MFI enables or whether they are VCAT channels.Catch if software is attempted to carry out on such channel, it will obtain hash.
When being in operation for previous one, software can not produce fast enough for the write request of CFG and catch request to send ANA.So ANA does not need to worry the generation of this situation.
7.9 spread signal tag extraction
On the low order channel, ANA is from extracting the spread signal label from 32 frames (adjusting based on 12 MFAS patterns) of first formation of K4 byte.If received identical value three times in row's channel, ANA writes into such value in the status register clauses and subclauses of this channel as the spread signal label of reception.
Spread signal tag extraction on given channel depends on the OMM1 state of this channel significantly.When channel was in the OOM1 state, ANA did not carry out extraction.
When being in the IM1 state, ANA confirms based on the MFI1 counter whether the K4 byte carries ESL position (that is, must between 11 and 18).
7.10 configuration
The ANA module does not have any configuration parameter of himself.
7.11 situation
7.11.1 public situation
When waiting for that the CXC schedule obtains second channel, catch a MFI value that reads in the self-channel situation memory of request in response to MFI and need be stored in the public register.
7.11.2 channel conditions
The channel conditions parameter combinations is in 1344 * 45 twin port memories.By the write and read visit of CXC request driving to it.
Some condition parameter only are only applicable to the low order channel.Therefore, be used for high-order channel or low order channel, in channel status memory, have two kinds of different entries according to clauses and subclauses.
The RX_CH_CFG_PARITY_ERR_COPY position that is stored in this memory is not the real state parameter that ANA uses.When software was removed RX_CH_VCAT_MFI_EN, when resetting other mode bits all, when RX_CH_SW_CFG_EN is set, this position was reset.
7.11.3 the high-order view of channel status memory clauses and subclauses
Following table shows the entry structure in this memory:
| Parameter | Size | The value of (1 is used for PRTY_ERR) after the initialization or when the MFI_EN of channel (SW_CFG_EN that is used for PRTY_ERR) is set to zero |
| RX_CH_VCAT_CUR_MFI | 12 | 0 |
| |
1 | 0 |
| |
3 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
3 | 0 |
| |
8 | 0 |
| |
1 | 0 |
| Do not use | 14 | 0 |
| |
1 | 1 |
7.11.4 the low order view of channel status memory clauses and subclauses
| Parameter | Size | The value of (1 is used for PRTY_ERR) after the initialization or when the MFI_EN of channel (SW_CFG_EN that is used for PRTY_ERR) is set to zero |
| RX_CH_VCAT_CUR_MFI | 10 | 0 |
| |
4 | 0 |
| |
3 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
3 | 0 |
| |
8 | 0 |
| |
4 | 0 |
| |
8 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 1 |
7.12 state
Because state parameter is overall, remain in the CFG functional block so catch relevant state parameter with MFI.
Channel state parameter is combined in 1344 * 12 twin port memories.
| Parameter | Size | The value of (1 is used for PRTY_ERR) after the initialization or when the FMI_EN of channel (SW_CFC that is used for PRTY_ERR) is configured to zero |
| |
1 | 1 |
| |
1 | 1 |
| |
1 | 1 |
| |
8 | 0 1 |
| |
1 | 0 |
Note 1: this parameter only is only applicable to the low order channel.Equally, if channel is in the OOM1 state, its value will can be ineffective.
7.13 non-VCAT channel data buffer
Non-VCAT channel data buffer utilizes two memories to carry out.First is 1344 * 8 twin port memories, and except that VC4, it is shared at low order channel and high-order interchannel.Second is 256 * 8 twin port memories, and it is used by VC 4 channels.
Because making, it realizes being used for the FIFO intention of VC 4-Nc application program than being easier to, so independent memory is used for VC 4 channels.Single FIFO intention is required for VC4-Nc (N 〉=2) situation, with the occasion of supporting that received frame disposes in the 4Xoc-3/12 model.In this case, CXC will be presented on the byte that receives on the different frame in staggered mode for the VCT_RX functional block.Yet, be used for VCT_RX and seem to be staggered in the OC-48 circuit with 1x schedule supposition VC 4 channels that obtain non-VCAT data from ANA.Do not use single FIFO for given VC 4-Nc, when CXC when not providing byte during the time slot that is used for this VC 4-Nc (that is, idle time slot), this can make data orders destroyed.
The memory of VC4 channel is used to carry out 16 FIFO, and each FIFO16 byte long is to handle all possible VC 4-Nc combination (comprising N=1, so that do not produce special circumstances).
Writing two memories is driven by the CXC request.For the high-order time slot relevant with VC 4 channels (that is, from sts_vt=0, the sts_vc4=1 of CXX), ANA utilizes VC 4 buffer storage.CXC represents among the VC 4-Nc (N 〉=1) the main STS channel id from STS.ANA can use it to determine to write data to which VC 4 FIFO.
DSQ drives reading in buffer storage, and it is in turn driven by the 1x schedule.For with the relevant time slot of VC 4 channels, ANA can not judge which FIFO is used in VC 4 buffer storage of the TID that is provided by SDQ.ANA knows that information that CXC provides is to judge this.The ANA storage is used for the bit of VC 4 to show that VC 4 is from VC 4-Nc or main VC4-Nc.For from VC 4, the ID of main VC 4 can determine from these mode bits.
Notice that circulate (rotation) afterwards from channel in the moment that basic SDH receiver side is broken away from (comprising CXC) reset mode at least one schedule, VC 4 channels among the VCT_RX must be broken away from reset mode.This needs, because attempting before VC 4 data buffers read, the VC 4 major state positions of ANA storage must be set.
ANA pipeline (pipeline) should provide bypass for the read and write conflict of single byte buffer, overflows avoiding.ANA utilizes 1344 triggers to have each channel data significance bit.When the channel that resets (set RX_CH_SW_CFG_EN), should remove this data significance bit.
Not needing provides the read and write bypass for 16 byte VC4FIFO.
7.14 merge VCAT and non-VCAT data
The dsl_ana_tid signal of separating preface device (DSQ) drives the merging of VCAT and non-VCAT data.ANA reads the non-VCAT data buffer relevant with the value of this signal.If do not insert dsq_ana_vld, and non-VCAT data buffer is not empty, will be sent to IFR from the data of VCAT data buffer so.If inserted dsq_ana_vld, so dsq_ana_data is sent to IFR.In two kinds of situations, utilize dsq_ana_lpid restricting data as LPID.If do not insert dsq_ana_vld, and non-VCAT data buffer is empty, do not have data can be transmitted to IFR so.
Notice that in order to prevent overflowing of non-VCAT data buffer, guarantee to break away from when resetting in the VCT_RX functional block, all channels all will be in reset mode (RX_CH_SW_CFG_EN=1) at first.
8 LCAS/VC controllers (LVC)
8.1 summary
With reference to Fig. 6, show LVC 602, it is conciliate preface device 606 with adjusting module (ALN), configuration (CFG) 608 and is connected.LVC comprises CH situation memory, CH status register, SK situation memory, SK status register and SO status register.The LV module is connected to ALIG_RD, DSQ and CFG module.The basic function of LVC module is as follows:
From the H4/K4 byte, extract forward control information (SQ in the LCAS situation and CTRL)
From the H4/K4 byte, extract the reverse control information of LCAS
Carry out the CRC check that the LCAS control data is wrapped
Carry out the dCRC setting/removing function of each LCAS VCG
The GID that carries out on the LCAS VCG checks
Catch GID value by the branch road reception of given LCAS VCG
Synchronously control (that is sequence) and send to the data of DSQ
Based on the authorization configuration of channel, handle the LCAS channel and reset and fault condition
When receiver is configured to LCAS, the detection in non-LCAS source.
Fig. 4 G:LVC module
8.2 the interface of ALIG_RD
No matter whether valid data (not only load and H4/K4) byte can be at the LVC that is delivered in this circulation on this channel, and the ALIG_RD LVC in each clock circulation provides the ID (being TID) of following configuration and control information and channel.
8.2.1 configuration information
Because all config memorys in the VCT_RX functional block maintain in the CFR module, the CFR module need send LVC and the needed configuration of downstream DSQ (except RX_SHORT_FRAMF_EN) pipeline to LVV by ALIG_RD.For the request from ALIG_RD to LVC of given channel, LVC need be used for himself the operation the following configuration parameter relevant with this channel:
·RX_CH_STS_VT
·RX_CH_SK_LPID
·RX_SK_LCAS_EN
·RX_CH_NL_VCAT_EXP_SQ
·RX_CH_VCAT_ACCEPTED
·RX_CH_LCAS_REV_EXT_EN
·RX_CH_LCAS_REV_EXT_SO_LPID
Also need to make it they pipelines can be sent to DSQ with only providing to VLC by the DSQ buffer desired following calendar information of overturning.LVC only passes by these parameter transmission, and without any processing.This also means that these are the only parameters that send DSQ to.
·RX_WID
·RX_CH_VC4
·RX_CH_STS_VTG_TYPE
When channel is in status of fail, above schedule and configuration information should be offered LVC.
When a path channels of authorizing entered failure or reset mode, DSQ need make current write buffer invalid.In order to do like this, to need to enter first of reset mode at a path channels at least and send the RX_SK_LPID configuration parameter to DSQ in the circulation all the time.When the software-reset channel, before the configuration that changes this channel, should wait for the sufficiently long time, so that DSQ detects the replacement of this channel upper signal channel.
CFR sends to ALIG_RD with the configuration and the failure information of non-VCAT channel, its not acknowledgement channel whether be the VCAT channel.But notice that because ALIG_WR will not write data the DRAM that is used for non-VCAT channel, and ALIG_RD also will not read any data from DRAM, for such channel, this channel fail condition will be set up never again.For such channel, ALIG_RD just never offers LVC to the valid data of these channels, but it will still send schedule and channel configuration to LVC.
Notice that CFR makes the channel failure of all path channels of VCG failure becoming.Channel and VCG reset and are sent to LVC respectively by ALIG_RD.
8.2.2 control information
ALIG_RD offers ALIG_RD with following control information in each clock circulation:
Data are effective
The channel fail condition
Channel replacement condition
The salty condition of putting of receiver end
The indication of H4/K4 byte
·HO/LOMFI
·SOF
H4/K4 byte indication, HO/LO MFI and SOF effectively are correct and channel is not in the meaning that resets/have during status of fail in data only.
HO/LO MFI counter should not only provide in the circulation of H4/K4 byte clock, also should be in the circulation of SOF clock (during perhaps all clocks when channel is not in malfunction circulate usually).
8.2.2.1 H4
At current channel is that high-order channel and current byte are when being used for the H4 byte of this channel, and ALIG_RD is provided with H4/K4 sign position and gives VLG.Because TOH, other HO POH and the byte of padding in the STS-1 frame are just deleted before its content is write DRAM, are the load bytes so be used for the every other byte of high-order channel.
For VC 4/STS-3c type VCG, the H4 byte that ALIG_RD will only be used for main STS-1 sends LVC to.
8.2.2.2 K4
At current channel is that low order channel and current byte are when being used for the K4 byte of this channel, and ALIG_RD is provided with H4/K4 sign position and gives VLG.Because TOH, other HO POH and the byte of padding among the VT of mapping STS-1 frame are just deleted before its content is write DRAM, are the load bytes so be used for the every other byte of low order channel.
8.3 the interface of DSQ
If have schedule, configuration and control information, LVC provides following schedule, configuration and control information to DSQ in each the clock circulation with load byte.
8.3.1 schedule and configuration information
·RX_CH_STS_VT
·RX_CH_STS_VTG_TYPE
·RX_CH_VC4
RX_WID (cascade position of all circulations (wheel))
·RX_CH_SK_LPID
·RX_SK_VCAT_EN
Notice that LVC does not use RX_CH_STS_VTG_TYPE, RX_CH_VC4 and RX_WID information, it only is sent to DSQ with them, and does not carry out any processing, thereby they are used for the buffer upset.
The structure of 13 RX_WID signals is as follows:
| VC4_WID(4) | VC3_WID(2) | VC2_WID(3) | VC11_WID(2) | WC12_WID(2) |
8.3.2 control information
Load data is effective
The channel fail condition
Channel replacement condition
·DNU
·SQ
8.4 the interface of CFG
LVC produces the interrupt status set request to CFG.CFG reads application state (under the situation of source port status register, writing) request and is assigned to LVC.
8.4.1 state
LVC provides following state information to CFG:
RX_CH_LCAS_SQ/RXX_CH_NL_VCAT_ACC_SQ (different views)
·RX_CH_LCAS_CTRL
·RX_CH_LCAS_CRC_ERR
·RX_CH_NL_VCAT_SQM
·RS_SK_LCAS_GID_ERR
·RX_SO_LCAS_MST
·RX_SO_LCAS_RS_ACK
8.4.2 Interface status
LVC produces the interrupt status to CFG that is used for following incident request is set:
·RX_CH_LCAS_SQ_CHG/RX_CH_NL_VCAT_ACC_SQ_CHG
·RX_CH_LCAS_CTRRL_CHG
·RX_CH_LCAS_ERR_CHG
·RX_CH_LCAS_NL_SRC_CHG
·RX_CH_NL_VAT_SQM_CHG
·RX_SK_LCAS_GID_ERR_CHG
·RX_SO_LCAS_MST_CHG
·RX_SO_LCAS_RS_ACK_CHG
8.5 situation and state parameter
All situations and status register are twin port.The situation memory is only by hardware access.
A port of status register is exclusively used in the CPU access.Notice that CPU need write the source port status register with to its initialization.If the state read request from software is conflicted with the write request from hardware, will transmit as reading the result from the new value of write request.
Under the situation of source port status register, if conflict with state write request from hardware from the state write request of software, so should be with software value write memory.This should can not take place (be used for before this source port, software should be forbidden the reverse control information of LCAS) owing to the appropriate software behavior, but hardware should prepare to handle this conflict.
Hardware can be not surpass the same channel conditions memory entries (for STS-3 VCG) of frequency visit of per 16 clock circulation primary.Similarly, hardware can not write identical channel status memory clauses and subclauses with the frequency that surpasses per 16 clock circulation primary.If desired, microstructure design can be utilized such advantage.
Channel conditions has different views with the status register clauses and subclauses, depends on whether channel is mapped to LCAS or non-LCAS VCG.Notice that it is identical that reset values makes for two kinds of situation parity checks.In fact, carry out like this, used virtual bit for status register.
Port level state and state parameter only can be applicable to the port for the LCAS configuration.
How such memory is described in detail in the following chapters and sections and provides by hardware utilized.
8.5.1 channel conditions
The channel conditions parameter combinations is in 1344 * 40 twin port memories, by high-order and low order Channel Sharing.Following table shows the LCAS and the non-LCAS view of the entry in this memory:
8.5.1.1 the LCAS view of channel conditions memory entries
| Parameter | Size | Value after initialization or |
| RX_CH_LCAS_NEXT_SQ | ||
| 8 | 0 1 | |
| |
1 | 0 |
| |
6 | 0 1 |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
| |
8 | 0 |
| |
1 | 0 1 |
| |
1 | 0 1 |
| |
8 | 0 1 |
| |
1 | 0 1 |
| |
1 | 0 1 |
| |
1 | 0 1 |
| |
1 | 0 1 |
| |
1 | 0 1 |
| |
1 | 0 |
Note 1: for the operation purpose, these parameters do not need to have initial value.Yet because the parity check protection, they are set to zero.
8.5.1.2 the non-LCAS view of channel conditions memory entries
| Parameter | Size | Initialization or believe value after resetting |
| |
8 | 0 1 |
| |
1 | 0 |
| |
2 | 0 |
| |
1 | 1 |
| |
1 | 0 |
| Do not use | 26 | 0 |
| |
1 | 0 |
Note 1: for the operation purpose, these parameters do not need to have initial value.Yet because the parity check protection, they are set to zero.
8.5.2 channel status
Channel state parameter is combined in 1344 * 15 twin port memories, by high-order and low order Channel Sharing.Following table shows the LCAS and the non-LCAS view of the clauses and subclauses in this memory:
8.5.2.1 the LCAS view of channel status memory clauses and subclauses
| Parameter | Size | Value after initialization or |
| RX_CH_LCAS_CUR_SQ | ||
| 8 | 0 | |
| |
4 | IDLE(0x5) |
| |
1 | 0 |
| |
1 | 0 |
| Do not use | 1 | 1 |
Under the situation of LCAS VCG, software is sequence and the control field of reading of data to determine to receive on channel in the self-channel status register always.This is very important, because unlike the VCT_TX functional block, LCAS control information variation does not occur under the control of software, and judges for the first time that for software it is very difficult which memory has the new forward control information that is used for given channel/VCG.
8.5.2.2 the non-LCAS view of channel status memory clauses and subclauses
| Parameter | Size | Value after initialization or |
| RX_CH_NL_VCAT_ACC_SQ | ||
| 8 | 0 | |
| |
1 | 1 |
| Do not use | 6 | 0 |
8.5.3 receiver port situation
Receiver port condition parameter utilizes 128 * 3 triggers to carry out.
| Parameter | Size | Value after initialization or receiver port reset |
| |
1 | 0 |
| |
1 | |
| RX_SK_LCAS_GID_MFI2_LSB | ||
| 1 | | |
| RX_SK_LCAS_GID_ERR_COPY | ||
| 1 | 0 |
8.5.4 receiver port state
Receiver port state parameter utilizes 128 * 1 triggers to carry out.
| Parameter | Size | Value after initialization or receiver port reset |
| |
1 | 0 |
8.5.5 source port state
The source port state parameter is combined in 128 * 65 twin port memories.Following table shows the entry structure in this memory:
| Parameter | Size | Value after the initialization |
| RX_SO_LCAS_MST | 64 | |
| |
1 | |
Note 1: for the operation purpose, these parameters do not need to have initial value.Do not exist source port to reset, but software can write initial value.
8.6 be used for the operation of non-VCAT channel
For non-VCAT channel, ALIG_RD will not have the valid data that are used for LVC, and still, the authorization configuration of receiver port LPID and channel will be sent to LVC with channel type and calendar information.
Because will can not have valid data, any situation or state that LVC can not carry out any channel or relevant receiver port and (virtual) source port upgrade operation.
8.7 LCAS operation
If the aln_rd_lv_ch_sk_lcas_en signal is inserted in the given clock circulation, carry out the LCAS operation.In this part, the inventor supposes that this is a kind of situation, and it is not shown clearly is a part that is used for the condition of renewal situation and state information.
The LCAS operations specifications is divided into following two zones:
The renewal of situation and state information
Control information and load data are to the transmission of DSQ
Also describe in detail and reset/processing of fault.
8.7.1 situation and state upgrade
8.7.1.1 high-order
Table 8-1 has specified LCAS situation and the state carried out by LVC for the high-order channel and has upgraded operation (inventor supposes that ALIG_RD_STS_VT is wrong).
| The time slot type | HO LCAS state and status update operation |
| SOF-LCP load～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_VLD ﹠﹠ ALIG_RD_LVC_SOF ﹠﹠ (ALIG_RD_LVC_MFI[3:0]==8) | Read CH_LCAS_CRC_VLD，CH_LCAS_CRC_ERR_COPY， CH_LCAS_NEXT_SQ and CH_LCAS_NEXT_CTRL If (CH_LCAS_CRC_VLD && ～CH_LCAS_CRC_ERR_COPY){ CH_LCAS_CUR_SQ＝CH_LCAS_NEXT_SQ CH_LCAS_CUR_CTRL＝CH_LCAS_NEXT_CTR Write CH_LCAS_CUR_SQ and CH_LCAS_CUR_CTRL } |
| Non-SOF-LCP load～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_VLD ﹠﹠～ALIG_RD_LVC_SOF ﹠﹠～ALIG_RD_LVC_H4_K4 | Read CH_LCAS_CUR_CTRL，CH_LCAS_CUR_SQ |
| MST[7:4] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[3:0]＝＝8) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[7:4]) CH_LCAS_MST[7:4]＝ALIG_RD_LVC_H4_K4[7:4]CH_LCAS_CRC_ALIGNED＝1 CH_LCAS_CRC_VLD＝1 Write CH_LCAS_CRC，CH_LCAS_CRC_ALIGNED， CH_LCAS_CRC_VLD，CH_LCAS_MST[7:4] |
| MST[3:0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[3:0]＝＝9) | Read CH_LCAS_CRC，CH_LCAS_MST[7:4]and SO_LCAS_MST CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[7:4]) CH_LCAS_MST[3:0]＝ALIG_RD_LVC_H4_K4[7:4] CH_LCAS_MST_CHG＝0 If (ALIG_RD_LVC_MFI[8:7]＝＝0){ MST_CHUNK_LSB_POS＝{ALIG_RD_LVC_MFI[6:0]，3’b0} MST_CHUNK_MSB_POS＝MST_CHUNK_LSB_POS+7 If (SO_LCAS_MST[MST_CHUNK_MSB_POS:MST_CHUNK_LSB_POS] !＝CH_LCASMST){ CH_LCAS_MST_CHG＝1 } } Write CH_LCAS_CRC，CH_LCAS_MST[3:0]and CH_LCAS_MST_CHG |
| RS_ACK ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[3:0]＝＝10) | Read CH_LCAS_CRC and SO_LCAS_RS_ACK CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC， ALIG_RD_LVC_H4[7:4]) CH_LCAS_RS_ACK＝ALIG_RD_LVC_H4_K4[4] CH_LCAS_RS_ACK_CHG＝(CH_LCAS_RS_ACK!＝SO_LCAS_RS_ACK) Write CH_LCAS_CRC，CH_LCAS_RS_ACK and CH_LCAS_RS_ACK_CHG |
| Oppositely～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST﹠﹠ ALIG_RD_LVC_DATA_VLD ﹠﹠ ALIG_RD_LVC_H4_K4 ﹠﹠, (ALIG_RD_LVC_MFI[3:0] 〉=11) ﹠﹠, (ALIG_RD_LVC_MFI[3:0]＜=13) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC，ALIG_RD_LVC_H4_K4[7:4]) Write CH_LCAS_CRC |
| SQ[7:4] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[3:0]＝＝14) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[7:4]) CH_LCAS_NEXT_SQ[7:4]＝ALIG_RD_LVC_H4_K4[7:4] Write CH_LCAS_CRC，and CH_LCAS_NEXT_SQ[7:4] |
| SQ[3:0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[3:0]＝＝15) | Read CH_LCAS_CRC，CH_LCAS_NEXT_SSQ，CH_CUR_SQ CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[7:4]) CH_LCAS_NEXT_SQ[3:0]＝ALIG_RD_LVC_H4_K4[7:4]CH_LCAS_SQ_CHG＝(CH_LCAS_NEXT_SQ!＝ CH_LCAS_CUR_SQ) Write CH_LCAS_CRC，CH_LCAS_NEXT_SQ[3:0]and CH_LCAS_CTRL_CHGG |
| MFI2 ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_O_MFI1 >＝0)&& (ALIG_RD_LVC_MFI[3:0]<＝1) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC，ALIG_RD_LVC_H4_K4[7:4]) Write CH_LCAS_CRC |
| CTRL ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[3:0]＝＝2) | Read CH_LCAS_CRC，CH_LCAS_CUR_CTRL CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[7:4]) CH_LCAS_NEXT_CTRL＝ALIG_RD_LVC_H4_K4[7:4]CH_LCAS_CTRL_CH＝(CH_LCAS_NEXT_CTRL!＝ CH_LCAS_CUR_CTRL) WriteCH_LCAS_CRC，CH_LCAS_NEXT_CTRLand CH_LCAS_CTRL_CHG |
| GID ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4&& (ALIG_RD_LVC_MFI[3:0J＝＝3) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC8(CHH_LCAS_CRC，ALIG_RD_LVC_H4_K4[7:4]) CH_LCAS_GID＝ALIG_RD_LVC_H4_K4[4] write CH_LCAS_CRC and CH_LCAS_GID |
| Oppositely～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_VLD ﹠﹠ ALIG_RD_LVC_H4_K4 ﹠﹠ (MFI[3:0] 〉=4) ﹠﹠ (MFI[3:0]＜=5) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC，ALIG_RD_LVC_H4_K4[7:4]) Write CH_LCAS_CRC |
| CRC[7:4] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL&& ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (MFI[3:0]＝＝6) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[7:4]) CH_LCAS_ZERO_CRC＝(ALIG_RD_LVC_H4_K4[7:4]＝＝0) Write CH_LCAS_CRC and CH_LCAS_ZERO_CRC |
| Rea dCH_LCAS_CRC_ALIGNED，CH_LCAS_CRC_VLD，CH_LCAS_CRC，CH_LCAS_CRC_ERR_COPY，CH_LCAS_NEXT_SQ，CH_LCAS_SO_CHG，CH_LAS_NEXT_CTRL，CH_LCAS_CTRL_CHG，CH_LLCAS_MST，CH_LCAS_MST_CHG，CH_LCAS_RS_ACK，CH_LCAS_RS_ACK_CHG，CH_LCAS_GID，CH_LCAS_ZERO_CRC，CH_LCAS_NL_SRC_COPY，SKK_LCAS_GID_VLD，SK_LCAS_GID，SK_LCAS_GID_MFI2_LSB，SK_LCAS_GID_ERR，LCAS_GID_CAP_VLD，LCAS_GID_CAP_PORT，LCAS_GID_CAP_STARTEO，LCAS_GID_CAPSTART_MFI2_LSB，LCAS_GID_CAP_Stop_MFI2_LSB，CH_LCAS_GID_CAP_IDXCH_LCAS_CRC＝NEXT_CRC8(CH_LCAS_CRC，ALIG_RD_LVC_H4_K4[7:4])If(～CH_LCAS_CRC_ALIGNED){ CH_LCAS_CRC_ALIGNED＝1}Else If(～CH_LCAS_CRC_VLD){ CH_LCAS_CRC_VLD＝1}// CRC Count captureIf(LCAS_CRC_CNT_CAP_VLD＝If(CH_LCAS_CRC_VLD){ CH_LCAS_CRC_ERR＝(CH_LCAS_CRC!＝0) If(CH_LCAS_CRC_ERR＝＝0){ If(CH_LCAS_SO_CHG){ Generate CH_LCAS_SQ_CHG interrupt for thischannel } If(CH_LCAS_CTRL_CHG){ Generate CH_LCAS_SQ_CHG interrupt for thischannel } If (CH_LCAS_LCAS_REV_EXT_EN){ MST_CHUNK_LSB_POS＝{ALIG_RD_LVC_MFI[2:0]，3′b0} MST_CHUNK_MSB_POS＝MST_CHUNK_LSB_POS+7 80SO_LCAS_MST[MST_CHUNK_MSB_POS:MST_CHUNK_LSB_POS]＝CH_LCAS_MST If(CH_LCAS_MST_CHG){ |
| Channel-failures ALIG_RD_LVC_CH_FAIL only | CH_LCAS_CRC_ALIGNED＝0 CH_LCAS_CRC_VLD＝0 CH_LCAS_CRC＝0 Write CH_LCAS_CRC_ALIGNED，CH_LCAS_CRC_VLD andCH_LCAS_CRC |
| The channel ALIG_RD_LVC_CH_RST that resets | CH_LCAS_CRC_ALIGN ED＝0 CH_LCAS_CRC_VLD＝0 CH_LCAS_CRC＝0 CH_LCAS_CRC_ERR＝0 CH_LCAS_CRC_ERR_COPY＝0 CH_LCAS_NL_SRC＝0 CH_LCAS_NL_SRC_COPY＝0 CH_LCAS_CUR_CTRL＝IDLE Write CH_LCAS_CRC_ALIGNED，CH_LCAS_CRC_VLD， CH_LCAS_CRC，CH_LCAS_CRC_ERR，CH_LCAS_NL_SRC，CH_LCAS_NL_SRC_COPY and CH_LCAS_CUR_CTRL |
| The port reset ALIG_RD_LVC_SK_RST ﹠﹠～ALIG_RD_LVC_CH_RST of receiving station | SK_LCAS_GID_VLD＝0 SK_LCAS_GID_ERR＝0 Write SK_LCAS_GID_VLD and SK_LCAS_GID_ERR |
LCAS situation/state on the table 8-1:HO channel upgrades operation
Based on the renewal operating instruction in table 8-1, table 8-2 has summed up the storage access requirement, is used for the state and the situation memory of the LCAS operation of high-order channel with renewal.Should be noted that for any kind from ALIG_RD request, hardware does not need to be read and write access status memory.Therefore, status register port can be exclusively used in the CPU access.If software is attempted reading state memory entries when hardware is attempted the update mode memory entries, the value that is about to write by hardware should be transmitted to software.
Table 8-2: be used for carrying out on the HO channel storage access scheme that LCAS situation/state upgrades operation
Note, on expressed for given request from ALIG_RD, write access takes place for status register.In order to be designed to work with the hardware of the single port that utilizes the twin port status register, the reading or writing visit and need occur in the identical pipe stage of given state memory.Show the embodiment of this situation.
Table: LVC pipeline sample
Notice that the channel conditions memory is being stored the information that whether changes about information forward or backwards.Therefore, renewal is finished with regard to waiting until that these memories read.Simultaneously, the decision of write state memory has to wait for, up to having read the situation memory and having carried out CRC calculating.Because need and to arrange the write access of status register, so can find that the order of storage access in the pipeline must be as implied above.
8.7.1.1.1 CRC check
When VCG obtained to adjust after initialization or after recovering from the VC fault, ALIG_RD can send data to always begin at the frame boundaries place VLC.Yet this frame can not unwrapped the beginning frame of (that is, HO_MFI is 8) in response to the LCAS control data, and perhaps channel can be broken away from after the H4 byte is received in this frame and reset.If this is the case, before carrying out CRC check, VLC need wait for the beginning of LCAS control data bag.For each channel, CH_LCAS_CRC_ALIGNED situation position is used for this purpose.
Reset/fault if channel has been broken away from, make that first H4 byte of its discovery is not to be used for HO_MFI=8, before the CH_LCAS_CRC_ALIGNED position is set, channel must be waited for always, be 7 up to the H4 byte that is used for HO_MFI1 so.But still can not exist effective CRC this moment.So can not use any LCAS control data bag field that extracts.In case handled complete LCAS control data bag, the CH_LCAS_CRC_VLD state quantities will be set.
When LVC is initialised, remove the CH_LCAS_CRC_ALIGNED and the CH_LCAS_CRC_VLD situation position of all channels.During normal running, when reset VCG or fault were expressed thereon, LVC removed the CH_LCAS_CRC_ALIGNED and the CHCRC_VLD position of channel.8.7.2 chapters and sections provide about resetting and the more information of troubleshooting.
No matter when the H4 byte is received is used for given channel, and LVC reads the CH_LCAS_CRC state quantities that is used for this channel, and calculates the next one value of LCAS_CRC variable based on the high nibble of the H4 byte that receives.Be provided with HO_MFI1 value 15 and CH_LCAS_CRC_ALIGNED if ALIG_RD shows, LVC checks whether the LCAS_CRC value of upgrading equals zero so.If not, this just represents to have taken place the CRC mistake.When another situation, LVC CH_LCAS_CRC state quantities is set to zero, to prepare next LCAS control data bag.
Last in CRC check, whether before upgrading the CH_LCAS_CRC_ERR mode bit, LVC reads the currency of CH_LCAS_CRC_ERR_COPY situation position, to change in the value before checking.If change, the CH_LCAS_CRC_ERR_CHG interrupt requests is sent to the CFR of this channel.
Notice that the reason that keeps the CH_LCAS_CRC_ERR mode bit to duplicate is to avoid having to the reading state memory to judge whether producing interrupt requests in the channel conditions memory.
LCAS_CRC_ERR state variable and monitoring CH_LCAS_CRC_ERR_COPY state quantities thereof are initialized as zero.Reset when channel enters/during failure condition, these variablees also reset.
8.7.1.1.2 the CRC fault verification (dCRC) that continues
Utilize moving window the CRC fault that continues to be counted in the VCG level.For all VCG, setting/removing window and setting/removing threshold value length be that the overall situation is fixing.Length of window is specified according to multi-frame quantity.For each VCG, the aggregate of the LCAS CRC mistake that the Orion counting detects on its any branch road.
When initialization LVC, remove SK_LCAS_DCRC mode bit, SK_LCAS_CRC_CNT and the SK_LCAS_DCRC_WDW_CNT field of all of the port.During normal running, when resetting the receiver port, LVC will remove these fields of this port.
No matter when on given channel current control data bag is carried out CRC check, increase one by one comprises the SK_LCAS_DCRC_WDW_CNT of LCAS receiver VCG.If detect the CRC mistake, increase the CRC counting of LCAS receiver VCG so seriatim.
If when SK_LCAS_DRC_WDW_CNT reaches the RX_LCAS_DCRC_N1 value, the SK_LCAS_DCRC mode bit is not set, the CRC counting is checked the LCAS_DCRC_K1 value so.If the CRC counting equals or is higher, so set LCAS_DRCR mode bit.
If when SK_LCAS_DRC_WDW_CNT reaches the RX_LCAS_DCRC_N2 value, be provided with the SK_LCAS_DCRC mode bit, SK_LCAS_CRC_CNT is checked the LCAS_DCRC_K2 value so.If SK_LCAS_CRC_CNT equals or is higher, set LCAS_DRCR mode bit so.
When set or the end of removing window, SK_LCAS_DRC_WDW_CNT and SK_LCAS_CRC_CNT are reset to zero.Equally, if the value of SK_LCAS_DCRC changes, set SK_LCAS_CRC_CHANGED interrupt status position so.
8.7.1.1.3 detect the CRC mistake on the VCG branch road
LVC can show setting/removing dCRC fault on specific VCG.Unless but software is observed the LCAS CRC state (being difficult to accomplish) of all path channels on each multi-frame, otherwise the branch road that can not judge in such condition whether has all most of mistakes or mistake is dispensed on all branch roads without exception.Can select a receiver VCG in order at length to count the CRC mistake on its all branch roads at every turn.
Software selects VCG to calculate branch road CRC mistake or by its port id being write overall LCAS_DCRC_CAP_PORT register.The window (in multi-frame) that software also utilizes overall LCAS_DCRCWS register to specify to collect the CRC error count.In order to begin this counting, software is removed the LCAS_DCRC_CAP_VLD position.
When count window exhausted, Orion was provided with LCAS_DCRC_CAP_DONE interrupt status position.Utilizing indirect memory, from the LCAS_CRC_CNT register, is feasible for the CRC counting that rises to 64 path channels, and this indirect register utilizes sequence number to carry out addressing.
Notice that hardware do not check whether the port of selection has been broken away from and reset, with and whether be the LCAS configured port.If software error ground has carried out this operation, CRC counting acquisition procedure will can not start.Software can write LCAS_DCRC_CAP_PORT to recover with perfecting value.
If (that is, LCAS_DCRC_CAP_VLD=0), hardware can not be written to LCAS_DCRC_CAP_PORT or LCAS_DCRC_CAP_WS register to exist CRC to catch activation.
8.7.1.1.4 the forward control information is upgraded
Hardware writes sequence and the control field that receives in the current LCAS control data bag respectively in CH_LCAS_NEXT_SQ and the CH_LCAS_NEXT_CTRL state variable.If such control data bag has effective CRC and it does not have the CRC mistake, frame at the next LCAS control data bag of beginning begins so, and hardware duplicates the value of CH_LCAS_NEXT_SQ and CH_LCAS_NEXT_CTRL parameter to CH_LCAS_CUR_SQ and CH_LCAS_CUR_CTRL parameter respectively.If but there is the CRC mistake, incite somebody to action not update mode parameter.
In order to control the transmission of load byte to DSQ, LVC utilizes CH_LCAS_CUR_SQ and CH_LCAS_CUR_CTRL state parameter.Therefore in the SOF byte that is the load byte, LVC does not read channel status memory, and on the contrary, for this purpose, it utilizes sequence and Control Parameter to use data from status register.Guarantee like this in the SOF circulation, only to require primary access for channel status memory.
When LVC received SQ and CTRL field, it read CH_LCAS_CUR_SQ and CH_LCAS_CUR_CTRL state parameter, and they and the value that receives are compared.If there are differences, LVC set CH_LCAS_SQ_CH and/or CH_LCAS_CTRL_CH position.
At LCAS control data bag end, if there is effective CRC, and CRC check is OK, and CH_LCAS_SQ_CHG and/or CH_LCAS_CTRL_CHG position be set, and LVC will produce interrupt status to CFR and request is set changes to carry out sequence and/or control word so.
The situation that channel is not in the situation that resets/fail that is applied to more than is discussed.If channel is in and resets/the failure situation, hardware will show as the situation described in the 8.7.2 chapters and sections.
8.7.1.1.5 oppositely control information is upgraded
Oppositely the execution of control information only takes place under the situation that the RX_CH_LCAS_REV_EXT_EN of channel parameter is set.In the following description, inventor's supposition is in this situation.
Do not attempt to check the MST that on the channel of the reverse information of carrying that is used for identical HO_MFI2 identical sources port, receives and RS_Ack value whether identically.Notice that any mistake of conflicting with these fields may be detected by CRC check.
The discussion of these chapters and sections is applicable to that channel is not in and resets/situation of malfunction.If channel is in and resets/fault condition under, hardware can not attempt to upgrade reverse control situation/state, and it can not produce be used for the interruption that changes on the correlated source port of channel, if vicissitudinous words.
Software can write the source port status register with initialization MST and RS_ACK value.Usually, the MST position can be initialized to complete 1 (MST=Fail).The initial value of RS_ACK is unimportant, unless software will be appreciated that what it is.
8.7.1.1.5.1 MST
The MST field that receives in the LCAS of given channel control data bag is stored in the channel conditions memory entries of this channel.When according to the MFI2 value, when receiving the low nibble of MST field on given channel, LVC also compares it with the corresponding M ST position in source port state relevant with this channel.If comparison shows that difference, set is used for the CH_LCAS_MST_CHG mode bit of this channel.
Because the channel maximum quantity that the inventor provides is defined as 64 in Orion, so some LCAS control data bags do not carry any useful MST information.This is based on the MFI2 decision.If there is MST, will be used for comparison from the MST of source port status register entry so, and upgrade after determining following from source port status register clauses and subclauses:
If(ALIG_RD_LVC_MFI[8:7]＝＝0){
MST_Chunk_LSB_Pos＝{ALIG_RD_LVC_MFI[6:4]，3b’0}
MST_Chunk_MSB_Pos＝MST_Chunk_LSB_Position+ 7
MST_Chunk＝SO_LCAS_MST[MST_Chunk_MSB_Pos:MST_Chunk_LSB_Pos]
}
// Else do not perform MST comparison and update
At the end of LCAS controlling packet, if there is effective CRC, and CRC check is OK, and if LCAS oppositely control be extracted on this channel and be enabled, that LVC upgrades the corresponding M ST position in the source port state relevant with the MST field that receives on this channel.If set CH_LCAS_MST_CHG position, LVC also produces the SO_LCAS_MST_CHG interruption that is used for the source port relevant with this channel so.
8.7.1.1.5.2 RS_ACK
The RS_ACK position that receives in the LCAS control data bag on given channel is stored in the channel conditions memory entries of this channel.At this moment, RS_ACK position compares in the source port state that LVC is also relevant with this channel with it.If comparison shows that difference, set is used for the CH_LCA_RS_ACK_CHG situation position of this channel.
End at LCAS control data bag, if there is effective CRC, and CRC check is OK, and if LCAS oppositely control be extracted on this channel and be enabled, LVC upgrades the RS_ACK position in the source port state relevant with the RS_ACK position that receives on this channel so.If set CH_LCAS_RS_ACK_CHG position, LVC also produces the SO_LCAS_RS_ACK_CHG interruption of the source port relevant with this channel so.
8.7.1.1.6 GID checks
LVC checks whether each mandate path channels of receiver port has received the identical GID position (that is last of each branch road reception) in the identical LCAS control data bag.If the GID position does not match on the different channels, LVC is provided with the SK_LCAS_GID_ERR mode bit so, and if mode bit have the value of change, produce receiver port GID interrupt requests.Except such mode bit, LVC also keeps following receiver port level situation position:
·SK_LCAS_GID_VLD
·SK_LCAS_GID
·SK_LCAS_GID_MFI2_LSB
·SK_LCAS_GID_ER_COPY
Although the SK_LCAS_GID_ERR_COPY mode bit is used to avoid reading receiver port state to judge whether producing interruption in design, whether must have such mode bit.Because receiver port mode bit is in the trigger,, do not clash and worry reading with software so they can read when reading receptor port situation/mode bit.The use of the not shown SK_LCAS_GID_ERR_COPY of false code.
When the GID position when given channel receives, it is stored in the channel status memory, because LVC wraps when being verified at the LCAS control data up to CRC, could work to it.
At the end of LCAS controlling packet, if there is effective CRC, and CRC check is OK, and LVC checks at first whether channel is authorized to (and checking that also it does not receive the IDLE as control word).If LVC then checks receiver level GID situation.
If there is not set SK_LCAS_CID_VLD, just mean that this is that GID relatively carries out for the first time in this receiver port.Under these circumstances, LVC is provided with SK_LCAS_GID_VLD, CH_LCAS_GID is duplicated to SK_LCAS_GID and with SK_LCAS_GID_MFI2_LSB be provided with to HO_MFI2[0].Yet, still not execution error verification.
If be provided with SK_LCAS_GID_VLD, LVC is with SK_LCAS_GID_MFI2_LSB and HO_MFI2[0] compare.If their differences just mean the new LCAS control data circulation that has proceeded to this receiver port, and current channel are first channel that is in LCAS control data bag end.In this case, LVC is provided with SK_LCAS_GID_VLD to CH_LCAS_GID, and SK_LCAS_GID_MFI2_LSB is provided with to HO_MFI2[0].Once more, still not execution error verification.
If be provided with SK_LCAS_GID_VLD, and SK_LCAS_GID_MFI2_LSB equals HO_MFI2[0] LSB, just mean that current channel is not first channel (it is set to the GID that receives on first channel) in the receiver port that compares of GID and receiver port GID with its reception.Under these circumstances, LVC compares CH_LCAS_GID and SK_LCAS_GID.If their differences are provided with SK_LCAS_GID_ERR and SK_LCAS_GID_ERR_COPY so.But before doing like this, LVC compares new value and the SK_LCAS_GID_ERR_COPY of SK_LCAS_GID_ERR.If their differences, LVC produces the SK_LCAS_GID_ERR_CHG interruption that is used for the correlation receiver port so.
8.7.1.1.7 detect the GID value on the VCG branch road
LVC reports when the GID mistake detects on specific VCG.In this level, can not determine to produce the stringent condition of GID mistake.For example, if a branch road has the GID value that is different from other, just can not this branch road of definition.Can select a receiver VCG at length to detect the GID value of this branch road this moment.Hardware catch selected VCG all branch roads the GID position and make it effective for software.
Software is selected VCG, on this VCG, catches branch road its port id is written to overall LCAS_GID_CAP_PORT register.GID catches by overall LCAS_GID_CAP_VLD position is set and begins.
In next control data bag cycle period, hardware will write overall LCAS_GID_CAP status register to the GID value of the reception of each branch road based on the sequence number of its reception.Because the full-size of receiver VCG is 64 among the Orion, use two 32 bit registers for this purpose.After this, hardware will be removed the LCAS_GID_CAP_VLD position and LCAS_GID_CAP_DONE interrupt status position will be set.
Notice that hardware do not check whether the port of selection has been broken away from and reset, and if break away from and reset, whether it is the LCAS configured port.If carried out these operations, the GID acquisition procedure will can not start hardware error.Software can write LCAS_GID_CAP_PORT to recover with perfecting value.
If (that is, LCAS_GID_CAP_VLS=0), hardware should not be written to the LCAS_GID_CAP_PORT register to exist GID to detect activation.
8.7.1.2 low order
Following table has shown that LCAS situation and the state carried out by the LVC that is used for the low order channel upgrade operation (supposition ALIG_RD_STS_VT is correct).
| The time slot type | LO LCAS situation and state upgrade operation |
| SOMF load～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_ VLD ﹠﹠ ALIG_RD_LVC_SOF ﹠﹠ (ALIG_RD_LVC_MFI[4:0]==0) | Read CH_LCAS_CRC_VLD，CH_LCAS_CRC_ERR_COPY， CH_LCAS_NEXT_SQ and CH_LCAS_NEXT_CTRL If(CH_LCAS_CRC_VLD &&～CH_LCAS_CRC_ERR_COPY){ CH_LCAS_CUR_SQ＝CH_LCAS_NEXT_SQ CH_LCAS_CUR_CTRL＝CH_LCAS_NEXT_CTRL Write CH_LCAS_CUR_SQ and CH_LCAS_CUR_CTRL } |
| Non-SOMF load～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_ VLD ﹠﹠～ALIG_RD_LVC_SOF ﹠﹠～ALIG_RD_LVC_H4_K4 MFI2[4] | Read CH_LCAS_CUR_CTRL，CH_LCAS_CUR_SQ |
| ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]＝＝0) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) CH_LCAS_CRC_ALIGNED＝1 CH_LCAS_CRC_VLD＝1 Write CH_LCAS_CRC，CH_LCAS_CRC_ALIGNED，CH_LCAS_CRC_VLD |
| MFI2[3:0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]>＝1)&& (ALIG_RD_LVC_MFI[ 4:0]<＝4) | Read CH_LCAS_CRC CH_LCA S_CRC＝NEXT_CRC3(CH_LCAS_CRC，ALIG_RD_LVC_H4_K4[6]) Write CH_LCAS_CRC |
| SQ[5:1] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]>＝5)&& (ALIG_RD_LVC_MFI[ 4:0]<＝9) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) BIT_POS＝10-ALIG_RD_LVC_MFI[4:0] CH_LCAS_NEXT_SQ[BIT_POS]＝ALIG_RD_LVC_H4_K4[6] Write CH_LCAS_CRC and CH_LCAS_NEXT_SQ[BITT_POS] |
| SQ[0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]＝＝10) | Read CH_LCAS_CRC，CH_LCAS_CUR_SQ CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) CH_LCAS_NEXT_SQ[0]＝ALIG_RD_LVC_H4_K4[6] CH_LCAS_SQ_CHG＝(CH_LCAS_NEXT_SQ!＝CH_LCAS_CUR_SQ) Write CH_LCAS_CRC，CH_LCAS_NEXT_SQ[SQ_BIT_POS]and CH_LCAS_SQ_CHG |
| CTRL[3:1] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]>＝11)&& (ALIG_RD_LVC_MFI[ 4:0]<＝13) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) BIT_POS＝14-ALIG_RD_LVC_MFI[4:0] CH_LCAS_NEXT_CTRL[BIT_POS]＝ALIG_RD_LVC_H4_K4[6] Write CH_LCAS_CRC and CH_LCAS_NEXT_CTRL[BIT_POS] |
| CTRL[0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]＝＝14) | Read CH_LCAS_CRC，CH_LCAS_CUR_CTRL CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) CH_LCAS_NEXT_CTRL[0]＝ALIG_RD_LVC_H4_K4[6] CH_LCAS_CTRL_CHG＝(CH_LCAS_NEXT_CTRL!＝ CH_LCAS_CUR_CTRL) Write CH_LCAS_CRC，CH_LCAS_NEXT_CTRL[SQ_BIT_POS]andCH_LCAS_CTRL_CHG |
| GID ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]＝＝15) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC，ALIG_RD_LVC_H4_K4[6]) CH_LCAS_GID＝ALIG_RD_LVC_H4_K4[6] Write CH_LCAS_CRC and CH_LCAS_GID |
| Oppositely～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_ VLD ﹠﹠ ALIG_RD_LVC_H4_K4 ﹠﹠ (ALIG_RD_LVC_MFI[4:0] 〉=16) ﹠﹠ (ALIG_RD_LVC_MFI[4:0]＜=19) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC，ALIG_RD_LVC_H4_K4[6]) Write CH_LCAS_CRC |
| RS_ACK ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]＝＝20) | Read CH_LCAS_CRC and SO_LCAS_RS_ACK CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) CH_LCAS_RS_ACK＝ALIG_RD_LVC_H4_K4[6] CH_LCAS_RS_ACK_CHG＝(CH_LCAS_RS_ACK!＝SO_LCAS_RS_ACK) Write CH_LCAS_CRC，CH_LCAS_RS_ACK and CH_LCAS_RS_ACK_CHG |
| MST[7:1] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]>＝21)&& (ALIG_RD_LVC_MFI[ 4:0]<＝27) | Read CH_LCAS_CRC CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) BIT_POS＝28-ALIG_RD_LVC_MFI[4:0] CH_LCAS_MST[BIT_POS]＝ALIG_RD_LVC_H4_K4[6] Write CH_LCAS_CRC and CH_LCAS_MST[BIT_POS] |
| MST[0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[ 4:0]＝＝28) | Read CH_LCAS_CRC and SO_LCAS_MST CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) CH_LCAS_MST[0]＝ALIG_RD_LVC_H4_K4[6] MST_CHUNK_LSB_POS＝{ALIG_RD_LVC_MFI[7:5]，3’b0} MST_CHUNK_MSB_POS＝MST_CHUNK_LSB_POS+7 CH_LCAS_MST_CHG＝(CH_LCAS_MST!＝ SO_LCAS_MST[MST_CHUNK_MSB_POS:MST_CHUNK_LSB_POS]) Write CH_LCAS_CRC，CH_LCAS_MST[0] and CH_LCAS_MST_CHG |
| CRC[2:1] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_ VLD && ALIG_RD_LVC_H4_K4 && (MFI[4:0]>＝29) && (MFI[4:0]<＝30) | Read CH_LCAS_CRC and CH_LCAS_ZERO_CRC CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) CH_LCAS_ZERO_CRC＝(ALIG_RD_LVC_H4_K4[6]＝＝0)&&CH_LCAS_ZERO_CRC Write CH_LCAS_CRC and CH_LCAS_ZERO_CRC |
| CRC[0] | Read CH_LCAS_CRC_ALIGNED，CH_LCAS_CRC_VLD， CH_LCAS_CRC，CH_LCAS_CRC_ERR_COPY，CH_LCAS_NEXT_SQ， CH_LCAS_SQ_CHG，CH_LCAS_NEXT_CTRL，CH_LCAS_CTRL_CHG，CH_LCAS_MST，CH_LCAS_MST_CHG，CH_LCAS_RS_ACK， CH_LCAS_RS_ACK_CHG，CH_LCAS_GID，CH_LCAS_ZERO_CRC， CH_LCAS_NL_SRC_COPY，SK_LCAS_GID_VLD，SK_LCAS_GID， SK_LCAS_GID_MFI2_LSB CH_LCAS_CRC＝NEXT_CRC3(CH_LCAS_CRC， ALIG_RD_LVC_H4_K4[6]) If(～CH_LCAS_CRC_ALIGNED){ CH_LCAS_CRC_ALIGNED＝1 } Else If(～CH_LCAS_CRC_VLD){ CH_LCAS_CRC_VLD＝1 } If(CRC_VLD){ CH_LCAS_CRC_ERR＝(CH_LCAS_CRC!＝0) If(CH_LCAS_CRC_ERR＝＝0){ If(CH_LCAS_SQ_CHG){ Generate CH_LCAS_SQ_CHG interrupt for this channel } If(CH_LCAS_CTRL_CHG){ Generate CH_LCAS_SQ_CHG interrupt for this channel } If(CH_LCAS_LCAS_REV_EXT_EN){ MST_CHUNKK_LSB_POS＝{ALIG_RD_LVC_MFI[7:5]， 3’b0} MST_CHUNK_MSB_POS＝MST_CHUNK_LSB_POS+7 SO_LCAS_MST[MST_CHUMK_MSB_POS:MST_CHUNK_LSB_POS]＝ CH_LCAS_MST If(CH_LCAS_MST_CHG){ Generate SO_LCASMST_CHG interrupt for CH_LCAS_REV_EXT_SO_LPID source port } 100 SO_LCAS_RS_ACK＝CH_LCAS_RS_ACK If(CH_LCAS_RS_ACK_CHG){ Generate 5O_LCAS_RS_ACK_CHG interrupt for |
| Channel-failures ALIG_RD_LVC_CH_FAIL | CH_LCAS_CRC_ALIGNED＝0 CH_LCAS_CRC_VLD＝0 CH_LCAS_CRC＝0 Write CH_LCAS_CRC_ALIGNED，CH_LCAS_CRC_VLD andCH_LCAS_CRC |
| The channel ALIG_RD_LVC_CH_RST that resets | CH_LCAS_CRC_ALIGNED＝0 CH_LCAS_CRC_VLD＝0 CH_LCAS_CRC＝0 CH_LCAS_CRC_ERR＝0 CH_LCAS_CRC_ERR_COPY＝0 CH_LCAS_NL_SRC＝0 CH_LCAS_NL_SRC_COPY＝0 CH_LCAS_CUR_CTRL＝IDLE Write CH_LCAS_CRC_ALIGNED，CH_LCAS_CRC_VLD， CH_LCAS_CRC，CH_LCAS_CRC_ERR，CH_LCAS_NL_SRC，CH_LCAS_NL_SRC_COPY and CH_LCAS_CUR_CTRL |
| The receiver port ALIG_RD_LVC_SK_RS T～ALIG_RD_LVC_CH_RST that resets | SK_LCAS_GID_VLD＝0 SK_LCAS_GID_ERR＝0 Write SK_LCAS_GID_VLD and SK_LCAS_GID_ERR＝0 |
LCAS situation/state on the table 8-3:LO channel upgrades operation
The difference of high-order and low order interchannel is: receive LCAS control data bag with 1 bit at every turn, rather than receive with 4 bits at every turn.But because always have some fields greater than 4 bits, this makes LO and HO more not have extra complexity.
Notice that for when carrying out the renewal operation, this method is identical for the high-order channel with the low order channel.Should also be noted that for the LO channel and do not need different pipe design.
8.7.2 handle that the receiver port resets, channel-failures and channel reset
VCG be discussed reset, in the LVC behavior that channel-failures and channel reset, it is useful at first looking back the performance of ALIG_RD and software.
8.7.2.1 ALIG_RD and software action
Below from software summed up ALIG_RD fault/behavior resets:
Fault on the mandate path channels or the fault on the reset trigger VCG then trigger the fault on all path channels that no matter whether are authorized to.
Fault on unauthorized path channels or reset can not trigger the fault on the VCG.During the time slot of the channel of failing, ALIG_RD does not send valid data to LVC, but continues to show channel failure situation to LVC.Undelegated channel is not automatically broken away from fault.Software has to remove static malfunction position.
No matter whether be authorized to the channel failure (not resetting) on all path channels of the receiver port reset trigger that software is initiated.Notice that the ALIG_RD module sends receiver port reset condition to LVC individually.
For influencing resetting and fault condition (that is, software receiver port resets or the authorization channel fault/reset) of VCG, guaranteed conditions should be inserted into the ground long enough so that all of VCG path channels can be seen this situation.
If a path channels of authorizing enters fault, and channel is not protected, and software is removed the authority bit of this channel so, makes that in case readjusted from the data of remaining path channels, these data will be transferred into LVC and DSQ.Channel is reconfigured for unauthorized because will fail, and the malfunction of this channel can not make that DSQ deactivates buffer.
More than be necessary in LCAS, implementing DNU mechanism.If the channel of failure is the active branch of VCG, that is, the source sends NORM/EOS on this channel, and when obtaining from receiver propping up the path channels status of fail, the source will begin to send the DNU as control word so.Receiver will can not found the DNU control word significantly, but it must be operatively as having found control word.This just requires receiver to extract data from a residue path channels.
If software is recognized the mandate of failure and props up path channels and will be protected that software will can not be removed the authority bit of this channel so, and it will can not send to the source to status of fail.When the protection channel enters, VCG will readjust all branch roads, and ALIG_RD will begin to send the data to LVC from all path channels once more.Hypothesis after this method is: during supplying, software can determine that the difference time-delay variation that takes place because being converted to protected path remains in the system constraint.For precalculated protection path application, this hypothesis effectively.
Before it at first became the branch road of LCAS VCG, channel need reset.If such channel has been the authorization channel of LVCAS VCG, the LCAS agreement at first will be used to delete the channel from this VCG so.At this moment, before channel is set to reset mode, software will be removed the authority bit of channel.
Notice that if the authorization channel of LCAS VCG is changed to reset mode, it will make that VCG is changed to reset situation.Generally can not handle like this.Utilize LCAS deletion rules at first will remove authorization channel, and followed before channel is changed to reset mode, remove authority bit on this channel by software.But, when deletion non-when recovering the VCG staging error, the authorization channel that can reset, and do not carry out the following step.Yet before by software channel being produced from reset mode, software should be removed its authority bit.
Can not automatically from some network failures, recover.For example, difference time-delay can become excessive (usually, after the network configuration that can or cannot be triggered by protection mechanism) or protocol error (for example, the invalid sequence on authorization channel number and/or sequence number combination) can be by software detection.In these cases, VCG can also be resetted by software (perhaps all channels can be changed to reset mode), and does not follow the branch road removal program of plan.Notice that software can also send status of fail on all path channels of this VCG by configuration VCT_TX functional block.
Notice that in given clock circulation, the receiver port resets and only have meaning when channel is not in reset mode.This is because if channel is in to be resetted, and its RX_CH_SK_LPID parameter is not effective so.
8.7.2.2 LVC behavior
According to the authorization configuration position of channel, LVC in response to reset from the channel on this channel of ALIG_RD/failure identification shows as follows:
When the channel-failures sign on the LVC discovery channel (authorizing or unauthorized), its CH_LCAS_CRC_ALIGNED with channel, CH_LCAS_CRC_VLD and CH_LCAS_CRC state variable are set to zero respectively.
When resetting channel, LVC is reset to channel situation and state variable their initial value.
When channel maintained failure or reset situation or relevant receiver port and is in reset situation, LVC did not handle H4/K4 byte on this channel to upgrade the situation/state variable (channel or port level) relevant with this channel.Yet, LVC the clock circulation that is used for this channel with the configuration of calendar information and channel, reset and the failure situation sends DSQ to.
When the receiver port was in reset mode, RX_SK_GID_VLD situation position and RX_SK_GID_ERR mode bit resetted.
LVC is given in the indication that resets of any channel-failures of naming a person for a particular job that can be in frame/reset or receiver port.In such clock cycle period, replace situation/state of discussing in the 8.7.1 chapters and sections and upgrade operation, as mentioned above, hardware can be provided with situation and state variable.
8.7.3 will control with load data and send DSQ to
Following false code has illustrated formally how LVC will control and load data sends DSQ to:
If(～ALIG_RD_LVC_CH_RST){
If(ALIG_RD_LVC_CH_ACCEPTED){
If(～ALIG_RD_LVC_DATA_VLD|ALIG_RD_LVC_H4_K4){
LVC_DSQ_DNU＝1
}
Else{
If((ALIG_RD_LVC_SOF＝＝1)&&
((～ALIG_RD_LVC_STS_VT && (ALIG_RD_LVC_MFI[3:0]＝＝8))
||
(ALIG_RD_LVC_STS)&&(ALIG_RD_LVC_MFI[4:0]＝＝0))){
If ((CH_LCAS_NEXT_CTRL＝＝NORM)|(CH_LCAS_NEXT_CTRL＝＝
EOS)) {
LVC_DSQ_DNU＝0
}
Else{
LVC_DSQ_DNU＝1
}
LVC_DSQ_CH_SQ＝CH_LCAS_NEXT_SQ
}
Else {
If((CH_LCAS_CUR_CTRL＝＝NORM)|(CH_LCAS_CUR_CTRL＝＝
EOS)){
LVC_DSQ_DNU＝0
}
Else{
LVC_DSQ_NU＝1
}
LVC_DSQ_CH_SQ＝CH_CUR_LCAS_SQ
}
}
}
}
Else {
LVC_DSQ_DNU＝1 // Dummy since channel in reset
LVC_OSQ_CH_SQ＝0 // Dummy since channel in reset
}
LVC_DSQ_CH_DATA＝ALIG_RD_LVC_CH_DATA
LVC_DSQ_CH_FAIL＝ALIG_RD_LVC_CH_FAIL
LVC_DSQ_CH_RST＝ALIG_RD_LVC_CH_RST
LVC_DSQ_SK_RST＝ALIG_RD_LVC_SK_RST
LVC_DSQ_CH_ACCEPTED＝ALIG_RD_LVC_CH_ACCEPTED
LVC_DSQ_SK_LPID＝ALIG_RD_LVC_SK_LPID
LVC_DSQ_WID＝ALIG_RD_LVC_WID
LVC_DSQ_CH_STS_VT＝ALIG_RD_LVC_CH_STS_VT
LVC_DSQ_CH_STS_VC4＝ALIG_RD_LVC_CH_STS_VC4
LVC_DSQ_CH_STS_VTG_TYPE＝ALIG_RD_LVC_CH_STS_VTG_TYPE
As above described in chapters and sections 9, the read/write buffers upset in the DSQ module is based on the schedule circulation, with carry out mode in the SQ of VCT_TX functional block module similar.For example, when being zero STS number that produces by schedule, all their read/write buffers of STS-1 type VCG upset.This is possible, guarantees that VCG will not stop in the centre of schedule circulation because SLIG_RD reads manager.
But, between receiver side and transmitter side, there is an important difference about the buffer upset.At transmitter side, the buffer upset is only carried out when the current byte by the CXC traction is the load byte.The current byte that receiver side can not promote ALIG_RD is that the load byte is used as condition.This is because if channel is in the fault, and the time slot that is used for this channel so can not be classified as load or H4 byte time slot.
In order to handle this situation, LVC sends to DSQ with request in each clock circulation, no matter whether have the valid data from ALIG_RD in this circulation, and no matter whether data are load or H4 byte.Yet, except the load cycle that is used for authorization channel, the DNU position is set for all situations, and described authorization channel is not in and resets/status of fail, and their CUR_CH_SQ state quantities is not set to DNU (perhaps NEXT_CH_SQ, if SOF is correct).
When DSQ attempts to be provided with the DNU position of the current write buffer that the CH_CUR_SQ by unauthorized channel represents, can find the size of the value of CH_CUR_SQ greater than the buffer of the rearrangement of relevant VCG.Under these circumstances, DSQ has voicelessly ignored this request.If this occurs on the authorization channel, should be protocol error.8.7.4 chapters and sections referring to the processing of LCAS protocol error.
During authorization channel did not have valid data or data and is the time slot of H4/K4 byte, LVC was provided with the DNU position to DSQ.Unwrap the first load byte of the frame of beginning except LCAS control data therein, during the load time slot of authorization channel, LVC only is provided with the DNU position when channel makes its CH_CUR_CTRL state variable be set to DNU, and LVC is provided for the DNU position of this channel.
Notice that LVC sends to DSQ with authorization configuration and channel failure scenarios.If channel is not authorized to, DSQ ignores failure scenarios so.LVC can not upgrade data buffer yet during this time slot.Guarantee like this to have under the situation of the sequence number that conflicts with the sequence number of authorization channel, can not cause the failure of VCG data flow at the unauthorized channel.Although above situation is illegal in the LCAS agreement, does like this and will prevent unnecessary data destruction.Notice that for the unauthorized channel, DSQ will send to ANA to the receiver port of schedule and channel.
8.7.4 the LCAS protocol error is handled
Except CRC and GID, all LCAS protocol errors are also by software detection.Following is possible LCAS protocol error:
Invalid control word (for example, illegal or undesirable value)
Outside sequence number range (for example, the about VCG size of the value on authorization channel)
The sequence number on the mandate branch road and/or the invalid combination of control word (for example, gap in the sequence number or overlapping, sequence number and control word are incompatible, etc.).
8.8 non-LCAS operation
8.8.1 situation and state upgrade
In non-LCAS operation, that is, when LVC determined channel Mapping to non-LCAS receiver port, LVC did not extract and handles the control word, GID, MST and the RS_ACK field that receive in the H4/K4 byte, and does not carry out any crc check.
LVC only extracts and handles the SQ field that is used for non-LVC channel.LVC with the SQ field store extracted in the CH_PREV_SQ state variable.Before when receiving new SQ value it being upgraded, LVC reads preceding value in this state quantities so that itself and the value that receives are compared.
If two identical, LVC increases the CH_NL_VCAT_PREV_SQ_PRT_CNT state variable that is used for this channel so.If Counter Value reaches 3, the value that will receive is duplicated the state parameter to CH_VC_ACC_SQ so.Notice that counter does not begin turning from 3.Whether identical or different with the expectation sequence that is used for this channel according to the CH_VC_ACC_SQ state parameter, LVC is provided with or removes the CH_VC_SQM state variable.If the value of state variable changes, LVC interrupts the CH_VC_SQM_CHG that generation is used for this channel so.
If two identical, LVC CH_NL_VCAT_SQ_PRT_CNT is set to zero so.When channel is in when resetting/failing situation, this counter also resets.
Notice that at a time, for non-LCAS channel, storage access requires and be inequality, but uses identical pipeline for LCAS with non-LCAS channel.Non-LCAS situation is a subclass in the LCAS situation, because it has the storage access (for example, not needing to read channel status memory) of less requirement.
8.8.1.1 high-order
Below tabulate non-LCAS situation and the state carried out by the LVC that is used for the high-order channel and upgraded operation:
| The time slot type | Non-LCAS situation of HO and state upgrade operation |
| Load～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ALIG_RD_LVC_DATA_VLD ﹠﹠～ALIG_RD_LVC_H4_K4 | |
| MFI2, oppositely～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ALIG_RD_LVC_DATA_VLD ﹠﹠ALIG_RD_LVC_H4_K4 ﹠﹠ (ALIG_RD_LVC_MFI[3:0] 〉=0) ﹠﹠ (ALIG_RD_LVC_MFI[3:0]＜=13) | |
| SQ[7:4]～ALIG_RD_LVC_RST &&ALIG_RD_LVC_DATA_VLD &&ALIG_RD_LVC_H4_K4 &&(ALIG_RD_LVC_MFI[3:0]＝＝14) | Read CH_NL_VCAT_PREV_SQ andCH_LCAS_PREV_SQ_MATCHCH_NL_VCAT_PREV_SQ_MATCH＝ (CH_NL_VCAT_PREV_SQ[7:4]＝＝ALIG_RD_LVC_H4_K4[7:4])CH_NL_VCAT_PREV_SQ[7:4]＝ALIG_RD_LVC_H4_K4[7:4]Write CH_NL_VCAT_PREV_SQ[7:4]andCH_NL_VCAT_PREV_SQ_MATCH |
| SQ[3:0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RO_LVC_CH_FAIL && ～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DAT_A_VLD &&ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[3:0] ＝＝15) | Read CH_NL_VCAT_PREV_SQ， CH_NL_VCAT_PREV_SQ_MATCH， CH_NL_VCAT_PREV_SQ_RPT_CNT and CH_NL_VCAT_SQM_COPY If(CH_NL_VCAT_PREV_SQ_MATTCH){ CH_NL_VCAT_PREV_SO_MATCH＝ (CH_NL_VCAT_PREV_SQ[3:0]＝＝ ALIG_RD_LVC_H4_K4[7:4]) } If(CH_NL_VCAT_PREV_SQ_MATCH){ If(CH_NL_VCAT_PREV_SQ_RPT_CNT<3){ CH_NL_VCAT_PREV_SQ_RPT_CNT++ } } CH_NL_VCAT_PREV_SQ_MATCH＝0 CH_NL_VCAT_PREV_SQ[3:0]＝ ALIG_RD_LVC_H4_K4[7:4] If(CH_NL_VCAT_PREV_SQ_RPT_CNT＝＝3){ CH_NL_VCAT_SQM＝(ALIG_RO_LVC_EXP_SQ!＝ CH_NL_VCAT_PREV_SQ) If(CH_NL_VCAT_SQM!＝CH_NL_VCAT_SQM_COPY){ Generate CH_NL_VCAT_SQMi nterrupt for this channel } CH_NL_VCAT_SQM_COPY＝CH_NL_VCAT_SQM CH_NL_VCAT_ACC_SQ＝CH_NL_VCAT_PREV_SQ } Write CH_NL_VCAT_PREV_SQ[7:4]， CH_NL_VCAT_SQM_COPY，CH_NL_VCAT_SQM， CH_NL_VCAT_PREV_SQ_RPT_CNT Write CH_NL_VCAT_ACC_SQ if (CH_NL_VCAT_PREV_SQ_RPT_CNT＝＝3) |
| Channel-failures ALIG_RD_LVC_CH_FAIL | CH_NL_VCAT_PREV_SQ_RPT_CNT＝0 CH_NL_VCAT_PREV_SQ_MATCH＝0 Write CH_NL_VCAT_PREV_SQ_RPT_CNT andCH_NL_VCAT_PREV_SQ_MATCH |
| The channel ALIG_RD_LVC_CH_RST that resets | CH_NL_VCAT_PREV_SQ_RPT_CNT＝0 CH_NL_VCAT_PREV_SQ_MATCH＝0 CH_NL_VCAT_SQM＝1 CH_NL_VCAT_ACC_SQ＝0 Write CH_NL_VCAT_PREV_SQ_RPT_CNT， CH_NL_VCAT_PREV_SQ_MATCH，CH_NL_VCAT_SQM andCH_NL_VCAT_ACC_SQ |
| The port reset ALIG_RD_LVC_SK_RST ﹠﹠～ALIG_RD_LVC_CH_RST of receiving station | - |
Non-LCAS VCAT situation/state on the table 8-4:HO channel upgrades operation
According to the renewal operating instruction of listing among the table 8-4, at the high-order channel, following table 8-5 has summed up the memory access requirement for non-LCAS VCAT operation renewal situation and status register.
Table 8-5: be used for the storage access scheme that the situation/state on the non-LCAS VCAT HO channel upgrades
8.8.1.2 low order
Following table has illustrated that at the low order channel non-LCAS VCAT situation and the state carried out by LVC upgrade operation (inventor supposes that ALIG_RD_STS_VT is correct).
| The time slot type | LO non-LCAS VCAT situation and state upgrade operation |
| Load～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_VLD ﹠﹠～ALIG_RD_LVC_H4_K4 | - |
| MFI2 ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL &&～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[4:0] >＝0) && (ALIG_RD_LVC_MFI[4:0] <＝4) | - |
| SQ[5:1] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL &&～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[4:0] >＝5) && (ALIG_RD_LVC_MFI[4:0] <＝9) | Read CH_NL_VCAT_PREV_SQ and CH_NL_VCAT_PREV_SQ_MATCH BIT_POS＝10-ALIG_RD_LVC_MFI[4:0] If(!CH_NL_VCAT_PREV_SQ_MATCH){ CH_NL_VCAT_PREV_SQ_MATCH＝ (CH_NL_VCAT_PREV_SQ[BIT_POS]＝＝ ALIG_RD_LVC_H4_K4[6]) } CH_NL_VCAT_PREV_SQ[BIT_POS]＝ ALIG_RD_LVC_H4_K4[6] Write CH_NL_VCAT_PREV_SQ[BIT_POS]and CH_NL_VCAT_PREV_SQ_MATCH |
| SQ[0] ～ALIG_RD_LVC_CH_RST && ～ALIG_RD_LVC_CH_FAIL &&～ALIG_RD_LVC_SK_RST && ALIG_RD_LVC_DATA_VLD && ALIG_RD_LVC_H4_K4 && (ALIG_RD_LVC_MFI[4:0] ＝10) | Read CH_NL_VCAT_PREV_SQ， CH_NL_VCAT_PREV_SQ_MATCH， CH_NL_VCAT_PREV_SQ_RPT_CNT and CH_NL_VCAT_SQM_COPY If(CH_NL_VCAT_PREV_SQ_MATCH){ CH_NL_VCAT_PREV_SO_MATCH＝ (CH_NL_VCAT_PREV_SQ[0]＝＝ ALIG_RD_LVC_H4_K4[6]) } If(CH_NL_VCAT_PREV_SQ_MATCH){ If(CH_NL_VCAT_PREV_SQ_RPT_CNT<3){ CH_NL_VCAT_PREV_SQ_RPT_CNT++ } } CH_NL_VCAT_PREV_SQ_MATCH＝0 CH_NL_VCAT_PREV_SQ[0]＝ALIG_RD_LVC_H4_K4[6] If(CH_NL_VCAT_PREV_SQ_RPT_CNT＝＝3){ CH_NL_VCAT_SQM＝(ALIG_RD_LVC_EXP_SQ!＝ CH_NL_VCAT_PREV_SQ) If(CH_NL_VCAT_SQM!＝CH_NL_VCAT_SQM_COPY){ Generate CH_NL_VCAT_SQ Minterrupt for this channel } CH_NL_VCAT_SQM_COPY＝CH_NL_VCAT_SQM CH_NL_VCAT_ACC_SQ＝CH_NL_VCAT_PREV_SQ } Write CH_NL_VCAT_PREV_SQ[0]， CH_NL_VCAT_SQM_COPY，CH_NL_VCAT_SQM， CH_NL_VCAT_PREV_SQ_RPT_CNT Write CH_NL_VCAT_ACC_SQ if (CH_NL_VCAT_PREV_SQ_RPT_CNT＝＝3) |
| Oppositely～ALIG_RD_LVC_CH_RST ﹠﹠～ALIG_RD_LVC_CH_FAIL ﹠﹠～ALIG_RD_LVC_SK_RST ﹠﹠ ALIG_RD_LVC_DATA_VLD ﹠﹠ ALIG_RD_LVC_H4_K4 ﹠﹠ (ALIG_RD_LVC_MFI[4:0] 〉=16) ﹠﹠ (ALIG_RD_LVC_MFI[4:0]＜=19) | |
| Channel-failures ALIG_RD_LVC_CH_FAIL | CH_NL_VCAT_PREV_SQ_RPT_CNT_＝0 CH_NL_VCAT_PREV_SQ_MATCH＝0 Write CH_NL_VCAT_PREV_SQ_RPT_CNT and CH_NL_VCAT_PREV_SQ_MATCH |
| The channel ALIG_RD_LVC_CH_RST that resets | CH_NL_VCAT_PREV_SQ_RPT_CNT＝0 CH_NL_VCAT_PREV_SQ_MATCH＝0 CH_NL_VCAT_SQM＝1 CH_NL_VCAT_ACC_SQ＝0 Write CH_NL_VCAT_PREV_SQ_RPT_CNT， CH_NL_VCAT_PREV_SQ_MATCH，CH_NL_VCAT_SQM and CH_NL_VCAT_ACC_SQ |
| The port reset ALIG_RD_LVC_SK_RST ﹠﹠～ALIG_RD_LVC_CH_RST of receiving station |
Non-LCAS VCAT situation/state on the table 8-6:LO channel upgrades operation
8.8.2 will control with data and send DSQ to
For non-LCAS channel, LVC utilizes the sequence number of the expectation that configures when sending data byte to DSQ.The expectation sequence number of this channel is maintained in the CFG functional block and in each clock circulation relevant with this channel and sends to LVC.
Similar as much as possible between LCAS and non-LCAS VCG in order to keep data to transmit design, except following difference, LVC shows with will controlling with data and sends the identical mode in DSQ path to:
The expectation sequence number that will receive from ALIG_RD sends DSQ to as the sequence number of all load bytes
DNU only is unsupported time slot setting and never is provided with for the load time slot
All channels are handled (that is, ignoring the alig_rd_lvc_accepted signal) as authorization channel.
Following false code has illustrated formally how LVC will control and load data sends DSQ to:
If (～ALIG_RD_LVC_CH_RST){
If (～ALIG_RD_LVC_DATA_VLD||ALIG_RD_LVC_H4_K4){
LVC_DSQ_DNU＝1
}
Else{
LVC_DSQ_DNU＝0
}
LVC_DSQ_CH_SQ＝CH_NL_VCAT_EXP_SQ
LVC_DSQ_CH_ACCEPTED＝1
}
Else {
LVC_DSQ_CH_SQ＝0//Dummy since channel in reset
LVC_DSQ_DNU＝1//Dummy since channel in reset
LVC_DSQ_CH_ACCEPTED＝0//Dummy since channel in reset
}
LVC_DSQ_CH_FAIL＝ALIG_RD_LVC_CH_FAIL
LVC_DSQ_CH_RST＝ALIG_RD_LVC_CH_RST
LVC_DSQ_SK_RST＝ALIG_RD_LVC_SK_RST
LVC_DSQ_CH_DATA＝ALIG_RD_LVC_CH_DATA
LVC_DSQ_SK_LPID＝ALIG_RD_LVC_SK_LPID
LVC_DSQ_WID＝ALIG_RD_LVC_WID
LVC_DSQ_CH_STS_VT＝ALIG_RD_LVC_CH_STS_VT
LVC_DSQ_CH_STS_VC4＝ALIG_RD_LVC_CH_STS_VC4
LVC_DSQ_CH_STS_VTG_TYPE＝ALIG_RD_LVC_CH_STS_VTG_TYPE
8.9 be configured to interactional receiver with non-LCAS source LCAS
When the LCAS Channel Detection when CRC and control word are zero, it is provided with the RX_CH_LCAS_NL_SRC mode bit.This is likely that wherein non-LCAS source is relevant with the LCAS receiver because the network management configuration error takes place.In this case, software should be found such mode bit of being provided with on all channels of VCG.Notice that this can not change any other LCAS operation.
Software then can with channel and receiver end is salty be put they are reconfigured for non-LCASVCG.Generally, for each branch road of non-LCAS VCG, need be configured the expectation sequence number by NMS.Yet, in this case, can wish that software uses the sequence number of reception.For such processing, software at first can be distributed to the VCG with virtual expectation sequence number a path channels.The sequence number of the reality that software then will just utilize by the receive sequence number state parameter software is determined.During this section, the authority bit of channel can be closed (perhaps forbid be correlated with IFR port).At last, software will reconfigure the sequence number of the expectation of channel according to the state variable of the reception in the step before.
9 separate preface device (DSQ)
In this input data path, the DSQ Module Links is to LVC.Before the load data byte was transferred to IFR, the load data byte that is produced by the DSQ after the rearrangement was with multiplexing from the load data of non-VC channel.
The function of DSQ is resequenced according to the load byte of the VCG that the reception gap of its path channels order arrives at automatic network, to mate the VC sequence order of these channels.Under the situation of LCAS VCG, the VC sequence number that is used for resequencing extracts from the H4/K4 overhead byte.Under non-LCAS VCG situation, use the sequence number of the expectation that configures.Notice that the DSQ module itself does not know that VCG is an also right and wrong LCAS pattern of LCAS.
Utilize 1344 * 1 fixing schedules in common configuration and the schedule generator module, the data that will receive on the channel of VCG branch road (load and H4/K4) byte is pushed to DSQ.The data that identical schedule also is used for resequencing are from wherein extracting.
In each time slot of the given channel of distributing to the VCG branch road, no matter whether byte is pushed into, and all proposes to extract requirement always.When load was pushed into DSQ, DSQ can not be sent to the byte variable data management bag side.Otherwise also be correct.
Fig. 7 shows the interface and the memory that is included in wherein of DSQ module.Separating preface device 702 is connected with LVC704, ANA multiplexer 706 (it exports incoming frame (IFR) 708 to) and CFG710.DSQ comprises the Data Buffer Memory that reorders, status register and reorder buffer selection config memory reorder.
9.1 the interface of LVC
DSQ receives following schedule, configuration and control information and load byte (if any) from LVC in each clock circulation
9.1.1 schedule and configuration information
·RX_CH_STS_VT
·RX_CH_STS_VTG_TYPE
·RX_CH_VC4
·RX_WID
·RX_CH_SK_LPID
9.1.2 control information
Load data is effective
The channel fail condition
The channel reset condition
·DNU
·SQ
9.2 the interface of ANA
DSQ offers ANA with following configuration and control information in company with load byte (if any) together in each clock circulation:
·RX_CH_LPD
·RX_CH_DATA_VLD
9.3 the interface of CFR
DSQ is that following incident is provided with request to CFR generation interrupt status:
·RX_SK_RBID_CHG_DONE
There is not the state variable that remains among the DSQ.
9.4 the interface of CFG
DSQ is kept for the following configuration parameter of each VCG:
·RX_SK_RBID_0
·RX_SK_RBID_1
The read and write that the CFG module will be used for these parameters requires indication to give the DSQ module.
DSQ does not have any state parameter.
No matter when interrupt for it produces, DSQ will send CFG to from the receiver port signal that LVC receives.Notice that DSQ is not for himself manipulating receiver port repositioning information.
9.4.1 interrupt event
DSQ produces following interrupt event for CFG:
·RX_CH_VCAT_SK_RBID_CHG_DONE
9.5 configuration
Utilize 128 * 20 triggers to carry out following configuration parameter.
The RX_VCAT_SK_RBID_SEL parameter.
| Configuration parameter | Size | Value after the |
| RX_VCAT_SK_RBID_0 | ||
| 10 | | |
| RX_VCAT_SK_RBID_1 | ||
| 10 | Undefined |
Note, map to any channel that VC enables the receiver port break away from reset before, should reasonably dispose the reorder buffer configuration parameter of this port.
Notice that the DSQ module is carried out the activation/mapped access scheme that is used for these parameters, to keep and the VCT_TX structure compatible.When not relevant unsettled variation, the RX_VCAT_SK_RBID_SEL parameter recognition activates and duplicates.Software should be able to only read to activate and duplicate.Software can be in mapping be duplicated reading of data or data are write mapping duplicate.Software requirement activates or mapping is duplicated and will be changed by triggering the RX_VCAT_SK_RBID_SEL parameter.When changing, the DSQ module will change to carry out and interrupt.
9.6 state
Utilize 128 * 11 triggers to carry out following receiver port level state parameter.
| State variable | Size | Value after the |
| WR_BUF_SEL | ||
| 1 | 0 | |
| |
1 | 0 |
| |
1 | 0 |
| |
6 | 0 |
| |
1 | 0 |
| |
1 | 0 |
9.7 reorder buffer data storage
Disregarding data width is 9 bits, and the structure of reorder buffer memory is identical with reorder buffer memory in the VCT_YX functional block.With 1 as the DNU position.
9.8 sequence algorithm is separated in load
A lot of aspects, the class of algorithms that DSQ uses is similar to the load of using in the VCT_TX functional block and separates sequence algorithm, comprises resequencing buffer and the buffer upset that circulates based on schedule.Yet, also have some important differences.When writing resequencing buffer, load is separated sequence algorithm and is utilized channel sequence number, and knows that the next one of each VCG reads the position.In addition, DSQ need handle stop, channel-failures and DNU situation.
ALIG_RD can stop, and not only because data read arrives soon than it, and because when increasing when having the new branch road of long delay more than existing branch road, possibility must stop the data flow from the existing branch road of LCAS VCG.Yet the ALIG_RD design guarantees that VCG can not stop in the centre.In other words, in the schedule cycle period of respective type (and when not having the branch road channel-failures), all branch roads of VCG will send data in LVC/DSQ or they to and transmit data without any a meeting.Reduce the clear needs that write the byte number of each VCG like this, and allowed the schedule circulation to be used to the buffer upset.
Fault on authorization channel need be handled by DSQ.Under these circumstances, DSQ will make current write buffer invalid.LVC shields fault on undelegated channel, but is provided with the DNU position.
No matter whether have valid data as above described in the 8.7.3 chapters and sections, no matter whether it is load or H4/K4, and perhaps no matter whether channel is under failure/reset situation, and LVC gives DSQ with data passes in each clock circulation.Yet except having the situation of payload bytes that is not set to the authorization channel of DNU from current control word, LVC is provided with the DNU position under other all situations.Like this, DSQ does not need to be concerned about whether the byte that writes wherein is payload bytes veritably.
DSQ be in reset or the circulation of the clock of undelegated channel in deal with data or upgrade its situation not.Notice that non-VCAT channel can be set to zero in its authorization configuration position usually.
9.9 resequencing buffer
According to the current size of VCG, distribute resequencing buffer from of four ponds (pool), for each VCG.In logic, resequencing buffer comprises two buffers, for each possibility branch road of VCG, two spaces that all have a byte.When the load byte is written into a buffer, under any effective situation, from another buffer, read the load byte.At the schedule circulation time corresponding, exchange the buffer of given VCG with the type of VCG.
Disregarding data width is 9 bits that hold the DNU position, and the identical data buffer core that reorders that is used for the VCT_TX functional block can be used in DSQ.This core presents the form of four one-port memories with logic twin port memory, utilizes resequencing buffer ID and specifies the relevant position in the resequencing buffer can carry out addressing.
When the size of VCG need increase to capacity than the current resequencing buffer of distributing to it when big, need distribute bigger resequencing buffer to VCG.When in the VCT_TX framework, discussing, make required size to tankage, the feasible any combination that can hold VCG.
As employed load bank sequence algorithm in the VCR_TX functional block, load is separated sequence algorithm and is handled the resequencing buffer variation.At first, the process of writing switches to new resequencing buffer at first in the next schedule circulation of this VCG, then reads process in next one circulation.
The DSQ functional block makes and himself is synchronized with the resequencing buffer variation.Software arrangements resequencing buffer ID, and be wherein that given VCG configuration DSQ will use.In any branch road channel time slot of VCG, when DSQ found the current new value that is different from software arrangements of its use, it began to change when next one circulation beginning.When loop ends, carry out to switch, and DSQ will carry out variable signal to resequencing buffer and offers the CFR functional block.
9.10 buffer upset based on the schedule circulation
Because the schedule generator state of encoding in the RX_WID signal is offered DSQ clearly, DSQ when dislocation (wheel position) vanishing of finding respective type, the buffer of the VCG of the given type of overturning.
Following table shows the global buffer roll over condition that is used for different VCG types:
| The VCG type | When global buffer is selected upset |
| VC-4 | As RX_WID[13:10] when being zero (VC-4 dislocation is zero) |
| VC-3 | As RX_WID[13:8] when being zero (VC-4 and VC-3 dislocation are zero) |
| TU-3 | As RX_WID[13:8] when being zero (VC-4 and VC-3 dislocation are zero) |
| VC-12 | As RX_WID[13:2] when being zero (VC-4, VC-3, VC-2 and VC-11 dislocation are zero) |
| VC-11 | As RX_WID[13:4] and RW_WID[1:0] when being zero (VC-4, VC-3, VC-2 and VC-12 dislocation are zero) |
For each VCG type, DSQ safeguards overall WR_BUF_SEL state variable.These variablees overturn according to above condition.
In addition, each VCG safeguards the WR_BUF_SEL state variable of himself.When first path channels of VCG finds that the WR_BUF_SEL variable of this VCG is different from corresponding global state variable, trigger the VCG state variable.Guarantee that like this VCG state variable only is triggered once in corresponding schedule circulation.
9.11 the TID of ANA
According to the schedule and the channel type information that receive from the LVC module, the following dsq_ana_tid signal that provides to ANA is provided the DSQ module:
If(lvc_dsq_sts_VC4){
lvc_dsq_tid＝alig_rd_lvc_wid[12:9]＊84
}
Else If(～lvc_dsq_sts_vt){
dsq_ana_tid＝lvc_dsq_wid[12:9]＊84+lvc_dsq_wid[8:7]＊28
}
Else If(lvc_dsq_sts_vtg_type){//VC-11
dsq_ana_tid＝lvc_dsq_wid[12:9]*84+lvc_dsq_wid[8:7]＊28+
lvc_dsq_wid[6:4]＊4+lvc_dsq_wid[1:0]
}
Else{//VC-12
dsq_ana_tid＝lvc_dsq_wid[12:9]*84+lvc_dsq_wid[8:7]＊28+
lvc_dsq_wid[6:4]＊4+lvc_dsq_wid[3:2]
}
" vct_rx_uarch " file has the form of implementation of the optimization of these equations.
Whether relevant or channel is in failure/reset case to the channel relevant with this time slot with VCAT receiver port, and TID produces and carries out in each clock circulates.
Notice no matter whether channel is in reset case, does not influence channel architecture.Channel architecture information remains in the independent STS level register.
9.13 false code
// global write buffer is selected to upgrade and is checked
If(～lvc_dsq_ch_sts_vt){
If(lvc_dsq_ch_VC4){
If(lvc_dsq_wid[13:10]＝＝0){
RX_VCAT_VC4_WR_BUF_SEL＝～RX_VCAT_VC4_WR_BUF_SEL
}
}
Else{
If(lvc_dsq_wid[13:10]＝0){
RX_VCAT_VC3_WR_BUF_SEL＝～RX_VCAT_VC3_WR_BUF_SEL
}
}
}
Else{
If(lvc_dsq_ch_vtg_type＝＝0){//VT12
If(lvc_dsq_wid[13:2]＝＝0){
RX_VCAT_VC12_WR_BUF_SEL＝～RX_VCAT_VC12_WR_BUF_SEL
}
}
Else{
If((lvc_dsq_wid[13:4]＝＝0)&&(lvc_dsq_wid[1:0]＝＝0)){
RX_VCAT_VC11_WR_BUF_SEL＝～RX_VCAT_VC11_WR_BUF_SEL
}
}
}
// For channels in reset or thatare not accepted don’t
// process data and update state
If(～lvc_dsq_ch__rst && lvc_ch_accepted){
//Read the configuration memory entry for this VCG
{Rbid0，Rbid1，Rbid_Sel}＝DSQ_CFG_MEM[lvc_dsq_ch_sk_lpid]
// Read the state memory entry for this VCG
{Wr_Buf_Sel，
Buf0_Vld，
Buf1_vld，
Next_Rd_Pos
Rbid_Wr_Copy，
Rbid_Rd_Copy}＝DSQ_STATE_MEM[lvc_dsq_ch_sk_lpid]
//Determine if we are flipping the VCG of this channel or not
Flip＝0
If(～lvc_dsq_ch_sts_vt){
If(lvc_dsq_ch_VC4){
IF(lvc_dsq_wid[13:10]＝＝0){
Flip＝(RX_VCAT_VC4_WR_BUF_SEL!＝Wr_Buf_Sel)
}
}
Else{
If (lvc_dsq_wid[13:10]＝＝0){
Flip＝(RX_VCAT_VC3_WR_BUF_SEL!＝Wr_Buf_Sel)
}
}
}
Else {
If(lvc_dsq_ch_vtg_type＝0){// VT12
If(lvc_dsq_wid[13:2]＝＝0){
Flip＝(RX_VCAT_VCI2_WR_BUF_SEL!＝Wr_Buf_Sel)
}
}
Else{
If ((lvc_dsq_wid[13:4]＝＝0)&&(lvc_dsq_wid[1:0]＝＝0)){
Flip＝(RX_VCAT_VC11_WR_BUF_SEL!＝Wr_Buf_Sel)
}
}
}
If(Flip){
// Flip the buffers
Wr_Buf_Sel＝～Wr_Buf_Sel
// Initially buffer is valid
Wr_Buf_Vld＝1
// Next read position starts at zero at the beginning of a
// calendar rotation
NeXt_Rd_POS＝0
// Update reorder buffer copy used by write and read side
// if a change requested and generate interrupt when change
// is done
If(Rbid_Sel!＝Rbid_Wr_Copy){
Rbid_Wr_Copy＝Rbid_Sel
}
Else If(Rbid_Sel!＝Rbid_Rd_copy){
Rbid_Rd_Copy＝Rbid_Sel
Generate RX_SK_RBID_CHG_DoNE interrupt for
lvc_dsq_ch_sk_lpid
}
}
// Determine the read and write buffer ids to use in this cycle
If(Rbid_Wr_Copy){
Wr_Rbid＝Rbid1
}
Else{
Wr_Rbid＝Rbid0
}
If(Rbid_Rd_Copy){
Rd_Rbid＝Rbid1
}
Else{
Rd_Rbid＝Rbid0
}
// A fail condition on an accepted channel causes current
// write buffer to be invalidated
If (lvc_dsq_ch_fail){
Wr_Buf_Vld＝0
}
// Do the write
If (lvc_dsq_ch_sq<＝GET_RB_CAPACITY(Wr_Rbid)){
WRITE_TO_RB(Wr_Rbid，
Wr_Buf_Sel，
lvc_dsq_ch_sq，
lvc_dsq_ch_dnu，
lvc_dsq_ch_data)
}
// Do the read
{Rd_Data，Rd_DNU}＝READ_FROM_RB(Rd_Rbid，
～Wr_Buf_Sel，
Next_Rd_Pos)
Next_Rd_POs++
// Generate the data and data valid signals to ANA
If (Rd_Buf_Vld &&～Rd_DNU){
// Got valid payload data to send out
dsq_ana_data_vld＝1
dsq_ana_data＝Rd_Data
}
Else{
dsq_ana_data_vld＝0
}
// Update the VCG state
If (Wr_Buf_Sel){
Buf1_Vld＝Wr_Buf_Vld
}
Else{
Buf0_Vld＝Wr_Buf_Vld
}
DSQ_STATE_MEM[lvc_dsq_ch_sk_lpid]＝{Wr_Buf_Sel，
Buf0_Vld，
Buf1_Vld，
Next_Rd_Pos
Rbid_Wr_Copy，
Rbid_Rd_Copy}
}
Else{//Channel in reset or not accepted
dsq_ana_data_vld＝0
dsq_ana_data＝0//dummy
}
// LPID is passed th rough for non-VCAT channels
dsq_ana_lpid＝lvc_dsq_ch_sk_lpid
// Generate the TID for ANA for non-VCAT channels
If(lvc_dsq_sts_vt){
If(lvc_dsq_sts_vtg_type){// VC-11
dsq_ana_tid＝lvc_dsq_wid[12:9]＊84+
lvc_dsq_wid[8:7]＊28+
lvc_dsq_wid[6:4]＊4+
lvc_dsq_wid[1:0]
}
Else{//VC-12
dsq_ana_tid＝lvc_dsq_Wid[12:9]＊84+
lvc_dsq_wid[8:7]＊28+
lvc_dsq_wid[6:4]＊4+
lvc_dsq_wid[3:2]-
}
}
Else If(lvc_dsq_sts_vc4){
lvc_dsq_tid＝alig_rd_lvc_wid[12:9]＊84
}
Else{
dsq_ana_tid＝lvc_dsq_wid[12:9]＊84+lvc_dsq_wid[8:7]＊28
}
1 summary
1.1 Function Decomposition model
Fig. 8 shows the high-order element that virtual concatenation sends (VCT_TX) functional block.VCT_TX 800 is connected with CPU 802, and comprises and be used for the configuration module 804 that communicates with CPU.This configuration module also communicates with load sorting unit 806 (it is connected with output OFR 808), and communicates with path overhead generator 810.This configuration module and path overhead generator all receive the input from overall multi-frame indication (indicator) and group id (GID) generator module 812.Load sorting unit and path overhead generator are multiplexing, all are SPE byte and control data, and output is sent to interconnection (CXC).The data path of VCT_TX functional block is driven by the request from CXC fully, thereby has produced frame schedule (comprising the circulation of VT super frame).
When CXC effectively asks in the circulation of given clock, its allocated channel ID and frame position information, for example row number and row number.According to such information, the TX_VCAT functional block determines whether be used for the load byte or be used for overhead byte from the request of CXC, and in the situation afterwards, it determines produce which kind of concrete overhead byte.Load requests is transferred into load sorting unit functional block, and the overhead byte request is transferred into passage generator functional block.Data output from these functional blocks is synchronous, and is multiplexed into the data input of CXC.
In order to support the VCAT function, will transmit by the load sorting unit from the load byte that OFR extracts.The order different in proper order with the transmission gap of channel can appear because be dispensed to the sequence number of the path channels of VCG, before being sent to CXC, and the load data byte that needs buffering to extract from OFR.The specific load bank sequence algorithm of selecting has been described in this article.
The path overhead generator provides the response for all path overhead bytes.Yet, disregard the H4/Z7 byte, produced 0.The path overhead generator uses overall MFI and GID counter and each channel internal state to produce the H4/Z7 overhead byte.
In order to support LCAS, two of config memory that keep storage VCAT forward control information and the reverse control information of LCAS duplicate.When software requirement change specific LCAS VCG be configured to change its line state or upgrade the reverse control information of LCAS the time, in response to the beginning of LCAS controlling packet, overall MFI counter is used to make configuration variation and frame boundaries synchronous.
The data path that is used for channel is not shown, this channel bearing packet data, but be not virtual concatenation.Yet, in this article with the formal description of action specification the Data Stream Processing of this channel.
Sequence algorithm is conciliate in 2 loads ordering
According to one embodiment of present invention, the system and method that is used to carry out the load bank sequence algorithm is for propping up the byte rearrangement that the transmission gap number of path channels extracts in proper order from the packet lateral root according to VCG, to mate the programmed sequence order of these channels.It also is configured to handle dynamic VCG branch road state variation.
The employed load bank sequence algorithm of VCT_TX functional block can be described in different stage.In a rank, the basic rearrangement algorithm that is used for single VCG has been described, it is the core of whole load bank sequence algorithm.The rearrangement algorithm utilizes double buffering to handle VCG branch road state variation to support LCAS.
Should be noted that,, can reuse basic rearrangement algorithm separating in the preface device modular design of VCT_RX functional block.In fact, may in two functional blocks, use identical rearrangement core logic.
Then, described how this algorithm carries out work for a plurality of VCG in VCT_RX functional block environment.Key point is that the VCG of dissimilar (that is, propping up the type of path channels) has different schedule cycle periods herein.For example, ignore invalid clock circulation, the VCG of STS-1 type will have the circulation schedule of 48 clocks, and the VCG of VT-1.5/TU-11 type will have the circulation schedule of 1344 clocks.The design of the schedule cycle period of VCG is important in the VCT_TX functional block, controls VCG when conversion between the read and write process because the load bank sequence algorithm utilizes schedule to circulate.
At last, introduced based on the notion of the VCG buffer that maximizes the VCG size to pond (pair pool), the buffer that provides is to supporting this maximization VCG size.For the quantity that reduces buffer storage, this is a best-of-breed technology.Because VCG branch road state variation, require the expansion of rearrangement algorithm, be used for from the buffer in different ponds between switch.
2.1 be used for the rearrangement algorithm of virtual concatenation group (VCG)
How 9 is used for each VCG with a pair of buffer if showing the rearrangement algorithm.The byte capacity of each buffer is equal to or greater than the quantity of VCG branch road.The read and write process is switched between these two buffers.When the process of writing write a buffer, read procedure is reading of data from another buffer.Notice that two processes are all driven by the CXC request.
The process of writing is safeguarded the NEXT_WR_POS state quantities for each VCG.At first, this variable is set to zero.When CXC is that given channel is when requiring the load byte, the process of writing extracts byte from the OFR of the TX_PL_LPID configuration parameter that utilizes this channel, and it is stored in the current write buffer of this VCG in the position that utilizes NEXT_WR_POS state quantities index.
When byte being write the current write buffer of VCG, the NEXT_WR_POS state quantities of VCG increases seriatim at every turn.When the byte number that writes VCG equaled the size of this VCG, this variable was set to zero once more, and the step that next time writes this VCG can take place after exchange buffering.
When CXC is a given channel when requiring the load byte, read procedure loads byte in the position corresponding to the configuration VCAT sequence number of this channel from the current read buffer of VCG.Therefore unlike write operation, continuous reading cannot be visited continuous position in the current read buffer.
The rearrangement algorithm is not known the size of VCG, and therefore can not switch the VCG buffer between the read and write process by himself determining when.Suppose that this is followed respectively, and buffer will switch, externally the NEXT_WR_POS variable will be reset under Dai Li the control.In the situation of VCT_TX functional block, because all branch roads of the VCG of given type should write a byte in a schedule circulation that is used for the type, can switch buffer, and can be in the schedule of the type circulation beginning or the NEXT_WR_POS state quantities of all VCG of replacement the type when finishing.
Notice that the supposition of rearrangement algorithm to writing when finishing, is also finished from the read operation that circulates before.Because read and write all drives from identical schedule, so this obviously is correct for the VCT_TX functional block.Note,, and can not stop, so this hypothesis is also supported the VCT_RX functional block because the every clock of IFR can receive new request.The VCT_RX functional block need be handled to write and stop, but this handles outside the rearrangement algorithm encloses.
2.1.1 dynamically branch road changes
Change in order to handle dynamic VCG branch road, read procedure moves a circulation schedule according to the Configuration Values of its use after writing process.Configuration variation can only exert an influence to the corresponding frame boundaries of beginning with LCAS control data bag.So VCG for given type, when circulating schedule the first time of the type, the process of writing can utilize new configuration (according to which channel to be the branch road of this VCG and to be the data of requirement, promptly, control word is the channel of NORM/EOS), this circulation Schedule type is consistent with frame, and this frame is consistent with the beginning of the LCAS control data bag of the type, and the configuration before the read procedure utilization (which channel is the branch road of this VCG and is the data of requirement and their sequence number).In next schedule circulation, read procedure also utilizes new configuration.
During the initialization of VCG, before path channels was broken away from reset mode, the inventor supposed that the duplicating of control word that software will be used for this channel is set to IDLE.Therefore, read or the process of writing can during initialization, visit the rearrangement buffer.Then, when the control word configuration of propping up path channels of some or all is set to NORM/EOS, the process of writing will at first be found configuration change, and beginning began to write a circulation before read procedure is found configuration change and begun to read.
The example that provides in next chapters and sections shows the operation of the algorithm under the dynamic-configuration change.In order to simplify, the inventor will consider the single high-order VCG in the STS-3 frame in example.
2.1.2 rearrangement algorithm running example
In the example that these chapters and sections provide, consider to begin to have the single VCG of two branch roads.In each time slot, example shows from OFR and to extract and the data byte of write buffer, read and send to the content of data byte and the buffer of CXC from buffer.
Round | -
1 | 0 | 1 |
| | | |
slot | 0 1 2 | 0 1 2 | 0 1 2 |
| | | |
NEXT_WR_POS| - 0 1 | - 0 1 | - 0 1 |
| | | |
Input | - D0 D1| - D2 D3| - D4 D5|
| | | |
TX_VCAT_SQ | - 1 0 | - 1 0 | - 1 0 |
| | | |
WrBuf | A A A | B B B | A A A |
WrAddr | - 0 1 | - 0 1 | - 0 1 |
| | | |
RdBuf | B B B | A A A | B B B |
RdAddr | - - - | - 1 0 | - 1 0 |
| | | |
BA-0 | - D0 D0| D0 D0 - | - D4 D4|
BA-1 | - - D1| D1 - - | - - D5|
BA-2 | - - - | - - - | - - - |
| | | |
BB-0 | - - - | - D2 D2| D2 D2 - |
BB-1 | - - - | - - D3| D3 - - |
BB-2 | - - - | - - - | - - - |
| | | |
Output | - 0 0 | - D1 D0| - D3 D2|
Table A: the example of initial branch road
Round | 12382 | 12383 |
12384 |
12385 |
| | | | |
Slot |0 1 2 |0 1 2 |0 1 2 |0 1 2 |
| | | | |
NEXT_WR_POS|- 0 1 |0 1 2 |0 1 2 |0 1 2 |
Input |- D24766 D24767|D24768 D24769 D24770|D24771 D24772 D24773|D24774 D24775 D24776|
| | | | |
TX_VCAT_SQ |- 1 0 |2 1 0 |2 1 0 |2 1 0 |
| | | | |
Wrguf |B B B |A A A |B B B |A A A |
wrAddr |- 0 1 |0 1 2 |0 1 2 |0 1 2 |
| | | | |
RdBuf |A A A |B B B |A A A |B B B |
RdAddr |- 1 0 |- 1 0 |2 1 0 |2 1 0 |
| | | | |
BA-0 |D24764 D24764 - |D24768 D24768 D24768|D24768 D24768 - |D24774 D24774 D24774|
BA-1 |D24765 - - |- D24769 D24769|D24769 - - |- D24775 D24775|
BA-2 |- - - |- - D24770|- - - |- - D24776|
| | | | |
BB-0 |- D24766 D24766|D24765 D24766 - |D24771 D24771 D24771|D24771 D24771 - |
BB-1 |- - D24767|D24767 - - |- D24772 D24772|D24772 - - |
BB-2 |- - - |- - - |- - D24773|- - - |
| | | | |
Output |- D24765 D24764|- D24767 D24766|D24770 D24769 D24768|D24773 D24772 D24771|
Table B: branch road additional example
First embodiment that illustrates shown from the algorithm operation (that is, the first load byte 0 of STS-1) of 0 beginning that circulates, and suppose to circulate 0 to begin corresponding to the high-order multi-frame.Note that the VCG configuration is not had the leg modifications of activation for having two activation branch roads (that is, the final load byte 2 of STS-1) from circulation before, it is-1 by label.
The algorithm that the next example that provides among the B at table shows when in next multi-frame new branch road being increased to VCG moves, it is in schedule circulation 12,384 places begin, note once more, because after writing process, read procedure has fallen behind a circulation, so the end that is configured in multiframe boundaries (promptly, schedule circulation 12,383) changes.The inventor supposes that the size of VCG buffer is at least 3 bytes and increases to hold new branch road.
The algorithm operating that the last example that provides among the C at table shows the branch road that will have sequence number 0 at next multi-frame place when removing from VCG, it begins at schedule 24,768 places of circulating.
Round |
24766 |
24767 | 24768 | 24769 |
| | | | |
slot |0 1 2 |0 1 2 |0 1 2 |0 1 2 |
| | | | |
NEXT_WR_POS|0 1 2 |0 1 - |0 1 - |0 1 - |
| | | | |
Input |D61920 D61921 D61922|D61923 D61924 - |D61925 D61926 - |D61927 D61928 - |
| | | | |
TX_VCAT_SQ |2 1 0 |1 0 - |1 0 - |1 0 - |
| | | | |
WrBuf |B B B |A A A |B B B |A A A |
WrAddr |0 1 2 |0 1 - |0 1 - |0 1 - |
| | | | |
RdBuf |A A A |B B B |A A A |B B B |
RdAddr |2 1 0 |2 1 0 |1 0 - |1 0 - |
| | | | |
BA-0 |D61917 D61917 - |D611923 D611923 D61923|D61923 - - |D61927 D61927 D61927|
BA-1 |D61918 - - |- D61924 D61924|- - - |- D61928 D62928|
BA-2 |- - - |- - - |- - - |- - - |
| | | | |
BB-0 |D61920 D61920 D61920|D61920 D61920 - |D61925 D61925 D61925|D61925 - - |
BB-1 |- D61921 D61921|D61921 - - |- D61926 D61926|- - - |
BB-2 |- - D61922|- - - |- - - |- - - |
| | | | |
Output |D61919 D61918 D61917|D61922 D61921 D61920|D61924 D61923 - |D61926 D61925 - |
Table C: branch road is removed example
2.1.3 handling the interim branch road of LCAS removes
The LCAS agreement utilizes the DNU control word to represent that branch road is removed temporarily.When channel was in the DNU state, it is the carry load data not.Writing side, therefore hardware should not extract load data in the time slot of this channel from OFR.Reading side, it should send zero.
Yet the sequence number that transmits in LCAS control data bag does not change when one or more branch roads are in the DNU situation.Read to handle if use the sequence number that send in LCAS control data bag to control, the algorithm of resequencing so can correctly not move when the one or more branch roads of VCG are in the DNU situation.Therefore, hardware utilizes the independent sequence number of load and expense to handle interim branch road removal.
Table D show the branch road with sequence 1 enter the DNU state rather than during by permanent delet algorithm how to move.Suppose that first schedule that circulation 12384 is opened corresponding to the H4 byte in the frame of beginning the one LCAS control data bag circulates, it represents the DNU of this branch road.For 16 frames less than a schedule, that is, up to circulation 24767, load configuration can not change.In this schedule circulation place, load configuration changes.
Round |
24766 |
24767 | 24768 | 24769 |
| | | | |
slot |0 1 2 |0 1 2 |0 1 2 |0 1 2 |
| | | | |
NEXT_WR_POS|0 1 2 |0 1 - |0 1 - |0 1 - |
| | | | |
Input |D61920 D61921 D61922|D61923 D61924 - |D61925 D61926 - |D61927 D61928 - |
| | | | |
TX_VCAT_SQ |2 1 0 |1 0 - |1 0 - |1 0 - |
| | | | |
WrBuf |B B B |A A A |B B B |A A A |
WrAddr |0 1 2 |0 1 - |0 1 - |0 1 - |
| | | | |
RdBuf |A A A |B B B |A A A |B B B |
RdAddr |2 1 0 |2 1 0 |1 0 - |1 0 - |
| | | | |
BA-0 |D61917 D61917 - |D61923 D61923 D61923|D61923 - - |D61927 D61927 D61927|
BA-1 |061918 - - |- D61924 D61924|- - - |- D61928 D62928|
BA-2 |- - - |- - - |- - - |- - - |
| | | | |
BB-0 |D61920 D61920 D61920|D61920 D61920 - |D61925 D61925 D61925|D61925 - - |
BB-1 |- D61921 D61921|D61921 - - |- D61926 D61926|- - - |
BB-2 |- - D61922|- - - |- - - |- - - |
| | | | |
Output |D61919 D61918 D61917|D61922 D61921 D61920|D61924 D61923 - |D61926 D61925 - |
Table D: interim branch road is removed example
Note, will be used for load sequence number rearrangement, that be called as TX_VCAT_PL_SQ be configured to seemingly branch road be eliminated the same, although the sequence number that uses in expense, be called as TX_LCAS_OH_SQ does not change.
2.2 consider the load bank sequence algorithm of a plurality of VCG
Show the load bank sequence algorithm as how four dissimilar VCG operations.Buffer A and B represent two copy data buffer storage, the double buffering scheme of its algorithm that is used to support to resequence.Suppose that the schedule that is used for all channel types is created in clock 0 place to begin.
According to the schedule cycle period of these VCG of (effectively) clock cyclic number purpose shown in the following table:
| VCG number | Type | The schedule |
| 1 | STS- |
16 |
| 2 | STS-1 | 48 |
| 3 | VT-2 | 1008 |
| 4 | VT-1.5 | 1344 |
Because the difference between the schedule cycle period of different channels type, for each VCG type, need know the reorder buffer memory which duplicate and be used to write and which duplicates and is used to read.When schedule is given channel type circulation time, all VCG of the type switch the Writing/Reading view of their reorder buffer memories.Figure 10 shows the load bank sequence algorithm with dissimilar VCG.
Note, handle pipeline by adjusting read and write, one-port memory can be used for data buffer, make in given clock, only a VCG reads and writes from the buffering memory.
2.3 resequencing buffer pond
According to the capacity of resequencing buffer, resequencing buffer is combined in the following pond:
64 byte pool;
32 byte pool;
16 byte pool; And
8 byte pool.
VCG distributes to the resequencing buffer in the concrete pond by the size of software according to this VCG.For example, if VCG has 10 path channels at first, it can be distributed to the resequencing buffer in 16 byte pool.Surpass 16 branch roads if need after a while the size of this VCG increased, can need so VCG is shone upon bigger buffer to wherein.By identical mark, if being reduced in future, the size of VCG is lower than 8, it is right that VCG can switch position 8 byte buffer, so that 16 byte buffer are to effective for another VCG that may need it.In following chapters and sections will to buffer between this handover mechanism be described.
Provide the sum of the channel that may need virtual concatenation, can determine the right number of buffer that each pond need have, in the VCG combination, not have restriction.For 1344 channels, we can carry out following operation:
1.33 the maximum number of individual branch road VCG is 40.Because can be used for unique pond of these VCG is 64 byte pool, the capacity in 64 byte buffer ponds must be 40;
2.17 the maximum number of individual branch road VCG is 79.For them, both can utilize 64 byte pool also can utilize 32 byte pool.If use all buffers in 64 byte pool right, in 32 byte pool, can need 79-40=39 buffer right for them;
3.9 the maximum number of individual branch road VCG is 149.For them, can utilize 64 byte pool, 32 or 16 byte pool.If use all buffers in 64 byte pool, 32 byte pool and 16 byte pool right, in 16 byte pool, can need 149-79-40=70 buffer right for them;
4.8 the maximum number of individual branch road VCG is 168.For them, can utilize 64 byte pool, 32 byte pool or 16 byte pool.If use all buffers in 64 byte pool, 32 byte pool and 16 byte pool right, in 8 byte pool, can need 168-70-39-40=19 buffer right for them.
In a word, support that the capacity of needs in each pond of 1344 channels is as follows:
| The pond type | Tankage |
| 64 bytes | 40 |
| 32 bytes | 39 |
| 16 bytes | 70 |
| 8 |
19 |
The whole quantity that requirement has the buffering byte of buffer unit pool optimization is 10160 bytes.Do not have such optimization, that is, suppose that each VCG can have 64 branch roads, the byte of requirement can be 32768 bytes.Ignore the poor efficiency that relates to the memory construction of supporting buffer unit pool, this expression has saved about 69%.
Note because the quantity (128) of the VCG that the overall quantity (168) of rearrangement buffer is supported greater than needs, so be indifferent to used all VCG with situation and in them neither one have and surpass 8 branch road.
2.3.1 switching resequencing buffer
Switching to another type from one type resequencing buffer takes place at the schedule boundary.Because the read and write process is the variation between two buffers of the resequencing buffer on the frame boundaries after all, switch to another type from one type resequencing buffer and can change the identical method of using as handling dynamic branch road, promptly, by after writing process, make and read to find configuration change a schedule.Switch for resequencing buffer, VCG becomes resequencing buffer mapping configuration.
Show and how to finish the resequencing buffer switching.Less buffer in schedule circulation N is to being the current resequencing buffer that VCG uses.In circulation N+1, the process of writing uses new buffer right, but read procedure reads from old buffer centering.From circulation N+2, for the read and write process, it is right that VCG has switched to new bigger buffer, and old buffer is to turning back to the pond.
The next resequencing buffer that software need specify VCG to use, and provide indication about the variation of affected VCG request to hardware.In case hardware is found to indication, it will at first be write the switching of this VCG to handle at next schedule boundary and switch to new buffer.In following schedule border, read procedure also will switch to new buffer.
Figure 11 show buffer between the example that switches.Notice that resequencing buffer switches can occur in any schedule boundary, so it can be separated from the branch road configuration variation that occurs in multiframe boundaries.For example, before increasing new branch road to VCG, software can at first switch to VCG new buffer or bigger capacity, and then new branch road is increased to VCG.When branch road is removed, software can finish remove operation after, it is right that VCG is switched to less buffer.
On the other hand, for why the resequencing buffer switching can not be carried out in the VCT_TX functional block in the branch road configuration variation, without any reason.By making up them, identical software arrangements change mechanism can be used to carry out VCAT forward configuration change.The inventor supposes that this is a kind of situation in the configuration mode of describing in the chapters and sections 3.
2.3.2 resequencing buffer switches sample
Table E provide an example that how to utilize two resequencing buffers at buffer between transfer period.In this example, utilize resequencing buffer 1 initialization VCG in schedule circulation 0 with two byte capacities.Beginning in circulation 2, VCG switches to resequencing buffer 2, and it has the capacity of 3 bytes.End in circulation 4 finishes handover operation, and resequencing buffer 1 can be another VCG use.
Rourd | 0 | 1 | 2 | 3 |
| | | | |
slot | 0 1 2 | 0 1 2 | 0 1 2 | 0 1 2 |
| | | | |
NEXT_WR_POS|- 0 1 | - 0 1 | - 0 1 | - 0 1 |
| | | | |
Input | - D0 D1| - D2 D3| - D4 D5| - D6 D7|
| | | | |
TX_VCAT_SQ | - 1 0 | - 1 0 | - 1 0 | - 1 0 |
| | | | |
WrBuf | A1 A1 A1| B1 B1 B1| A2 A2 A2| B2 B2 B2|
WrAddr | - 0 1 | - 0 1 | - 0 1 | - 0 1 |
| | | | |
RdBuf | B1 B1 B1| A1 A1 A1| B1 B1 B1| A2 A2 A2|
RdAddr | - - - | - 1 0 | - 1 0 | - 1 0 |
| | | | |
A1-0 | - D0 D0| D0 D0 - | - - - | - - - |
A1-1 | - - D1| D1 - - | - - - | - - - |
| | | | |
B1-0 | - - - | - D2 D2| D2 D2 - | - - - |
B1-1 | - - - | - - D3| D3 - - | - - - |
| | | | |
A2-0 | - - - | - - - | - D4 D4| - D4 - |
A2-1 | - - - | - - - | - - D5| - - - |
A2-2 | - - - | - - - | - - - | - - - |
| | | | |
B2-0 | - - - | - - - | - - - | - D5 D5|
B2-1 | - - - | - - - | - - - | - - D7|
B2-2 | - - - | - - - | - - - | - - - |
| | | | |
Output | - 0 0 | - D1 D0| - D3 D2| - D5 D4|
Table E: switch to bigger buffer to example
3 allocation models
Some configuration parameters describe in channel level, and other illustrate in the VCG level.According to they whether make a comment or criticism separately to or oppositely, the channel level parameter is added prefix TX_CH, and VCG level parameter is added prefix TX_SO or TX_SK.
Except the TX_CH_SO_LPID parameter, it is the channel of VCG branch road that all configuration parameters can be applicable to.In these parameters some only are applied to LCAS VCG.And other parameters are applied to non-LCAS and LCAS VCG.By being used in, LCAS distinguishes the parameter that only is applied to LCAS VCG in the parameter name.By being used in, VCAT distinguishes the parameter that is applied to non-LCAS and LCAS VCG in the parameter name.
When there being any not the resetting during transmitting channel of given logic port of mapping to, in some sense, control sends the configuration parameter of the loadtype of logic port, be TX_SO_VCAT_EN and TX_SO_LCAS_EN parameter, be static, these parameter values that are used for this logic port should not change.
In some sense, every other parameter is dynamic, can change them and the channel that need not reset.Yet, under the situation of TX_CH_SO_LPID parameter, be assigned to VCG (promptly if channel is current, set SO_VCAT_EN), so before changing the TX_CH_SO_LPID parameter of this channel, should be at first be IDLE (and fully changing) with the TX_CH_VCAT_CTRL parameter change of this channel.
Software triggers configuration change independently in four levels:
The configuration of VCG level VCAT/LCAS forward;
Reverse MST of VCG level LCAS and RS_ACK configuration;
Channel level LCAS oppositely inserts the configuration that receiver port and insertion enable; And
The channel level source port of mapping configuration.
VCG forward or backwards the configuration parameter that changes of level require two to duplicate supporting dynamic VCG configuration change, thereby support LCAS, and under the situation of non-LCAS VCG, support VCG to reach the destination in an orderly manner and stop.
Notice that even specified some dynamic-configuration parameters (as TX_VCAT_CTRL) in channel level, but they change in the VCG level.This configuration change that allows to comprise a plurality of path channels carries out simultaneously.
Following table provide a row configuration parameter, they static state/dynamic class and they are in which kind of grade change:
| Configuration parameter | Static or dynamic | Change level | Duplicate |
| TX_CH_SO_LPID | Dynamically 1 | The channel forward | 1 |
| TX_CH_VCAT_PL_SQ | Dynamically | The VCG forward | 2 |
| TX_CH_LCAS_OH_SQ | Dynamically | The VCG forward | 2 |
| TX_CH_VCAT_CTRL | Dynamically | The VCG forward | 2 |
| TX_CH_LCAS_REV_INS_EN | Dynamically | Channel is reverse | 1 |
| TX_CH_LCAS_REV_INS_SK_LPID | Dynamically | Channel is reverse | 1 |
| TX_SO_VCAT_EN | Static | N/ |
1 |
| TX_SO_LCAS_EN | Dynamically | N/ |
1 |
| TX_SO_VCAT_RBID | Dynamically | The VCG forward | 2 |
| TX_SK_LCAS_MST | Dynamically | VCG is reverse | 2 |
| TX_SK_LCAS__RS_ACK | Dynamically | VCG is reverse | 2 |
Note 1: even the TX_CH_SO_LPID parameter is dynamic, in order to guarantee the VCG configuration change in an orderly manner, if channel at the current VCG that is assigned to, so at first should be IDLE with the TX_CH_VCAT_CTRL parameter change of this channel and finished the forward change before finishing the TX_CH_SO_LPID parameter that changes it.
For having two configuration parameters that duplicate, the configuration variation controlling mechanism of same type is used for VCG level variation forward or backwards.Duplicating of the configuration that software utilization selection position specify hardware should be used.It is synchronous that hardware changes with suitable frame boundaries this, and changing by interrupting informing when finishing software.
During switching to new configuration, because hardware can use configuration before, so software should not change the configuration before of VCH from previous configuration.The amount of switching time depends on oppositely whether changing of forward configuration and whether VCG is that LCAS enables.
3.1 config memory
The memory that storage static configuration parameter and dynamic-configuration change Control Parameter must be a twin port, visit in the time of with support hardware and software.
The memory of storage static configuration parameter also is a twin port, is necessary for when before variation is in the processing and realizes the new time quantum that changes (being changed to other VCG probably) and wait for to reduce software.This is because during the configuration hand-off process, and for low order LCAS VCG, two of configuration parameter duplicate all need be in up to 32ms effectively.
Because CXC provides the such information with each request, so in the VCT_TX functional block, do not require the channel type configuration.
Be not illustrated in the parity check bit that is used for error detection in the config memory.
Notice that the Global reset position that is used for VCT_TX remains on outside the functional block.
3.1.1 global configuration
| Parameter | Size | Initial value behind the Global reset |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | 0 |
FAST_LOCK_EN is applied to VCT_TX and VCT_RX.So it should remain on outside the VCT_TX functional block.TX_MFI_EN and TX_SHORT_FRAME_EN only are applied to the VCT_TX functional block, but they also can remain on outside this functional block.
Notice that the purpose that designs these global configuration parameters is to quicken checking.They should not be included in the tables of data.
3.1.2 each channel configuration
3.1.2.1 TX_LPID_CFG_MEM
Following configuration parameter is combined in 1344 * 9 the twin port memory, and it is by high-order and low order Channel Sharing:
| Parameter | Size | Initial value behind the Global reset |
| |
1 | 1 |
| |
8 | |
| TX_CH_LCAS_REV_INS_EN | ||
| 8 | 0 | |
| |
8 | Undefined |
3.1.2.2 TX_CH_VCAT_FWD_CFG_MEM_0/1
Following configuration parameter is combined in 1344 * 16 the twin port memory, and it is by high-order and low order Channel Sharing:
| Parameter | Size | Initial value behind the Global reset |
| |
6 | |
| TX_CH_VCAT_OH_SQ | ||
| 6 | | |
| TX_CH_VCAT__PL_CTRL | ||
| 4 | IDLE |
Exist two of such memory to duplicate to support dynamic VCG configuration change.Software utilizes the TX_SO_VCAT_FWD_SEL configuration parameter to formulate each VCG switching requirement.Hardware compares TX_SO_VCAT_FWD_SEL configuration parameter and inner TX_SO_VCAT_FWD_COPY state quantities.If their differences, this just means that software has required to change.When switching was carried out, hardware was with set TX_SO_VCAT_FWD_CHG_DONE interrupt status position.
3.1.3 each VCG config memory
3.1.3.1 TX_SO_PL_TYPE_CFG_MEM
Following configuration parameter is combined in 128 * 2 the memory:
| Parameter | Size | Initial value behind the Global reset |
| |
1 | 0 |
| |
1 | 0 |
When the channel disengaging maps to resetting of this port, should not change these parameters.
3.1.3.2 TX_SO_VCAT_RBID_CFG_MEM_0/1
Following configuration parameter is combined in the memory of twin port 128 * 10:
| Parameter | Size | Initial value behind the |
| TX_SO_VCAT_RBID | ||
| 10 | Undefined |
Exist two of such memory to duplicate to support dynamic VCG configuration change.Software utilizes the TX_SO_VCAT_FWD_SEL configuration parameter to formulate each VCG switching requirement.Hardware compares TX_SO_VCAT_FWD_SEL configuration parameter and inner TX_SO_VCAT_FWD_COPY state quantities.If their differences, this just means that software has required to change.When switching was carried out, hardware was with set TX_SO_VCAT_FWD_CHG_DONE interrupt status position.
3.1.3.3 SO_VCAT_FWD_SEL_CFG_MEM
Following configuration parameter is combined in the memory of twin port 128 * 2:
| Parameter | Size | Initial value behind the |
| TX_SO_VCAT_FWD_SEL | ||
| 1 | 0 | |
| |
1 | 0 |
3.1.3.4 SK_LCAS_REV_SEL_CFG_MEM
Following configuration parameter is combined in the memory of twin port 128 * 2:
| Parameter | Size | Initial value behind the |
| TX_SK_LCAS_REV_SEL | ||
| 1 | 0 | |
| |
1 | 0 |
3.1.3.5 SK_LCAS_REV_CFG_MEM_0/1
Following configuration parameter is combined in the memory of twin port 128 * 65:
| Parameter | Size | Initial value behind the Global reset |
| TX_SK_LCAS_INS_MST | 64 | 1 |
| |
1 | 0 |
Exist two of such memory to duplicate to support dynamic VCG configuration change.Software utilizes the TX_SK_LCAS_REV_SEL configuration parameter to formulate each VCG switching requirement.Hardware compares TX_SK_LCAS_REV_SEL configuration parameter and inner TX_SK_LCAS_REV_COPY state quantities.If their differences, this just means that software has required to change.When switching was carried out, hardware was with set TX_SK_LCAS_REV_CHG_DONE interrupt status position.
4 interrupt status patterns
4.1 interrupt status memory
Software has the write access for the interrupt status memory, to read and to remove the interrupt status position.Hardware only needs write access so that the interrupt status position to be set.
If the interrupt status position read request from software is asked conflict with write (that is, set) from hardware, the new value from write request transmits as reading the result so.
Conflict set interrupt status so if remove the set request of asking with from hardware from the interrupt status of software.
4.1.1 each VCG interrupt status memory
4.1.1.1 TX_SO_VCAT_FWD_CHG_DONE_MEM
Following interrupt configuration parameter is combined in the memory of twin port 128 * 1:
| Parameter | Size | Initial value behind the Global reset |
| |
1 | 0 |
5 situation patterns
Unless possibility in diagnostic mode, status register does not need to pass through softward interview.
In these chapters and sections, except load sorting unit buffer, the not shown parity check bit that is used for error detection in all situation memories.
5.1 situation memory
5.1.1 each channel conditions memory
5.1.1.1 TX_CH_LCAS_STATE_MEM
Following state variable is combined in 1344 * 12 memories of twin port, and it is by high-order and low order Channel Sharing:
| Parameter | Size | Initial value after channel resets |
| |
8 | 0 |
| |
1 | 0 |
5.1.2 each VCG situation memory
5.1.2.1 TX_SO_VCAT_STATE_MEM
Following state variable is combined in the memory of twin port 128 * 10:
| Parameter | Size | Initial value behind the Global reset |
| |
1 | 0 |
| |
2 | 0 |
| |
1 | 0 |
| |
6 | 0 |
Although above memory supposes that every VCG keeps writing the buffer storage choice situation,, can use the global variable of each VCG type for such purpose.
5.1.2.2 TX_SK_LCAS_STATE_MEM
Following state variable is combined in the memory of twin port 128 * 3:
| Parameter | Size | Initial value behind the Global reset |
| |
1 | 0 |
| |
1 | 0 |
| |
1 | Undefined |
5.2 global state variable
| Parameter | Size | Initial value behind the Global reset |
| |
4 | 0 |
| |
8 | 0 |
| |
16 | 0 |
| |
5 | 0 |
| |
5 | 0 |
| |
16 | 0 |
5.3 load reorder buffer memory
5.3.1 PL_RECORDER_BUF_MEM_0/1
Exist two of load reorder buffer memory to duplicate, with the double buffering scheme that realizes using by the rearrangement algorithm.Can utilize one-port memory by adjusting read and write processing pipeline, make in a clock, from the buffering memory, read and write only VCG.
The explanation of adjuster
6 forewords
The VC/LCAS of Orion adjusts functional block and is responsible for the path channels that deflection (de-skew) reconciliation preface belongs to identical virtual concatenation group (VCG).The network differential time-delay of going deflection to pass through compensation different channels accumulation among the DRAM is externally carried out.
The VCT adjuster receives the data of a byte and the control information of this byte in each clock circulation from the VCT analyzer.Data sequence is made up of time intersection (time interleaved) Synchronous Optical Network (HO SPE or LO VT SPE).Between different SPE, do not exist and do not carry out the frame that multi-frame is adjusted.Difference time-delay between them is arbitrarily, and depends on the external network topological structure.
After passing through adjuster, the SPE that belongs to all channels of identical VCG is adjusted by multi-frame.In the VCT regulator output, make the load byte of adjoining of each VCG (different) effective.This is enough to make VCT to separate preface device recovery byte and recovers the VCG load.
Figure 12 shows the various modules in the VCT adjusting module.The VCT adjuster is formed by writing manager module and reading manager module.It also utilizes the information that is produced by configuration information, schedule generation and troubleshooting logic.Write manager and at a time will reach the storage of a byte provisionally on each channel FIFO.After having accumulated the enough bytes that are used for given channel, they send to DRAM with burst form immediately.Read manager and carry out reverse process: it with the burst form reading of data, and at a time sends out before the byte from DRAM, with storage on each channel FIFO.
Adjusting processing itself carries out by reading manager.This is undertaken by selectivity clear channel FIFO, makes all data fifos of given VCG be adjusted.
Whole VCT adjuster utilizes the TDM schedule of free-running operation fully, so that data are moved to the next stage from a stage.All Schedules is followed the same sequence (determining by configuration) of channel, but the data volume that each schedule can be moved as required is with different speed circulations.
Activate which channel and VCG when equally, fault processing unit is determined at any given time.The system of Figure 12 shows system 100, and it has such as the analyzer of MFI analyzer, VCT adjuster 1204, and VCT adjuster 1204 comprises to be write manager 1206 and read manager 1208.System also comprises MCT1210, and it can be positioned at the inside or the outside of system.Output is sent to separates preface device 1212.
7 schedules
Adjust 5 kinds of states of existence in the functional block at VCT, wherein, the schedule of free-running operation is used for being which channel services below the decision.Go out in this purpose, have 4 different schedules (sharing identical schedule for 2 in the stage).Each schedule is followed by disposing definite same sequence.Yet each different schedule utilizes different speed to carry out in proper order with this, produces the different cycles.4 schedules have following column clock cycle period in the VCT adjustment functional block: 1 * 1344,2 * 1344,56 * 1344 and 62 * 1344.
Figure 13 shows schedule and how to be produced by the VCT adjuster.Schedule A (be of a size of X, wherein X is 1,2,56 or 62) has each the counter that is used for 5 conversions VC-4, VC-3, VC-2, VC-12 and VC-11.The VC-4 size conversion is 16, and the VC-3 size conversion is 3, and the VC-2 size conversion is 7, and the VC-12 size conversion is 3, and the VC-11 size conversion is 4.
Every X core clock circulation, the VC-4 counter increases by 1.At 15 o'clock, counter rollover returned 0.Because each VC-4 circulation, the VC-3 counter increases by 1.Similarly, because each VC-3 circulation, it is 1. last that the VC-2 counter increases, and for every VC-2 circulation, VC-11 and VC-12 counter increase by 1.
Other schedule for each is carried out identical mechanism, and the cycle that just is used to upgrade first conversion (VC-4) can change.
By this way, VCT adjusts four schedules that functional block has produced friction speed.At any time, each schedule provides current VC-4, VC-3, VC-2, VC-12 and VC-11 counter.Such information is enough to determine next with processed channel number together in company with channel configuration.
As shown in table 7, channel configuration requires 48 * 9 bits.Each schedule of having nothing for it but duplicates such information to avoid reading conflict.
Table 7: adjust the channel information that requires in the functional block at VCT
8 DRAM tissue and share situation
VCT adjust functional block with 64 byte conversion write with reading of data to/from outside DRAM.Outside DRAM can support the VCT data of 64MB.If require less storage, DRAM can also be configured to only to support 16,32 or the memory of 48MB.Notice that this is the global configuration setting that is used for whole VCT functional block.
| Object | Size | Explanation |
| The |
2 | Distribute to the size of the dram space of VCAT.00-16MB, 01-32MB, 10-48MB and 11-64MB |
Table 8:DRAM dimensional configurations
In each channel FIFO, organize the VCAT data among the DRAM.Such FIFO is up to 1344.The full-size of each FIFO depends on the type of channel and the overall size of VCAT DRAM (16MB-64MB).Each FIFO utilizes among the DRAM fixing position, and it is broken away from the VCT functional block and fixes after resetting.
Continuous read and write is distributed to the mode of different DRAM memory cell, determine the DRAM position that each FIFO uses.Table F shows how to dispose different VC-4 (sts-3) in DRAM, thereby will cause 0 to 3 memory cell to be intersected periodically constantly to the consecutive access of VC-4.
The DRAM memory cell of table F:VCAT FIFO is intersected
The size of each FIFO depends on channel type and whole VCAT DRAM size.Minimum FIFO is corresponding to vt 1.5 channels among the VCAT DRAM of 16MB size, and maximum FIFO is corresponding to the sts-3c channel of the VCAT DRAM of 64MB size.In order to hold so variable FIFO size, the inventor has defined VCAT memory cell (VMU), and it is the basic storage size that can redistribute to different FIFO.
VMU has 4096 or the size of 4KB.VMU can support 64 64 byte conversion from the VCT functional block.When being in the 16MB pattern, vt 1.5 channels are assigned with 3 VMU of DRAM storage, and vt 2 is assigned with 4 VMU, and sts-1 is assigned with 84 VMU, and sts-3c distributes 256 VMU.If VCAT DRAM has more than 16MB, just increase each channel storage pro rata.
Can use set formula to calculate by the position among the employed DRAM of given FIFO.The schedule index and the channel type of this channel use as the input of formula, to calculate the start address of FIFO.The full-size of FIFO only depends on channel type.Following variables A, B, C, D and E are set to be used for the schedule index of given channel:
| Index | Value | Index | Value |
| VC-4 | VC-4：a1a2a3a4(4bits) | VC-3 | VC-3：B(2bits) |
| VC-2 | VC-2：C(3bits) | VC-12 | VC-12：D(2bits) |
| VC-11 | VC-11：E(2bits) |
Table 9: the schedule index that is used for given channel
Utilize schedule index and channel type, table 10 has illustrated the maximum sized formula that is used for calculating storaging unit number, start address and each channel FIFO of DRAM.Be not in these formula, VMU is 4KB, and " S " is the global configuration register in the whole space of explanation VCAT (0-16MB, 1-32MB, 2-48MB, 3-64MB) use.
Table 10: the DRAM that is used for VCAT distributes
Notice no matter whether this space is used for sts-3c, above memory allocation scheme all stays the space of 16KB for each 1MB.
More than calculate the memory cell number produced 2 and 18 storage address (in 64 byte units).
For each channel FIFO, adjusting functional block needs carrier state information:
Table 11: share the state that is used for DRAM FIFO
Pointer is stored in 64 byte units, and is added into channel FIFO base address to obtain actual DRAM memory cell.In the time of in 64 new block of bytes being stored into DRAM, write pointer upgrades by writing manager.When obtaining 64 new byte conversion from DRAM, read pointer upgrades by reading manager.
Read pointer reads by writing manager, to guarantee that FIFO is not filled.Write pointer also reads by reading manager, and FIFO is not a sky with checking.
When FIFO when reading manager and reset, it is set to 1 with at first invalid FIFO position, then, writes the write and read pointer with 0.In case FIFO breaks away from reset mode, write manager and will be at first MFI number of new valid data be write in " MFI " field.Then, it writes DRAM with new 64 byte conversion, upgrades write pointer, and invalid FIFO position is not set.
9 reset, fault and alarm
Adjust functional block and support each channel and each VCG set, two set are all started by writing suitable RX configuration register by software.When channel is in SM set mode, adjusts functional block and can not handle this channel, and will empty any FIFO that belongs to this FIFO.When whole VCG is in reset mode, it will make all path channels be in reset mode.
Adjust functional block and also support each channel and each VCG fault mode.Fault mode is very similar to reset mode, and just this pattern can directly trigger by hardware rather than by software.The channel that is under the fault mode is not handled, and emptied its FIFO.VCG in the fault mode will force all its branch roads to be under the fault mode.Unlike channel in the whole RX functional block of influence and the software reset of VCG, fault mode only influences channel and the VCG that adjusts in the functional block.
In adjusting functional block, also there is each channel alarm of two types.When the alarm that receives from analyzer, write manager and have each channel alert situation.Similarly, when the alarm that receives from MCT, read manager and have each channel alert situation.To describe in next chapters and sections and how detect alarm.
Whether by software " mandate ", the fault scheme is different according to given channel.Authorizing branch road is a kind of carrying or the branch road of wishing the carrying valid data.Unauthorized branch road is a kind ofly not carry valid data (being in LCAS idle situation) but need combine branch road with the LCAS information of handling it with remaining VCG.Because their problem should not influence other mandate branch roads of VCG, so treat unauthorized branch road distinctively.
14 show reset and fault mode how together for authorizing and unauthorized branch road work.VCG resets and channel resets is the configuration state that is write by software.On the other hand, to read and write alarm be internal state by hardware maintenance to each channel.Similarly, VCG fault and channel-failures also are the internal states by hardware maintenance.
Utilize the single logic utilization of any effective schedule to reset and alert situation is determined fault state.
If any authorization channel of VCG makes it read to alarm set, VCG fault position will be set.On the other hand, if without any a channel it is write alarm set among the VCG, VCG fault position just is eliminated so.In order to guarantee to remove the time enough of FIFO,, need to determine the VCG fault state for the minimum of 1344 * 64 core clocks circulation.
When VCG was in fault or reset mode, the branch road of so all it (mandate with unauthorized) will be to their abort situation position.Also will be when channel be in reset mode set channel-failures position.To only reset at channel, corresponding VCG resets and during corresponding VCG fault bit clear, remove authorization channel fault position.The data that enter also must be in the frame initial condition.
For unauthorized branch road, alarm can not cause the VCG fault.On the contrary, channel is read alarm (on the unauthorized branch road) and will be made that branch road enters fault mode.If channel is in reset mode, channel also will enter fault mode.In case be in malfunction, unauthorized channel will be provided with static fault position.
Break away from fault mode for unauthorized branch road, must not write alarm, not reset.Software must be removed rest position, and the beginning that it must received frame.
Following table has been summed up and has been required to keep alarm, resetted and the position of fault state.Notice that the space that is used for reset mode, authority bit and fault rest position is positioned at the RX configuration.
Table 12: adjust the functional block alarm, reset and malfunction
10 write manager
Figure 15 shows another sketch of writing manager.
Write manager and have 1344 main FIFO, one of each channel.Before each FIFO, there are 2 byte section RAM.After all main FIFO, have single 62 byte RAM, its be used for be used as single conversion send to MCT before store byte.
The bytes store that arrives at from CXC is 2 byte memorys corresponding to its channel.The schedule of free-running operation periodically soars the content of 2 byte memorys, inserts among the corresponding main FIFO.Notice that the most of the time will write the data of occupying 2 bytes, but can only be 1 byte or 0 byte sometimes.
Main FIFO is made of one-port memory.Therefore, these FIFO's reads out and writes and cross one another.Write between the circulation to exist at per two and read circulation, otherwise still.Data are changed the into free-running operation schedule full speed running of its corresponding FIFO (not having idle) from 2 byte RAM.New FIFO of per two clock cyclic accesses, and in this clock circulation, insert up to 2 bytes.Per 1344 * 2 these cycles of circulation repeat once.
Similarly, once main FIFO is selected in the circulation of per 62 clocks of the schedule of free-running operation, and its content (62 bytes or still less) is imported among the 62 byte RAM.Amount to the data conversion is counted.This counting and null byte are preplaned in 62 bytes of data, to form the conversion of 64 bytes.Expense also comprises the bit of the fault (AIS) of notifying channel and the parity check bit of protection 1 byte stem.The conversion that table G shows 64 bytes sends to MCT.Per 1344 * 62 these cycles of circulation will repeat once.Such situation is shown in Figure 16.
10.1 alarm and fault state
If given channel receives the data with alarm signal from the analyser function piece, it is provided with channel and writes alert situation.When it stops the receiving alarm data, alert situation is write in removing.
Write alert situation if channel is in, but be not the fault situation, write manager and continue data are write MCT, but these data form by complete 1, activate the alarm position in 64 byte conversion simultaneously.2 bytes and main FIFO are not used, but need not to be cleared (as long as channel is not in the fault mode).Break away from when the channel of not failing and to write when alarm, write manager and continue to write MCT.Although this data failure writes MCT with it and there is no harm.
Therefore and the VCG fault that takes place as shown in next chapters and sections, the alarm position is set in 64 byte conversion unit will finally causes and read to alarm and.The VCG fault also may be resetted or attempted to write completely that the VCG branch road of FIFO causes by VCG.The VCG fault then produces channel-failures at all on its branch road.
If given channel is in malfunction, writes manager and no longer data are write MCT.On the contrary, the time interval that is exclusively used in this channel is used to empty the FIFO of 2 bytes, main FIFO and DRAM FIFO.Abandon the data that advance by the CXC that is used for this channel.Do not give next stage by doing as usual reading of data, empty 2 byte FIFO and main FIFO data passes.By effective FIFO bit of set and set read and write pointer, empty DRAM FIFO.
When branch road breaks away from fault state (it must be positioned at the beginning of frame), the MFI of new frame is write in the stem MFI field.New data transition is sent to MCT, and upgrade write pointer.At last, not set of the invalid bit of FIFO.
11 read manager
Figure 17 shows the structure chart of reading manager.Read manager and have 1344 main FIFO, one is used for each channel, and each FIFO has the specification of 120 bytes.After each FIFO, there are 2 byte section RAM.Before main FIFO, there are single 62 byte RAM, it is used to store the byte that receives from single MCT conversion, simultaneously, these bytes just is being written into main FIFO.
A main FIFO is selected in the per 56 clocks circulation of the schedule of free-running operation.If main FIFO level is carried out read request for this FIFO to MCT so less than 58 bytes.When carrying out read request, 62 bytes (or being less than) write this FIFO the most at last.Read request cycle, per 56 * 1344 clocks circulation repeated once.Because each MCT conversion carrying at least 56 byte, this has guaranteed that as long as have data, FIFO in DRAM can all not be empty.
Read manager and be maintained as the FIFO request that the MCT that also do not receive data carries out.When newly asking, new clauses and subclauses are placed in the do not work afterbody of FIFO of (request-on-the-fly) of this request.These clauses and subclauses comprise the channel id of request.When receiving new data slice from MCT, the do not work clauses and subclauses of stem of FIFO of recovery request.Channel id on the clauses and subclauses shows the FIFO that data belong to.
The do not work maximum specification of FIFO of this request is 16 clauses and subclauses.If FIFO was once full, it is indicating the DRAM bandwidth problem.This is not catastrophic incident.Read manager and cross current time slot (not carrying out new request) simply, and keep normal running at this time slot.If such situation of overflowing is interim, read the manager bandwidth of compensating missing the most at last.
If the request FIFO situation of overflowing takes place too frequently, DRAMFIFO overflows the most at last and adjustment process will be failed.This shows that the DRAM bandwidth is inadequate.In order to detect this situation, read hold the record 32 state counters of the overall situation of number of times of manager, detect overflow condition or do not detect unripe MCT.No matter the count value timing changing all passes through (maskable) and interrupts informing CPU.
Reading manager can also be up to 16 62 byte buffer with the data burst (burst) of storage from MCT.If write become owner of FIFO speed faster than the speed that is used for per two cycles 2 bytes, can reduce this buffering potentially.
Main FIFO is made of one-port memory.Therefore, these FIFO's reads and writes and cross one another.Write between the circulation to exist at per two and read circulation, otherwise still.
By send out data from corresponding main FIFO, another free-running operation schedule is periodically filled the content of 2 byte memorys.Per 2 circulation primary are carried out 2 bytes (only reading cycle period).Per 1344 * 2 these cycles of circulation repeat once.
Another free-running operation schedule extracts data from 2 byte section RAM, to send to Xie Xuqi.Can every clock circulation from different RAM, read a byte.Per 1344 these cycles of circulation repeat once.Chapters and sections 11.2 have been described the read states machine and how to have been determined whether to read byte.
11.1 alarm and fault state
Reading manager detects and reads alarm by observe alarm position in the 64 byte delivery units read out from MCT.
Read alarm if detect on authorization channel, it will make whole VCG enter malfunction so.Then, can make each branch road of this VCG enter fault mode like this.Read alarm if detect on unauthorized channel, it only makes this channel enter malfunction.
When channel is in fault mode, read not reading of data from MCT of manager.In being exclusively used in the time slot of this channel, reading manager and empty corresponding main FIFO and 2 byte FIFO simply.On the interface of Xie Xuqi, it sends one complete 1 byte and alarm identifier.
When channel was broken away from fault mode, it checked to observe whether removed the DRAMFIFO significance bit.In case the removing significance bit, it reads the stem MFI value that is used for this channel.It can continue from MCT reading of data now and carry out with normal running.
11.2 read states machine
Following state machine has been described for the adjustment of all branch roads that obtain VCG by reading the operation that manager is carried out.For each channel, whether the byte that the state machine decision is positioned at 2 byte FIFO stems should keep thereon, whether should read and abandon or whether read and send to Xie Xuqi.The appropriate combination of these 3 kinds of operations is with all branch roads of the identical VCG of byte adjustment (byte-align).
Table 13 shows the desired additivity into each VCG.Each VCG state comprises the information of describing given VCG situation when attempting to adjust self.Adjusting MFI (AMFI) is target MFI, and whole VCG attempts and will himself be adjusted to target MFI.The branch road of adjusting has himself the MFI that the AMFI of VCG is given in locking.The adjustment branch road of SOF bit representation VCG is faced with the beginning of frame.There is at least one branch road of the group (after a while when the DRAIN situation, to its definition) of attempting to point out to adjust branch road in the DRAM bit representation.At least one of last STALL bit representation VCG adjusted branch road and had sky FIFO.This just means that this whole VCG need wait for a such branch road.
Table 13: each additional VCG state of reading the requirement of manager state machine
Notice that each type of VCG (VC-4, VC-3, VC-2 and VC-11) has different schedule cycle periods.The per 16 core clock circulation circulation primary of VC-4 schedule, the per 48 core clock circulation circulation primary of VC-3 schedule, the per 1008 circulation circulation primary of VC-12 schedule, and the per 1344 circulation circulation primary of VC-11 schedule.Therefore, for each of 4 VCG types, need one group of pointer represent 3 duplicate which be reading and writing or removing.
Table 14 shows desired each the additional channel conditions of this state machine.
Table 14: read desired each the additional channel status of manager state machine
Figure 19 shows and reads the senior state figure that manager is used for carrying out the algorithm of adjustment.When not being in the channel-failures pattern, each channel can be in a kind of in 4 kinds of states: INIT, WAIT, DRAIN and GO.
At the INIT state, channel is waited for and obtain the MFI value from stem MFI field.Whether in case obtain current MFI value, channel can be judged its whether in the front portion of adjusting MFI too (wait state) far away, perhaps its in the back of adjusting MFI too (DRAIN state) far away.In the WAIT state, FIFO never is cleared, and in the DRAIN state, FIFO always is cleared, and abandons data.When channel MFI with adjust MFI when identical, it enters the GO state, wherein, it is just with other branch roads reading of data from FIFO of the VCG that is in the GO state.Adjust the branch road that all are in the GO state.Each channel status bit (and interruption) will inform whether software has adjusted given channel.
Following false code has been explained in more detail and has been read the manager algorithm.Subscripts_write, _ read and _ which that 3 every VCG duplicate clear be used for representing just using.
1. inspection channel-failures
If channel falure bit is set
Go to step 7
If channel falure bit is released
Set state to INIT
2. initialization and read action
If(state＝＝INIT)
If(DRAM FIFO invald＝＝1)or(SRAM FIFO is ampty)
Stay In INIT
Else
Get CMFI from Head MFI fleld
If(AMFI_VALID＝＝0)
Stay in INIT
Else If(CMFI<＝AMFI)
Set state to DRAIN
Else If(CMFI>AMFI)
Set state to WAIT
If(state＝＝DRAIN)
If(CMFI＝＝AMFI)and(VCG_NSOF_read＝＝0)and(channel is in SOF)
Set state to GO
Day se If (SRAM FIFO Is non-empty〉and (VCG_STALL_read==0)
Flead byte from Read Mgr FIFO and throw it away
If(state＝＝WAIT)
If(CMFI＝＝AMFI)and(VCG_NSOF_read＝0)
If(VCG_STALL_read＝0)and(VCG_DRAIN_read＝＝0)
Read byte from Read Mgr FIFO and send to De-Sequencer
Set state to GO
If(state＝＝GO)
If(VCG_STALL_read＝＝0)and[(VCG_NSOF_read＝＝1)or(VCG_DRAIN_read＝＝0))
Flead byte from Read Mgr FIFO and send to De-Sequencer
If(state＝＝IDLE)
Transmit“Fail/Res to De-Sequencer
4. write action (utilizing byte count and the FIFO level after step 3, upgraded)
If(state＝＝DRAIN)
VCG_DRAIN_write＝1
If(state＝＝GO)and(SRAM FIFO is empty)
VCG_STALL_write＝1
If[(state＝＝GO)and SRAM FIFO head is NOTSOF
VCG_NSOF_write＝1
5. upgrade CMFI (utilizing byte count and the FIFO level upgraded after the step 3)
6. upgrade AMFI (utilizing the CMFI value of calculating in the step 5)
If(state＝＝INIT)and(DRAM FIFO invalid＝＝0)and(AMFI_VALID＝＝0)and(SRAM FIFO isnon-empty)
AMFI＝CMFI
AMFI_VALID＝1
If state＝GO
AMFI＝max(CMFI，AMFI)
AMFI_VALID＝1
7. remove action
VCG_DRAIN_clear＝0
VCG_STALL_dear＝0
VCG_NSOF_clear＝0
12 optimize
12.1 write main FIFOs
Figure 20 shows how to distribute main FIFO.
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| US60/645,841 | 2005-01-21 | ||
| PCT/US2006/002144 WO2006081150A2 (en) | 2005-01-21 | 2006-01-20 | System and method for performing concatenation of diversely routed channels |
| US11/336,188 | 2006-01-20 | ||
| US11/336,188 US7684426B2 (en) | 2005-01-21 | 2006-01-20 | System and method for performing concatentation of diversely routed channels |
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| CN101507145B CN101507145B (en) | 2013-05-29 |
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| CN2006800054611A Expired - Fee Related CN101507145B (en) | 2005-01-21 | 2006-01-20 | System and method for performing concatenation of different routing channels |
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| EP (1) | EP1913599A2 (en) |
| JP (1) | JP2008538456A (en) |
| CN (1) | CN101507145B (en) |
| TW (1) | TWI487351B (en) |
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2006
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| CN114207721B (en) * | 2019-08-05 | 2023-09-05 | 赛普拉斯半导体公司 | Memory controller for non-interfering access to non-volatile memory by different hosts and related systems and methods |
| CN111221575A (en) * | 2019-12-30 | 2020-06-02 | 核芯互联科技(青岛)有限公司 | Register renaming method and system for out-of-order high-performance processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008538456A (en) | 2008-10-23 |
| EP1913599A2 (en) | 2008-04-23 |
| TW200644540A (en) | 2006-12-16 |
| WO2006081150A9 (en) | 2008-01-17 |
| US9461942B2 (en) | 2016-10-04 |
| US8503470B2 (en) | 2013-08-06 |
| US7684426B2 (en) | 2010-03-23 |
| CN101507145B (en) | 2013-05-29 |
| WO2006081150A2 (en) | 2006-08-03 |
| US20130315258A1 (en) | 2013-11-28 |
| TWI487351B (en) | 2015-06-01 |
| WO2006081150A8 (en) | 2007-07-12 |
| WO2006081150A3 (en) | 2009-04-09 |
| US20060187715A1 (en) | 2006-08-24 |
| US20100254709A1 (en) | 2010-10-07 |
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