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CN101500367B - Signal processing circuit and method - Google Patents

Signal processing circuit and method Download PDF

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Publication number
CN101500367B
CN101500367B CN200810004770A CN200810004770A CN101500367B CN 101500367 B CN101500367 B CN 101500367B CN 200810004770 A CN200810004770 A CN 200810004770A CN 200810004770 A CN200810004770 A CN 200810004770A CN 101500367 B CN101500367 B CN 101500367B
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frequency
synchronization
pulse
synchronization signal
signal
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CN101500367A (en
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李庭吉
刘温良
陈俊雄
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Signal Electronics Co ltd
Holtek Semiconductor Inc
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Signal Electronics Co ltd
Holtek Semiconductor Inc
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Abstract

一种信号处理电路及方法，所述方法包括下列步骤：当一第一同步信号的一同步频率在一频率范围之外时，产生具有一选择频率的一第二同步信号，其中选择频率在频率范围之内；当同步频率在频率范围之内时，在第一同步信号的一下一预定脉冲的一预定上升缘时间，产生一第二同步信号中对应于该下一预定脉冲的一第一脉冲的上升缘；及，当同步频率在该频率范围之内时，根据在预定上升缘时间之后且在一第一时间之前该下一预定脉冲是否出现的一侦测结果，产生第一脉冲的下降缘。藉由该电路和方法可消除液晶显示器的画面闪烁现象。

Figure 200810004770

A signal processing circuit and method, the method comprising the following steps: when a synchronization frequency of a first synchronization signal is outside a frequency range, a second synchronization signal having a selected frequency is generated, wherein the selected frequency is within the frequency range; when the synchronization frequency is within the frequency range, at a predetermined rising edge time of a next predetermined pulse of the first synchronization signal, a rising edge of a first pulse corresponding to the next predetermined pulse is generated in a second synchronization signal; and, when the synchronization frequency is within the frequency range, a falling edge of the first pulse is generated according to a detection result of whether the next predetermined pulse appears after the predetermined rising edge time and before a first time. The circuit and method can eliminate the screen flickering phenomenon of a liquid crystal display.

Figure 200810004770

Description

Signal processing circuit and method
Technical field
This case is about a kind of signal processing circuit and method, particularly about a kind of circuit and method that is used for suppressing the water ripple phenomenon of cold cathode fluorescent lamp pipe.
Background technology
Generally when utilizing the cold cathode fluorescent lamp pipe to arrange in pairs or groups the panel of LCD (LCD); Because the cold cathode fluorescent lamp pipe can cause the fluctuation of the accurate position of ground connection (GND) in the moment of lighting; If when running into synchronized again; Can cause the current potential of LCD unstable, so be easy to generate the phenomenon of ripples line.
Synchronizing signal is that a kind of control signal also is a kind of triggering signal; It possibly be a pulse wave signal; Also possibly be a kind of sine wave or irregular pulse wave signal; As long as can the device of institute's desire control be reached the unanimity of frequency and phase place, the device of being controlled can be changed by predetermined sequential, this kind control signal is synchronizing signal.
In the known technology; The method of avoiding this water ripple phenomenon is with the some modulation frequency of cold cathode fluorescent lamp pipe and the synchronized of LCD; Though and such processing mode has solved the problem of ripples lines by the illusion that causes vision, the another one of but having derived problem; Promptly when inter-process, the synchronizing signal of part LCD control integrated circuit can postpone a pulse.Shown in Fig. 1 (a), it is for the synchronous signal that is used to drive cold cathode fluorescent lamp pipe drive integrated circult of liquid crystal display television; The display frequency of liquid crystal display television figure field (Field) is 60Hz (or 50Hz), and the some modulation frequency of cold cathode fluorescent lamp pipe is 48.5KHz, wherein puts modulation frequency by synchronizing signal V SYNFrequency control; Because it is the pulse of 48.5KHz that the pairing one-period of frequency 60Hz (or 50Hz) can't just in time hold an integer frequency, therefore, the synchronizing signal that part LCD control integrated circuit is produced can postpone a pulse.
See also Fig. 1 (b), it is the waveform sketch map of the tube current of the synchronizing signal cold cathode fluorescent lamp pipe pairing with it of having used LCD.As shown in the figure, as synchronizing signal V SYNCPulse when omission being arranged because of delay, this omission pulse the some modulating signal of corresponding cold cathode fluorescent lamp pipe also disappear, cause tube voltage to descend and current I CCFLReduce, and then cause the situation of film flicker.
As how effectively solve because of film flicker phenomenon that pulse caused of sync signal delay with easy circuit, be the mainspring of development this case.
Therefore, this case inventor is in view of the above-mentioned disappearance of having used technology, and this case " signal processing circuit and method " is created in the research that warp is concentrated, and a spirit of working with perseverance eventually.
Summary of the invention
One purpose of this case is for proposing a kind of signal processing circuit and method; Utilize one first synchronizing signal that is received to produce one second synchronizing signal that drives a cold cathode fluorescent lamp pipe; Wherein second synchronizing signal is supplied the pulse that first synchronizing signal is lacked, to eliminate the film flicker phenomenon of LCD.
First of this case is contemplated that and proposes a kind of signal processing method; When it comprises the following steps: that a synchronizing frequency when one first synchronizing signal is outside a frequency range; Generation has one second synchronizing signal of a selection frequency, wherein selects frequency within frequency range; When synchronizing frequency is within frequency range,, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse in the predetermined rising edge time of next predetermined pulse of first synchronizing signal; And when synchronizing frequency was within this frequency range, the detecting result according to whether this next predetermined pulse occurs after the time and before a very first time at predetermined rising edge produced the falling edge of first pulse.
Second of this case is contemplated that and proposes a kind of signal processing circuit that it comprises an external trigger interruption generating device, a timer, a programmable pulse generator and a control unit.Whether the edge of a pulse of external trigger interruption generating device detecting one first synchronizing signal that it received occurs to judge first synchronizing signal.The programmable pulse generator produces one second synchronizing signal according to the preparatory adjusted value that removes that it had.Control unit is coupled in external trigger interruption generating device, timer and programmable pulse generator; Wherein control unit utilizes external trigger interruption generating device and timer to arrive predetermined rising edge time of next predetermined pulse of any first synchronizing signal, and control programmable pulse generator produces in second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse.
Another of this case is contemplated that and proposes a kind of signal processing method, comprise the following steps:
In the predetermined rising edge time of next predetermined pulse of one first synchronizing signal, produce in one second synchronizing signal rising edge corresponding to one first pulse of this next predetermined pulse; And
According to the detecting result that whether this next predetermined pulse occurs after the time and before a very first time at this predetermined rising edge; Produce the falling edge of this first pulse; Wherein when a synchronizing frequency of this first synchronizing signal is outside a frequency range; Generation has one and selects this second synchronizing signal of frequency, and should select frequency within this frequency range.
Signal processing circuit of the present invention and method can be eliminated the film flicker phenomenon of LCD.
This case must be by the detailed description of drawings as hereinafter, with more deep understanding:
Description of drawings
Fig. 1 (a): with the synchronous signal that is used to drive cold cathode fluorescent lamp pipe drive integrated circult of liquid crystal display television;
Fig. 1 (b): the waveform sketch map of tube current of having used the synchronizing signal cold cathode fluorescent lamp pipe pairing of LCD with it;
Fig. 2: the block schematic diagram of the application system of this case first signal processing circuit that embodiment carries;
Fig. 3 (a): this case first embodiment carries the waveform sketch map that next predetermined pulse in the signal processing circuit has appearance;
Fig. 3 (b): this case first embodiment carries next predetermined pulse in the signal processing circuit does not have the waveform sketch map that occurs;
Fig. 4: the block schematic diagram of the application system of this case second signal processing circuit that embodiment carries; And
Fig. 5: the schematic flow diagram of this case second signal processing method that embodiment carries.
Embodiment
See also Fig. 2, it is the block schematic diagram of the application system of this case first signal processing circuit that embodiment puies forward.As shown in the figure, the application system 30 of signal processing circuit comprises a control integrated circuit 31, a signal processing circuit 32, a cold cathode fluorescent lamp pipe 331, and the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 of a LCD.
The synchronizing signal V that control integrated circuit 31 is produced S1In order to the control LCD picture show synchronously, and as an advance signal of control cold cathode fluorescent lamp pipe 331.Signal processing circuit 32 receives synchronizing signal V S1And adjustment synchronizing signal V S1, to produce synchronizing signal V S2The drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 receives synchronizing signal V S2, light the tube voltage signal V of cold cathode fluorescent lamp pipe 331 with generation CCFL, synchronizing signal V wherein S2Frequency as some modulation frequencies of cold cathode fluorescent lamp pipe 331.In addition, synchronizing signal V S2The one drive integrated circult (not shown) that also can offer a back light source in LED is used.
Signal processing circuit 32 comprises an external trigger interruption generating device 322, a timer 323, a programmable pulse generator 324 and a control unit 321.Signal processing circuit 32 can be, for example, and a microcontroller (MCU) or a special purpose integrated circuit (ASIC).External trigger interruption generating device 322 receives synchronizing signal V S1And detecting synchronizing signal V S1The edge, with the triggering that produces disruptive and offer control unit 321, synchronizing signal V wherein S1Have series of pulses, and design external trigger interruption generating device 322 makes it can detect synchronizing signal V S1Rising edge or falling edge, or one of them of rising edge and falling edge.
Programmable pulse generator 324 produces synchronizing signal V according to the preparatory adjusted value that removes that it had S2, wherein remove the adjusted value control synchronizing signal V that produces in advance S2The width of middle pulse.Control unit 321 is coupled in external trigger interruption generating device 322, timer 323 and programmable pulse generator 324, and the running of control external trigger interruption generating device 322, timer 323 and programmable pulse generator 324.When signal processing circuit 32 is microcontroller, represent the running of control unit 321 by a firmware, firmware is with the running of commands for controlling external trigger interruption generating device 322, timer 323 and programmable pulse generator 324.
The synchronizing signal V that external trigger interruption generating device 322 is received S1Comprise series of pulses, and synchronizing signal V S1Next predetermined pulse do not know whether really can occur.But no matter synchronizing signal V S1Next predetermined pulse whether occur, signal processing circuit 32 all will be guaranteed the synchronizing signal V that produces S2In can occur corresponding to one first pulse of next predetermined pulse.
See also Fig. 3 (a) and Fig. 3 (b); Fig. 3 (a) carries the waveform sketch map that next predetermined pulse in the signal processing circuit has appearance for this case first embodiment, and Fig. 3 (b) carries the waveform sketch map that next predetermined pulse in the signal processing circuit does not have appearance for this case first embodiment.Control unit 321 utilizes external trigger interruption generating device 322 and timer 323 statistics synchronizing signal V S1The cycle of one group of preceding pulse before next predetermined pulse NPS1 is to obtain synchronizing signal V S1A typical pulse width, a synchronizing cycle and a synchronizing frequency, wherein synchronizing frequency is the inverse of synchronizing cycle, and the predetermined rising edge time T 1 of next predetermined pulse NPS1 is synchronizing signal V S2One of a rising edge time and the summation of synchronizing cycle of final pulse, or be this sum total near.And the predetermined rising edge time T 1 of next predetermined pulse NPS1 also can be by synchronizing signal V S1One of a rising edge time or falling edge time, typical pulse width and the synchronizing cycle of final pulse calculate and get.
Control unit 321 utilizes external trigger interruption generating device 322 and timer 323 to arrive synchronizing signal V S1The predetermined rising edge time T 1 of next predetermined pulse NPS1, and control programmable pulse generator 324 produces synchronizing signal V S2In corresponding to the rising edge of the first pulse TPS1 of next predetermined pulse NPS1.
Whether control unit 321 utilizes external trigger interruption generating device 322 and timer 323 after predetermined rising edge time T 1 and before the very first time T2, to detect next predetermined pulse NPS1 to occur; And the detecting result who whether occurs according to next predetermined pulse NPS1; Utilize programmable pulse generator 324 to produce the falling edge of the first pulse TPS1; Wherein very first time T2 adds for 1/2nd synchronizing cycle for predetermined rising edge time T 1; Or very first time T2 adds the multiplying power of 1/2nd synchronizing cycle for predetermined rising edge time T 1, and usually this multiplying power near 1.
As synchronizing signal V S1When the falling edge of next predetermined pulse NPS1 occurring before the very first time T2, control unit 321 the falling edge of next predetermined pulse NPS1 the time after at once or a Preset Time afterwards, utilize programmable pulse generator 324 generation synchronizing signal V S2In the falling edge of the first pulse TPS1.As synchronizing signal V S1When the falling edge of next predetermined pulse NPS1 not occurring before the very first time T2, control unit 321 can be very first time T2 after at once or a Preset Time afterwards, generation synchronizing signal V S2In the falling edge of the first pulse TPS1.And control unit 321 is by the falling edge time of controlling the first pulse TPS1 in advance except that adjusted value of adjustment programmable pulse generator 324, to adjust the width of the first pulse TPS1.
See also Fig. 4, it is the block schematic diagram of the application system of this case second signal processing circuit that embodiment puies forward.The application system 40 of Fig. 4 is the expansion of Fig. 2 application system 30.As shown in Figure 4, the application system 40 of signal processing circuit comprises a control integrated circuit 31, a signal processing circuit 42, a cold cathode fluorescent lamp pipe 331, and the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331 of a LCD.
Signal processing circuit 42 comprises an external trigger interruption generating device 322, a timer 323, a programmable pulse generator 324, a programmable prescaler 325 and a control unit 321.Programmable prescaler 325 is coupled in control unit 321, according to the frequency divider value that it had, produces a triggering signal V who is supplied to programmable pulse generator 324 S3, wherein frequency divider value is controlled the triggering signal V that produces S3Frequency.
Control unit 321 utilizes external trigger interruption generating device 322 and timer 323 statistics synchronizing signal V S1The cycle of one group of preceding pulse before next predetermined pulse NPS1 is to obtain synchronizing signal V S1A typical pulse width, a synchronizing cycle and a synchronizing frequency, wherein synchronizing frequency is the inverse of synchronizing cycle, and synchronizing signal V S1The predetermined rising edge time T 1 of next predetermined pulse NPS1 be synchronizing signal V S2A rising edge time and the summation of synchronizing cycle of a final pulse, or be this sum total near.And the predetermined rising edge time T 1 of next predetermined pulse NPS1 also can be by synchronizing signal V S1A rising edge time or falling edge time, typical pulse width and the synchronizing cycle of a final pulse calculate and get.In addition, when signal processing circuit 42 was a microcontroller, the work of control unit 321 can be carried out by the firmware in the signal processing circuit 42.
The circuit that application drawing 4 then is described is to carry out method for processing signals.See also Fig. 5, it is for the schematic flow diagram of this case second signal processing method that embodiment carries.In step 502, control unit 321 obtains synchronizing signal V S1Synchronizing frequency, and check that arbitrary synchronizing frequency is whether in a frequency range (for example outside the 40kHz～50kHz).
In step 504, the synchronizing signal V that is obtained when control unit 321 S1Synchronizing frequency outside frequency range the time, expression synchronizing signal V S1Synchronizing frequency be abnormal.So control unit 321 control programmable prescaler 325 make programmable prescaler 325 produce the triggering signal V with a selection frequency S3, wherein select frequency in frequency range (for example between the 40kHz～50kHz), and triggering signal V S3Comprise series of pulses and offer programmable pulse generator 324, and the duty ratio of this series of pulses is 50% usually.Programmable pulse generator 324 is according to triggering signal V S3Generation has the synchronizing signal V that selects frequency S2, and it is offered the drive integrated circult 332 of cold cathode fluorescent lamp pipe 331, wherein control unit 321 removes adjusted value in advance by what set programmable pulse generator 324, with control synchronizing signal V S2The width of pulse, and synchronizing signal V S2Pulse can have 50% duty ratio, or have adjustable pulse duration.
In step 506, the synchronizing signal V that is obtained when control unit 321 S1Synchronizing frequency within frequency range the time, control unit 321 utilizes timer 323 and programmable pulse generator 324, makes programmable pulse generator 324 at synchronizing signal V S1The predetermined rising edge time T 1 of next predetermined pulse NPS1 produce synchronizing signal V S2The rising edge of the first pulse TPS1, wherein the first pulse TPS1 is corresponding to next predetermined pulse NPS1.
In step 508; Whether the falling edge that control unit 321 utilizes external trigger interruption generating device 322 and timer 323 after predetermined rising edge time T 1 and before a very first time T2, to detect next predetermined pulse NPS1 occurs; Wherein very first time T2 adds for 1/2nd synchronizing cycle for predetermined rising edge time T 1; Or very first time T2 adds the multiplying power of 1/2nd synchronizing cycle for predetermined rising edge time T 1, and usually this multiplying power near 1.
In step 510, as synchronizing signal V S1When after predetermined rising edge time T 1 and before very first time T2, the falling edge of next predetermined pulse NPS1 occurring; Control unit 321 the falling edge of next predetermined pulse NPS1 after the time at once or a Preset Time afterwards, utilize programmable pulse generator 324 to produce synchronizing signal V S2In the falling edge of the first pulse TPS1.
In step 512, as synchronizing signal V S1When after predetermined rising edge time T 1 and before very first time T2, the falling edge of next predetermined pulse NPS1 not occurring, control unit 321 after very first time T2 at once or a Preset Time afterwards, generation synchronizing signal V S2In the falling edge of the first pulse TPS1.And control unit 321 removing in advance the falling edge time that adjusted value is controlled the first pulse TPS1 by adjustment programmable pulse generator 324; To adjust the width of the first pulse TPS1; So, the film flicker phenomenon that pulse produced of omitting but optimization ground is eliminated.
In sum, signal processing circuit of this case and method can reach the effect that the invention conception sets really.Just, the above is merely the preferred embodiment of this case, is familiar with the personage of this case skill such as, and the equivalence of being done according to this case spirit in the whence is modified or changed, and all should be covered by in the following claim scope.

Claims (9)

1.一种信号处理方法，包括下列步骤：1. A signal processing method, comprising the following steps: 当一第一同步信号的一同步频率在一频率范围之外时，产生具有一选择频率的一第二同步信号，其中该选择频率在该频率范围之内；generating a second synchronization signal having a selected frequency when a synchronization frequency of a first synchronization signal is outside a frequency range, wherein the selected frequency is within the frequency range; 当该同步频率在该频率范围之内时，在该第一同步信号的一下一预定脉沖的一预定上升缘时间，产生一第二同步信号中对应于该下一预定脉冲的一第一脉冲的上升缘；及When the synchronization frequency is within the frequency range, at a predetermined rising edge time of a next predetermined pulse of the first synchronization signal, a second synchronization signal corresponding to a first pulse of the next predetermined pulse is generated rising edge; and 当该同步频率在该频率范围之内时，根据在该预定上升缘时间之后且在一第一时间之前，该下一预定脉冲是否出现的一侦测结果，产生该第一脉冲的下降缘。When the synchronization frequency is within the frequency range, the falling edge of the first pulse is generated according to a detection result of whether the next predetermined pulse occurs after the predetermined rising edge time and before a first time. 2.如权利要求1的信号处理方法，更包括下列步骤：2. The signal processing method as claimed in claim 1, further comprising the following steps: 藉由统计该第一同步信号在该下一预定脉冲之前的一组前置脉冲的周期，获得一同步周期及该同步周期倒数的该同步频率，其中该预定上升缘时间为该第二同步信号的一最后脉冲的一上升缘时间与该同步周期的总和。Obtain a synchronization period and the synchronization frequency of the reciprocal of the synchronization period by counting the period of a group of pre-pulses before the next predetermined pulse of the first synchronization signal, wherein the predetermined rising edge time is the second synchronization signal The sum of a rising edge time of a last pulse and the sync period. 3.如权利要求1的信号处理方法，更包括下列步骤：3. The signal processing method as claimed in claim 1, further comprising the following steps: 当该第一同步信号的该同步频率在该频率范围之外时，调整该第二同步信号的脉冲宽度；及adjusting the pulse width of the second synchronization signal when the synchronization frequency of the first synchronization signal is outside the frequency range; and 当该第一同步信号的该同步频率在该频率范围之内时，调整该第一脉冲的脉冲宽度。When the synchronization frequency of the first synchronization signal is within the frequency range, the pulse width of the first pulse is adjusted. 4.如权利要求1的信号处理方法，其中：4. The signal processing method as claimed in claim 1, wherein: 该第一时间为该预定上升缘时间加上二分之一的一同步周期，其中该同步周期为该同步频率的一倒数，而该第一时间为该预定上升缘时间加上二分之一的该同步周期的一倍率；及/或The first time is the predetermined rising edge time plus a half of a synchronization cycle, wherein the synchronization cycle is a reciprocal of the synchronization frequency, and the first time is the predetermined rising edge time plus one half a multiple of the synchronization period; and/or 在该第一时间之前该第一同步信号出现该下一预定脉冲的下降缘时，该第一脉冲的下降缘时间在该下一预定脉冲的下降缘时间后的一预设时间。When the falling edge of the next predetermined pulse occurs on the first synchronization signal before the first time, the falling edge time of the first pulse is a preset time after the falling edge time of the next predetermined pulse. 5.如权利要求1的信号处理方法，其中：5. The signal processing method as claimed in claim 1, wherein: 在该第一时间之前该第一同步信号没有出现该下一预定脉冲的下降缘时，该第一脉冲的下降缘时间在该第一时间后的一预设时间；及/或When the falling edge of the next predetermined pulse does not appear on the first synchronization signal before the first time, the falling edge time of the first pulse is a predetermined time after the first time; and/or 该第一同步信号由一液晶显示器的一控制集成电路所提供。The first synchronization signal is provided by a control integrated circuit of a liquid crystal display. 6.如权利要求1的信号处理方法，其中：6. The signal processing method as claimed in claim 1, wherein: 该第二同步信号提供给一冷阴极萤光灯管的一驱动集成电路，且该第二同步信号的频率作为该冷阴极萤光灯管的一点灯频率；及/或The second synchronization signal is provided to a driver integrated circuit of a cold cathode fluorescent lamp, and the frequency of the second synchronization signal is used as the lighting frequency of the cold cathode fluorescent lamp; and/or 该第二同步信号提供给一发光二极管背光源的一驱动集成电路。The second synchronous signal is provided to a driving integrated circuit of an LED backlight source. 7.如权利要求1的信号处理方法，其中：7. The signal processing method as claimed in claim 1, wherein: 该方法由一微控制器所执行；The method is performed by a microcontroller; 该微控制器包括至少一固件、一外部触发中断产生器、一可编程脉冲产生器与一计时器，其中该固件控制该外部触发中断产生器、该可编程脉冲产生器与该计时器的运作；The microcontroller includes at least one firmware, an external trigger interrupt generator, a programmable pulse generator and a timer, wherein the firmware controls the operation of the external trigger interrupt generator, the programmable pulse generator and the timer ; 该固件利用接收该第一同步信号，且利用该外部触发中断产生器与该计时器获得该第一同步信号的该同步频率；The firmware obtains the synchronization frequency of the first synchronization signal by receiving the first synchronization signal, and using the external trigger interrupt generator and the timer; 当该第一同步信号的该同步频率在该频率范围之外时，该可编程脉冲产生器产生具有该选择频率的一触发信号以产生该第二同步信号；when the synchronization frequency of the first synchronization signal is outside the frequency range, the programmable pulse generator generates a trigger signal with the selected frequency to generate the second synchronization signal; 当该第一同步信号的该同步频率在该频率范围之外时，该固件更设定该可编程脉冲产生器的一预除调整值，以控制该第二同步信号的脉冲的宽度；When the synchronization frequency of the first synchronization signal is outside the frequency range, the firmware further sets a predivision adjustment value of the programmable pulse generator to control the pulse width of the second synchronization signal; 当该同步频率在该频率范围之内时，该固件利用该计时器与该可编程脉冲产生器，使该可编程脉冲产生器在该预定上升缘时间产生该第二同步信号的该第一脉冲的上升缘；及When the synchronization frequency is within the frequency range, the firmware uses the timer and the programmable pulse generator to make the programmable pulse generator generate the first pulse of the second synchronization signal at the predetermined rising edge time the rising edge of ; and 当该同步频率在该频率范围之内时，该固件利用该侦测结果、该计时器与该可编程脉冲产生器，使该可编程脉冲产生器产生该第二同步信号的该第一脉冲的下降缘。When the synchronization frequency is within the frequency range, the firmware uses the detection result, the timer and the programmable pulse generator to make the programmable pulse generator generate the first pulse of the second synchronization signal falling edge. 8.如权利要求1的信号处理方法，其中：8. The signal processing method as claimed in claim 1, wherein: 该方法由一微控制器所执行；The method is performed by a microcontroller; 该微控制器包括至少一固件、一外部触发中断产生器、一可编程除频器、一可编程脉冲产生器与一计时器，其中该固件控制该外部触发中断产生器、该可编程除频器、该可编程脉冲产生器与该计时器的运作；The microcontroller includes at least one firmware, an external trigger interrupt generator, a programmable frequency divider, a programmable pulse generator and a timer, wherein the firmware controls the external trigger interrupt generator, the programmable frequency divider operation of the timer, the programmable pulse generator and the timer; 该固件利用接收该第一同步信号，且利用该外部触发中断产生器与该计时器获得该第一同步信号的该同步频率；The firmware obtains the synchronization frequency of the first synchronization signal by receiving the first synchronization signal, and using the external trigger interrupt generator and the timer; 当该第一同步信号的该同步频率在该频率范围之外时，该可编程除频器产生具有该选择频率的一触发信号，且该可编程脉冲产生器接收该触发信号以产生该第二同步信号；When the synchronization frequency of the first synchronization signal is outside the frequency range, the programmable frequency divider generates a trigger signal with the selected frequency, and the programmable pulse generator receives the trigger signal to generate the second synchronization signal; 当该第一同步信号的该同步频率在该频率范围之外时，该固件更设定该可编程脉冲产生器的一预除调整值，以控制该第二同步信号的脉冲的宽度；When the synchronization frequency of the first synchronization signal is outside the frequency range, the firmware further sets a predivision adjustment value of the programmable pulse generator to control the pulse width of the second synchronization signal; 当该同步频率在该频率范围之内时，该固件利用该计时器与该可编程脉沖产生器，使该可编程脉冲产生器在该预定上升缘时间产生该第二同步信号的该第一脉冲的上升缘；及When the synchronization frequency is within the frequency range, the firmware uses the timer and the programmable pulse generator to make the programmable pulse generator generate the first pulse of the second synchronization signal at the predetermined rising edge time the rising edge of ; and 当该同步频率在该频率范围之内时，该固件利用该侦测结果、该计时器与该可编程脉冲产生器，使该可编程脉冲产生器产生该第二同步信号的该第一脉冲的下降缘。When the synchronization frequency is within the frequency range, the firmware uses the detection result, the timer and the programmable pulse generator to make the programmable pulse generator generate the first pulse of the second synchronization signal falling edge. 9.如权利要求1的信号处理方法，其中该方法由一特殊用途集成电路所执行。9. The signal processing method of claim 1, wherein the method is implemented by an application specific integrated circuit.
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US6894463B2 (en) * 2002-11-14 2005-05-17 Fyre Storm, Inc. Switching power converter controller configured to provide load shedding
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