CN101499482A - Nonvolatile memory and method of manufacturing the same - Google Patents
Nonvolatile memory and method of manufacturing the same Download PDFInfo
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- CN101499482A CN101499482A CNA2008100055032A CN200810005503A CN101499482A CN 101499482 A CN101499482 A CN 101499482A CN A2008100055032 A CNA2008100055032 A CN A2008100055032A CN 200810005503 A CN200810005503 A CN 200810005503A CN 101499482 A CN101499482 A CN 101499482A
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Abstract
The invention provides a nonvolatile memory, which comprises a diode and a memory cell. The diode comprises a doped region, a metal silicide layer and a patterned doped semiconductor layer. The doped region is disposed in the substrate and has a first conductivity type. The metal silicide layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on the metal silicide layer and has a second conductivity type. The memory unit is disposed on the substrate and coupled to the diode.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, more particularly, relate to a kind of nonvolatile memory and manufacture method thereof.
Background technology
Along with the extensive use with system product popularized of consumption electronic products, also more and more higher for the demand of memory with low-power consumption, low cost, high read/write speed, small size and high capacity density.In present memory, have the memory that a kind of resistivity by the change variable resistance layer is come record data, be to do one's utmost one of non-volatile memory device that develops at present.
Resistance-type memory (resistive random access memory, RRAM) be to utilize current impulse and apply changing voltage to change filminess, with in the conversion of carrying out based on different resistivity under the different states between set condition (set state) and the Reset Status (reset state) as variable resistance layer.This kind memory can have high density, low cost, low-power consumption and the advantage such as non-volatile of the high-speed and dynamic random access memory of static RAM simultaneously.
Fig. 1 is the generalized section of known a kind of resistance-type memory.What Figure 1A illustrated is the resistance-type memory 100 with diode 120 structures, and resistance-type memory 100 comprises bottom electrode 108, praseodymium calcium manganese oxygen (PrCaMnO, PCMO) layer 110 and top electrode 112 at least.Wherein, top electrode 112 is all platinum electrode with bottom electrode 108.Bottom electrode 108 is disposed on the P type heavily doped region 106 in the P type silicon base 102.Top electrode 112 is disposed at bottom electrode 108 tops.Praseodymium calcium manganese oxygen layer 110 is disposed between top electrode 112 and the bottom electrode 108, and praseodymium calcium manganese oxygen layer 110 can contact with top electrode 112, bottom electrode 108 respectively.In addition, in P type silicon base 102, can be formed with N type well region 104, and P type heavily doped region 106 can be configured in the N type well region 104.And the joint between P type heavily doped region 106 and N type well region 104 can be because of the conductivity of both materials the different diodes 120 that form.
Generally speaking, the formation method of P type heavily doped region 106 normally utilizes ion implantation that impurity is injected N type well region 104 earlier, continues afterwards to carry out the tempering process that the back ion injects and finish it again.Yet, carrying out the drawing process that the back ion injects, often may change because of inappropriate heat treatment causes the profile of P type heavily doped region 106, cause adjacent two P type heavily doped regions 106 electric connection to take place and cause problem of short-circuit.And, along with the fast development of semiconductor process techniques, requiring under the more and more high situation of element integrated level, the problems referred to above are more necessary to be much accounted of.
Summary of the invention
The invention provides a kind of nonvolatile memory, it has higher integrated level, and has lower resistivity (resistivity) and higher making current (turn-on current).
The present invention provides a kind of manufacture method of nonvolatile memory in addition, can form self aligned diode structure, and helps to form highdensity memory.
The present invention proposes a kind of nonvolatile memory, and it comprises diode and memory cell.Diode comprises doped region, metal silicide (silicide) layer and patterning doping semiconductor layer.Doped region is disposed in the substrate, and doped region is first conductivity type.Metal silicide layer is disposed in the substrate.And the patterning doping semiconductor layer is disposed on the metal silicide layer, and the patterning doping semiconductor layer is second conductivity type.Memory cell arrangements and couples with diode in substrate.
In an embodiment of the present invention, the material of above-mentioned metal silicide layer comprises titanium silicide (TiSi
2), cobalt silicide (CoSi
2), tungsten silicide (WSi
2) or nickle silicide (NiSi
2).
In an embodiment of the present invention, said memory cells is phase change memory cell (phase changememory cell, PCM cell) or resistance-type memory cell.
In an embodiment of the present invention, said memory cells comprise top electrode, and the bottom electrode that couples of patterning doping semiconductor layer and be disposed at top electrode and bottom electrode between variable resistance layer.
In an embodiment of the present invention, the material of above-mentioned variable resistance layer comprises chalcogen compound (chalcogenide) or metal oxide.
In an embodiment of the present invention, above-mentioned chalcogen compound comprise germanium antimony tellurium alloy (GeSbTe, GST).
In an embodiment of the present invention, memory cell also comprises heating electrode, is disposed between bottom electrode and the variable resistance layer.
In an embodiment of the present invention, nonvolatile memory also comprise the top electrode connector (topelectrode connector, TEC) and word line.The top electrode connector is disposed on the memory cell, and couples with top electrode.Word line is disposed on the memory cell, and links to each other with the top electrode connector.
In an embodiment of the present invention, also comprise well region, be disposed in the substrate that so that doped region is disposed in the well region, and substrate for example is first conductivity type, well region for example is second conductivity type.
In an embodiment of the present invention, above-mentioned substrate for example is second conductivity type.
In an embodiment of the present invention, the material of above-mentioned patterning doping semiconductor layer for example is a doped polycrystalline silicon.
The present invention proposes a kind of manufacture method of nonvolatile memory in addition.At first, provide substrate.Then, in substrate, form doped region, and doped region is first conductivity type.Afterwards, in substrate, form metal silicide layer.Continue it, on metal silicide layer, form the patterning doping semiconductor layer, and the patterning doping semiconductor layer is second conductivity type.Then, form memory cell in substrate, wherein memory cell and patterning doping semiconductor layer couple.
In an embodiment of the present invention, the material of above-mentioned metal silicide layer comprises titanium silicide (TiSi
2), cobalt silicide (CoSi
2), tungsten silicide (WSi
2) or nickle silicide (NiSi
2).
In an embodiment of the present invention, said memory cells is phase change memory cell or resistance-type memory cell.
In an embodiment of the present invention, the formation method of said memory cells for example is prior to forming bottom electrode in the substrate, bottom electrode and patterning doping semiconductor layer couple, and then form variable resistance layer on bottom electrode, form top electrode afterwards again on variable resistance layer.
In an embodiment of the present invention, the material of above-mentioned variable resistance layer comprises chalcogen compound or metal oxide.
In an embodiment of the present invention, above-mentioned chalcogen compound comprises germanium antimony tellurium alloy.
In an embodiment of the present invention, also be included between bottom electrode and the variable resistance layer and form heating electrode.
In an embodiment of the present invention, on be set forth in form top electrode after, also comprise forming the top electrode connector that couples with top electrode, and the word line that links to each other with the top electrode connector of formation.
In an embodiment of the present invention, also is included in and forms well region in the substrate, and doped region is disposed in the well region, and substrate for example is first conductivity type that well region for example is second conductivity type.
In an embodiment of the present invention, above-mentioned substrate for example is second conductivity type.
In an embodiment of the present invention, the material of above-mentioned patterning doping semiconductor layer for example is a doped polycrystalline silicon.
Nonvolatile memory of the present invention is because of having the vertical diode structure that is made of doped region, metal silicide layer and patterning doping semiconductor layer, and, therefore can reduce contact resistance and lift elements usefulness owing to can form different contact performances with doped region or the joint between metal silicide layer and patterning doping semiconductor layer at metal silicide layer.
In addition, therefore the manufacture method of nonvolatile memory of the present invention can form the diode of arranged perpendicular in self aligned mode by form the patterning doping semiconductor layer on metal silicide layer, and forms the memory with higher density.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the generalized section of known a kind of resistance-type memory.
Fig. 2 A to Fig. 2 D is the manufacturing process generalized section according to the nonvolatile memory of one embodiment of the invention.
Fig. 3 is the generalized section according to the nonvolatile memory of one embodiment of the invention.
Main description of reference numerals
100: resistance-type memory
102:P type silicon base
104:N type well region
106:P type heavily doped region
108,216: bottom electrode
110: praseodymium calcium manganese oxygen layer
112,226: top electrode
120,212,310: diode
200,300: substrate
202,302: well region
204,304: doped region
206,306: metal silicide layer
208,214,218: dielectric layer
210,308: the patterning doping semiconductor layer
220,320: memory cell
222: heating electrode
224: variable resistance layer
228: the top electrode connector
230,316: word line
232,318: contact hole
234,322: bit line
312,314: conductor layer
330: nonvolatile memory
Embodiment
Fig. 2 A to Fig. 2 D is the manufacturing process generalized section according to the nonvolatile memory of one embodiment of the invention.It is noted that, the manufacture method of the nonvolatile memory of the following stated only is to form a kind of in polytype nonvolatile memory, it mainly is in order to describe method of the present invention in detail in the making flow process that forms diode section, so that those skilled in the art can implement according to this, and be not in order to limit scope of the present invention.As for the configuration of other member such as memory cell, word line or bit line etc., generation type and order, all can be according to the fabrication techniques known to the those of ordinary skill in the affiliated technical field, and it is described to be not limited to the foregoing description.
Please refer to Fig. 2 A, substrate 200 is provided, it for example is a P type silicon base.Form well region 202 in substrate 200, it for example is a N type well region.The formation method of well region 202 for example is that ion implantation technology is carried out in substrate 200.Then, in substrate 200, form doped region 204, and doped region 204 is formed in the well region 202.Doped region 204 for example is a P type heavily doped region, and its formation method is for to carry out ion implantation technology to substrate 200.In addition, in another embodiment, also can not form well region in substrate, in the case, substrate for example is a N type silicon base, and doped region then is a P type heavily doped region.
Please continue A, in substrate 200, form layer of metal silicide layer 206 with reference to Fig. 2.The material of metal silicide layer 206 for example is titanium silicide (TiSi
2), cobalt silicide (CoSi
2), tungsten silicide (WSi
2), nickle silicide (NiSi
2) or other suitable metal silicide materials, and its formation method for example is physical vaporous deposition or chemical vapour deposition technique.
Please refer to Fig. 2 B, on metal silicide layer 206, form patterning doping semiconductor layer 210, and form the dielectric layer 208 that covers residual metallic silicide layer 206.The material of patterning doping semiconductor layer 210 for example is the polysilicon that injects or be doped with impurity through ion, and it is the heavily doped polysilicon of N type.The formation method of patterning doping semiconductor layer 210 can be to form earlier one dielectric layer 208 and one deck patterning photoresist layer (not illustrating) in substrate 200 in regular turn, be mask then with this patterning photoresist layer, remove the dielectric layer 208 of exposure, and form a plurality of openings that expose metal silicide layer 206, and after removing patterning photoresist layer, in opening, insert polycrystalline silicon material and form it through mixing.In another embodiment, the formation method of patterning doping semiconductor layer 210 also can be directly to form one deck doped polycrystalline silicon material layer on metal silicide layer 206, directly the doped polycrystalline silicon material layer is carried out photoetching process and etch process then, to define patterning doping semiconductor layer 210.
What specify is, be formed on doped region 204 in the substrate 200, be positioned in the substrate 200 patterning doping semiconductor layer 210 with can constitute a vertical diode 212 jointly between aforementioned metal silicide layer 206 between the two, and can improve component density, help to form highdensity memory.Because the metal silicide layer 206 that metal silicide materials constitutes has different work functions respectively with doped region 204, patterning doping semiconductor layer 210 that semi-conducting material constitutes, when metal silicide layer 206 contacts with doped region 204 or with patterning doping semiconductor layer 210, can be according to the conductivity (P type or N type) of semi-conducting material and form ohmic contact (Ohmic contact) or form Schottky diode (Schottky diode) at both contact-making surface.Shown in Fig. 2 B, in diode 212, can form ohmic contact at the face that connects of metal silicide layer 206 and the doped region 204 of P type, and can reduce contact resistance; Simultaneously, can form Schottky diode at the face that connects of metal silicide layer 206 and the patterning doping semiconductor layer 210 of N type, and can promote the element efficiency of diode 212.
In addition, in the above-described embodiments, be to be that example constitutes diode 212, but the present invention is not limited to this with doped region 204 that in the well region 202 of N type, forms the P type and the patterning doping semiconductor layer 210 that on metal silicide layer 206, forms the N type.Certainly, in other embodiments, the conductivity type of the conductivity type of the conductivity type of the conductivity type of substrate 200, well region 202, doped region 204, patterning doping semiconductor layer 210 can also be other combination, as long as make the metal silicide layer 206 and the face that connects of doped region 204 form ohmic contact, and the metal silicide layer 206 and the face that the connects formation Schottky diode of patterning doping semiconductor layer 210 are got final product, the visual process requirements of those skilled in the art is adjusted.
Please refer to Fig. 2 C, in substrate 200, form memory cell 220.Memory cell 220 for example is phase change memory cell, resistance-type memory cell or the memory cell of other kinds.In one embodiment, memory cell 220 comprises bottom electrode 216, variable resistance layer 224 and top electrode 226.Wherein, variable resistance layer 224 for example is to carry out phase change under different temperature, or can change its resistivity under different status conditions.Bottom electrode 216 can be formed on the patterning doping semiconductor layer 210, thereby can make memory cell 220 and patterning doping semiconductor layer 210 electric property couplings.
If with the phase change memory cell is example, memory cell 220 can form by following steps: form one dielectric layer 214 earlier on dielectric layer 208 and patterning doping semiconductor layer 210.Afterwards, in dielectric layer 214, form bottom electrode 216 again.The material of bottom electrode 216 for example is metal or other suitable electric conducting materials.Then, on dielectric layer 214 and bottom electrode 216, form another layer dielectric layer 218.Thereupon, in dielectric layer 218, form the opening (not indicating) that bottom-exposed goes out bottom electrode 216 surfaces.Then, in opening, form the heating electrode 222 that fills up this opening.The material of heating electrode 222 for example is a tungsten.Afterwards, on dielectric layer 218 and heating electrode 222, form one deck variable-resistance material layer (not illustrating) and one deck upper electrode material layer (not illustrating) in regular turn.The material of variable-resistance material layer for example is a chalcogen compound.Chalcogen compound can be the alloy that is mixed by germanium (germanium), antimony (antimony) and tellurium (tellurium), be called again germanium antimony tellurium alloy (GeSbTe, GST).And chalcogen compound can also be that silver indium antimony tellurium alloy (AgInSbTe), aluminium arsenic tellurium alloy (AlAsTe) or other contain the compound of any VI family element on the periodic table.And the material of upper electrode material layer for example is metal or other suitable electric conducting materials.Afterwards, patterning variable-resistance material layer and upper electrode material layer, and above heating electrode 222, form variable resistance layer 224 and top electrode 226.
From the above, in phase change memory cell, the heating electrode 222 that utilization is formed between bottom electrode 216 and the variable resistance layer 224 carries out heat effect, and the chalcogenide materials as variable resistance layer 224 is changed between crystalline state and amorphous state.At high temperature (for example above 600 ℃), chalcogen compound can become liquid state, in case and it cools down, then can be frozen into the amorphous glass attitude, have high electrical resistance.On the other hand, by chalcogen compound being heated to the temperature between its crystalline temperature and its fusing point, chalcogen compound can form the crystalline state of marshalling, and has lower resistance.So, utilize chalcogen compound under different temperatures, can have the characteristic of different resistance, can distinguish according to its resistance sizes, and as the basis of memory cell 220 storage datas.
Please refer to Fig. 2 D, in substrate 200, form top electrode connector 228 and word line 230.The material of top electrode connector 228 for example is a conductor material.Top electrode connector 228 for example links to each other with the top electrode 226 of memory cell 220.Word line 230 for example links to each other with top electrode connector 228.Thus, memory cell 220 just can electrically connect by top electrode connector 228 and word line 230.Afterwards, the contact hole 232 that forms bit line 234 and connect metal silicide layer 206 and bit line 234 in substrate 200 can be finished nonvolatile memory of the present invention.
Fig. 3 is the generalized section according to the nonvolatile memory of one embodiment of the invention.
Please refer to Fig. 3, nonvolatile memory 330 comprises diode 310 and memory cell 320.Memory cell 320 is disposed in the substrate 300, and couples with diode 310.
Memory cell 320 can be the memory cell of phase change memory cell, resistance-type memory cell or other kinds.Memory cell 320 for example is connected with patterning doping semiconductor layer 308 in the diode 310 by conductor layer 312.In one embodiment, memory cell 320 comprise top electrode (not illustrating), and the bottom electrode (not illustrating) that couples of patterning doping semiconductor layer 308 and be disposed at top electrode and bottom electrode between variable resistance layer (not illustrating).The material of variable resistance layer for example is chalcogen compound or metal oxide.With the phase change memory cell is example, for example is the alloy that is mixed by germanium (germanium), antimony (antimony) and tellurium (tellurium) as the chalcogen compound of variable resistor layer material, be called again germanium antimony tellurium alloy (GeSbTe, GST).In memory cell is under the situation of phase change memory cell, and memory cell also comprises heating electrode, is disposed between bottom electrode and the variable resistance layer, comes variable resistance layer is carried out heat effect.By heat effect the chalcogen compound occurrence temperature as variable resistance layer is changed, and make the ceaselessly conversion between crystalline state (crystalline state) and amorphous state (amorphous state) of this type of material, also can produce different resistivity and remember stored energy.Certainly, in other embodiments, memory cell 320 can also be the memory cell of other kinds, and the present invention does not do any qualification in this.
In addition, in nonvolatile memory 330, also comprise word line 316 and bit line 322, be disposed at the top of memory cell 320.Wherein, word line 316 for example electrically connects by conductor layer 314 and memory cell 320, and bit line 322 for example electrically connects by contact hole 318 and metal silicide layer 306.In one embodiment, when memory cell 320 was memory cell for phase change memory cell or resistance, conductor layer 314 can be the top electrode connector, so that the top electrode of memory cell 320 and word line 316 couple.
What deserves to be mentioned is that the diode 310 that is made of doped region 304, metal silicide layer 306 and patterning doping semiconductor layer 308 is to dispose with the form perpendicular to substrate 300 surfaces, therefore can increase the element integrated level.In addition, metal silicide layer 306 is formed by metal silicide materials, and doped region 304, patterning doping semiconductor layer 308 all are made up of semi-conducting material, because metal silicide materials has different material behaviors with semi-conducting material, therefore the special face that connects characteristic can appear in the joint at two kinds of different materials.For instance, the joint between the doped region 304 of metal silicide layer 306 and P type can form ohmic contact (Ohmic contact), can reduce the generation of contact resistance, and reduces resistivity.On the other hand, joint between the patterning doping semiconductor layer 308 of metal silicide layer 306 and N type then can form Schottky diode (Schottky diode), and have lower forward drop (forward voltage drop), and then lift elements usefulness.
In the above-described embodiments, be the doped region 304 that disposes the P type respectively with both sides and the patterning doping semiconductor layer 308 of N type is the diode that example illustrates nonvolatile memory of the present invention, but the present invention is not limited to this at metal silicide layer 306.In another embodiment, the conductivity type of the conductivity type of the conductivity type of the conductivity type of substrate 300, well region 302, doped region 304, patterning doping semiconductor layer 308 can also be other combination, as long as can make the metal silicide layer 306 and the face that connects of doped region 304 form ohmic contact, and the metal silicide layer 306 and the face that the connects formation Schottky diode of patterning doping semiconductor layer 308 are got final product.Certainly, in other embodiments, can also not form well region, and directly form doped region in substrate, the visual process requirements of those skilled in the art is adjusted.
In sum, nonvolatile memory of the present invention and manufacture method thereof have following advantage at least:
1. in nonvolatile memory of the present invention and manufacture method thereof, its diode structure is to adopt two connecing face and dispose the semi-conducting material of different conductivity types and form ohmic contact and Schottky diode respectively up and down at metal silicide layer, therefore can reduce resistivity, and effective lift elements usefulness.
2. in nonvolatile memory of the present invention and manufacture method thereof, because of forming diode structure perpendicular to substrate surface, just the contact-making surface at patterning doping semiconductor layer and metal silicide layer promptly constitutes diode, therefore can form self aligned structure, and form highdensity memory.
3. nonvolatile memory of the present invention can create by simple process steps, and has better simply circuit design, therefore can help to reduce the technology cost.
Though the present invention discloses as above with preferred embodiment; but it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; change and retouching when carrying out some, thus protection scope of the present invention when with appended claim the person of being defined be as the criterion.
Claims (22)
1. nonvolatile memory comprises:
Diode comprises:
Doped region is disposed in the substrate, and this doped region is first conduction type;
Metal silicide layer is disposed in this substrate; And
The patterning doping semiconductor layer is disposed on this metal silicide layer, and this patterning doping semiconductor layer is second conduction type; And
Memory cell is disposed in this substrate, and this memory cell and this diode couple.
2. nonvolatile memory according to claim 1, wherein the material of this metal silicide layer comprises titanium silicide, cobalt silicide, tungsten silicide or nickle silicide.
3. nonvolatile memory according to claim 1, wherein this memory cell is phase change memory cell or resistance-type memory cell.
4. nonvolatile memory according to claim 3, wherein this memory cell comprises:
Top electrode;
Bottom electrode, this bottom electrode and this patterning doping semiconductor layer couple; And
Variable resistance layer is disposed between this top electrode and this bottom electrode.
5. nonvolatile memory according to claim 4, wherein the material of this variable resistance layer comprises chalcogen compound or metal oxide.
6. the manufacture method of nonvolatile memory according to claim 5, wherein this chalcogen compound comprises germanium antimony tellurium alloy.
7. nonvolatile memory according to claim 4, this memory cell also comprises heating electrode, is disposed between this bottom electrode and this variable resistance layer.
8. nonvolatile memory according to claim 4 also comprises:
The top electrode connector is disposed on this memory cell, and this top electrode connector and this top electrode couple; And
Word line is disposed on this memory cell, and this word line links to each other with this top electrode connector.
9. nonvolatile memory according to claim 1 also comprises well region, is disposed in this substrate, so that this doped region is disposed in this well region, and this substrate is this first conduction type, and this well region is this second conduction type.
10. nonvolatile memory according to claim 1, wherein this substrate is this second conduction type.
11. nonvolatile memory according to claim 1, wherein the material of this patterning doping semiconductor layer is a doped polycrystalline silicon.
12. the manufacture method of a nonvolatile memory comprises:
Substrate is provided;
In this substrate, form doped region, and this doped region is first conduction type;
In this substrate, form metal silicide layer;
On this metal silicide layer, form the patterning doping semiconductor layer, and this patterning doping semiconductor layer is second conduction type; And
Form memory cell in this substrate, wherein this memory cell and this patterning doping semiconductor layer couple.
13. the manufacture method of nonvolatile memory according to claim 12, wherein the material of this metal silicide layer comprises titanium silicide, cobalt silicide, tungsten silicide or nickle silicide.
14. the manufacture method of nonvolatile memory according to claim 12, wherein this memory cell is phase change memory cell or resistance-type memory cell.
15. the manufacture method of nonvolatile memory according to claim 14, wherein the formation method of this memory cell comprises:
Form bottom electrode in this substrate, this bottom electrode and this patterning doping semiconductor layer couple;
On this bottom electrode, form variable resistance layer; And
On this variable resistance layer, form top electrode
16. the manufacture method of nonvolatile memory according to claim 15, wherein the material of this variable resistance layer comprises chalcogen compound or metal oxide.
17. the manufacture method of nonvolatile memory according to claim 16, wherein this chalcogen compound comprises germanium antimony tellurium alloy.
18. the manufacture method of nonvolatile memory according to claim 15 also is included between this bottom electrode and this variable resistance layer and forms heating electrode.
19. the manufacture method of nonvolatile memory according to claim 15 wherein after forming this top electrode, also comprises:
Form the top electrode connector, this top electrode connector and this top electrode couple; And
Form word line, this word line links to each other with this top electrode connector.
20. the manufacture method of nonvolatile memory according to claim 12 also is included in this substrate and forms well region, and this doped region is disposed in this well region, and this substrate is this first conduction type, this well region is this second conduction type.
21. the manufacture method of nonvolatile memory according to claim 12, wherein this substrate is this second conduction type.
22. the manufacture method of nonvolatile memory according to claim 12, wherein the material of this patterning doping semiconductor layer is a doped polycrystalline silicon.
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|---|---|---|---|
| CNA2008100055032A CN101499482A (en) | 2008-02-03 | 2008-02-03 | Nonvolatile memory and method of manufacturing the same |
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|---|---|---|---|
| CNA2008100055032A CN101499482A (en) | 2008-02-03 | 2008-02-03 | Nonvolatile memory and method of manufacturing the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106796374A (en) * | 2014-10-09 | 2017-05-31 | 剑桥企业有限公司 | Liquid-crystal apparatus |
| CN113078625A (en) * | 2021-03-24 | 2021-07-06 | 重庆邮电大学 | Surge protection array based on chalcogenide compound and preparation method |
-
2008
- 2008-02-03 CN CNA2008100055032A patent/CN101499482A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106796374A (en) * | 2014-10-09 | 2017-05-31 | 剑桥企业有限公司 | Liquid-crystal apparatus |
| CN113078625A (en) * | 2021-03-24 | 2021-07-06 | 重庆邮电大学 | Surge protection array based on chalcogenide compound and preparation method |
| CN113078625B (en) * | 2021-03-24 | 2023-02-17 | 重庆邮电大学 | Surge protection array based on chalcogenide compound and preparation method |
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Open date: 20090805 |